Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * NVM Express device driver |
Matthew Wilcox | 8757ad6 | 2014-04-11 10:37:39 -0400 | [diff] [blame] | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | /* |
| 16 | * Refer to the SCSI-NVMe Translation spec for details on how |
| 17 | * each command is translated. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/nvme.h> |
| 21 | #include <linux/bio.h> |
| 22 | #include <linux/bitops.h> |
| 23 | #include <linux/blkdev.h> |
Keith Busch | 320a382 | 2013-10-23 13:07:34 -0600 | [diff] [blame] | 24 | #include <linux/compat.h> |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 25 | #include <linux/delay.h> |
| 26 | #include <linux/errno.h> |
| 27 | #include <linux/fs.h> |
| 28 | #include <linux/genhd.h> |
| 29 | #include <linux/idr.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/io.h> |
| 33 | #include <linux/kdev_t.h> |
| 34 | #include <linux/kthread.h> |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/mm.h> |
| 37 | #include <linux/module.h> |
| 38 | #include <linux/moduleparam.h> |
| 39 | #include <linux/pci.h> |
| 40 | #include <linux/poison.h> |
| 41 | #include <linux/sched.h> |
| 42 | #include <linux/slab.h> |
| 43 | #include <linux/types.h> |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 44 | #include <scsi/sg.h> |
| 45 | #include <scsi/scsi.h> |
| 46 | |
| 47 | |
| 48 | static int sg_version_num = 30534; /* 2 digits for each component */ |
| 49 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 50 | /* VPD Page Codes */ |
| 51 | #define VPD_SUPPORTED_PAGES 0x00 |
| 52 | #define VPD_SERIAL_NUMBER 0x80 |
| 53 | #define VPD_DEVICE_IDENTIFIERS 0x83 |
| 54 | #define VPD_EXTENDED_INQUIRY 0x86 |
Keith Busch | 7f749d9 | 2015-04-07 15:34:18 -0600 | [diff] [blame] | 55 | #define VPD_BLOCK_LIMITS 0xB0 |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 56 | #define VPD_BLOCK_DEV_CHARACTERISTICS 0xB1 |
| 57 | |
| 58 | /* CDB offsets */ |
| 59 | #define REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET 6 |
| 60 | #define REPORT_LUNS_SR_OFFSET 2 |
| 61 | #define READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET 10 |
| 62 | #define REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET 4 |
| 63 | #define REQUEST_SENSE_DESC_OFFSET 1 |
| 64 | #define REQUEST_SENSE_DESC_MASK 0x01 |
| 65 | #define DESCRIPTOR_FORMAT_SENSE_DATA_TYPE 1 |
| 66 | #define INQUIRY_EVPD_BYTE_OFFSET 1 |
| 67 | #define INQUIRY_PAGE_CODE_BYTE_OFFSET 2 |
| 68 | #define INQUIRY_EVPD_BIT_MASK 1 |
| 69 | #define INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET 3 |
| 70 | #define START_STOP_UNIT_CDB_IMMED_OFFSET 1 |
| 71 | #define START_STOP_UNIT_CDB_IMMED_MASK 0x1 |
| 72 | #define START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET 3 |
| 73 | #define START_STOP_UNIT_CDB_POWER_COND_MOD_MASK 0xF |
| 74 | #define START_STOP_UNIT_CDB_POWER_COND_OFFSET 4 |
| 75 | #define START_STOP_UNIT_CDB_POWER_COND_MASK 0xF0 |
| 76 | #define START_STOP_UNIT_CDB_NO_FLUSH_OFFSET 4 |
| 77 | #define START_STOP_UNIT_CDB_NO_FLUSH_MASK 0x4 |
| 78 | #define START_STOP_UNIT_CDB_START_OFFSET 4 |
| 79 | #define START_STOP_UNIT_CDB_START_MASK 0x1 |
| 80 | #define WRITE_BUFFER_CDB_MODE_OFFSET 1 |
| 81 | #define WRITE_BUFFER_CDB_MODE_MASK 0x1F |
| 82 | #define WRITE_BUFFER_CDB_BUFFER_ID_OFFSET 2 |
| 83 | #define WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET 3 |
| 84 | #define WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET 6 |
| 85 | #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET 1 |
| 86 | #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK 0xC0 |
| 87 | #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT 6 |
| 88 | #define FORMAT_UNIT_CDB_LONG_LIST_OFFSET 1 |
| 89 | #define FORMAT_UNIT_CDB_LONG_LIST_MASK 0x20 |
| 90 | #define FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET 1 |
| 91 | #define FORMAT_UNIT_CDB_FORMAT_DATA_MASK 0x10 |
| 92 | #define FORMAT_UNIT_SHORT_PARM_LIST_LEN 4 |
| 93 | #define FORMAT_UNIT_LONG_PARM_LIST_LEN 8 |
| 94 | #define FORMAT_UNIT_PROT_INT_OFFSET 3 |
| 95 | #define FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET 0 |
| 96 | #define FORMAT_UNIT_PROT_FIELD_USAGE_MASK 0x07 |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 97 | #define UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET 7 |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 98 | |
| 99 | /* Misc. defines */ |
| 100 | #define NIBBLE_SHIFT 4 |
| 101 | #define FIXED_SENSE_DATA 0x70 |
| 102 | #define DESC_FORMAT_SENSE_DATA 0x72 |
| 103 | #define FIXED_SENSE_DATA_ADD_LENGTH 10 |
| 104 | #define LUN_ENTRY_SIZE 8 |
| 105 | #define LUN_DATA_HEADER_SIZE 8 |
| 106 | #define ALL_LUNS_RETURNED 0x02 |
| 107 | #define ALL_WELL_KNOWN_LUNS_RETURNED 0x01 |
| 108 | #define RESTRICTED_LUNS_RETURNED 0x00 |
| 109 | #define NVME_POWER_STATE_START_VALID 0x00 |
| 110 | #define NVME_POWER_STATE_ACTIVE 0x01 |
| 111 | #define NVME_POWER_STATE_IDLE 0x02 |
| 112 | #define NVME_POWER_STATE_STANDBY 0x03 |
| 113 | #define NVME_POWER_STATE_LU_CONTROL 0x07 |
| 114 | #define POWER_STATE_0 0 |
| 115 | #define POWER_STATE_1 1 |
| 116 | #define POWER_STATE_2 2 |
| 117 | #define POWER_STATE_3 3 |
| 118 | #define DOWNLOAD_SAVE_ACTIVATE 0x05 |
| 119 | #define DOWNLOAD_SAVE_DEFER_ACTIVATE 0x0E |
| 120 | #define ACTIVATE_DEFERRED_MICROCODE 0x0F |
| 121 | #define FORMAT_UNIT_IMMED_MASK 0x2 |
| 122 | #define FORMAT_UNIT_IMMED_OFFSET 1 |
| 123 | #define KELVIN_TEMP_FACTOR 273 |
| 124 | #define FIXED_FMT_SENSE_DATA_SIZE 18 |
| 125 | #define DESC_FMT_SENSE_DATA_SIZE 8 |
| 126 | |
| 127 | /* SCSI/NVMe defines and bit masks */ |
| 128 | #define INQ_STANDARD_INQUIRY_PAGE 0x00 |
| 129 | #define INQ_SUPPORTED_VPD_PAGES_PAGE 0x00 |
| 130 | #define INQ_UNIT_SERIAL_NUMBER_PAGE 0x80 |
| 131 | #define INQ_DEVICE_IDENTIFICATION_PAGE 0x83 |
| 132 | #define INQ_EXTENDED_INQUIRY_DATA_PAGE 0x86 |
Keith Busch | 7f749d9 | 2015-04-07 15:34:18 -0600 | [diff] [blame] | 133 | #define INQ_BDEV_LIMITS_PAGE 0xB0 |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 134 | #define INQ_BDEV_CHARACTERISTICS_PAGE 0xB1 |
| 135 | #define INQ_SERIAL_NUMBER_LENGTH 0x14 |
Keith Busch | 7f749d9 | 2015-04-07 15:34:18 -0600 | [diff] [blame] | 136 | #define INQ_NUM_SUPPORTED_VPD_PAGES 6 |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 137 | #define VERSION_SPC_4 0x06 |
| 138 | #define ACA_UNSUPPORTED 0 |
| 139 | #define STANDARD_INQUIRY_LENGTH 36 |
| 140 | #define ADDITIONAL_STD_INQ_LENGTH 31 |
| 141 | #define EXTENDED_INQUIRY_DATA_PAGE_LENGTH 0x3C |
| 142 | #define RESERVED_FIELD 0 |
| 143 | |
| 144 | /* SCSI READ/WRITE Defines */ |
| 145 | #define IO_CDB_WP_MASK 0xE0 |
| 146 | #define IO_CDB_WP_SHIFT 5 |
| 147 | #define IO_CDB_FUA_MASK 0x8 |
| 148 | #define IO_6_CDB_LBA_OFFSET 0 |
| 149 | #define IO_6_CDB_LBA_MASK 0x001FFFFF |
| 150 | #define IO_6_CDB_TX_LEN_OFFSET 4 |
| 151 | #define IO_6_DEFAULT_TX_LEN 256 |
| 152 | #define IO_10_CDB_LBA_OFFSET 2 |
| 153 | #define IO_10_CDB_TX_LEN_OFFSET 7 |
| 154 | #define IO_10_CDB_WP_OFFSET 1 |
| 155 | #define IO_10_CDB_FUA_OFFSET 1 |
| 156 | #define IO_12_CDB_LBA_OFFSET 2 |
| 157 | #define IO_12_CDB_TX_LEN_OFFSET 6 |
| 158 | #define IO_12_CDB_WP_OFFSET 1 |
| 159 | #define IO_12_CDB_FUA_OFFSET 1 |
| 160 | #define IO_16_CDB_FUA_OFFSET 1 |
| 161 | #define IO_16_CDB_WP_OFFSET 1 |
| 162 | #define IO_16_CDB_LBA_OFFSET 2 |
| 163 | #define IO_16_CDB_TX_LEN_OFFSET 10 |
| 164 | |
| 165 | /* Mode Sense/Select defines */ |
| 166 | #define MODE_PAGE_INFO_EXCEP 0x1C |
| 167 | #define MODE_PAGE_CACHING 0x08 |
| 168 | #define MODE_PAGE_CONTROL 0x0A |
| 169 | #define MODE_PAGE_POWER_CONDITION 0x1A |
| 170 | #define MODE_PAGE_RETURN_ALL 0x3F |
| 171 | #define MODE_PAGE_BLK_DES_LEN 0x08 |
| 172 | #define MODE_PAGE_LLBAA_BLK_DES_LEN 0x10 |
| 173 | #define MODE_PAGE_CACHING_LEN 0x14 |
| 174 | #define MODE_PAGE_CONTROL_LEN 0x0C |
| 175 | #define MODE_PAGE_POW_CND_LEN 0x28 |
| 176 | #define MODE_PAGE_INF_EXC_LEN 0x0C |
| 177 | #define MODE_PAGE_ALL_LEN 0x54 |
| 178 | #define MODE_SENSE6_MPH_SIZE 4 |
| 179 | #define MODE_SENSE6_ALLOC_LEN_OFFSET 4 |
| 180 | #define MODE_SENSE_PAGE_CONTROL_OFFSET 2 |
| 181 | #define MODE_SENSE_PAGE_CONTROL_MASK 0xC0 |
| 182 | #define MODE_SENSE_PAGE_CODE_OFFSET 2 |
| 183 | #define MODE_SENSE_PAGE_CODE_MASK 0x3F |
| 184 | #define MODE_SENSE_LLBAA_OFFSET 1 |
| 185 | #define MODE_SENSE_LLBAA_MASK 0x10 |
| 186 | #define MODE_SENSE_LLBAA_SHIFT 4 |
| 187 | #define MODE_SENSE_DBD_OFFSET 1 |
| 188 | #define MODE_SENSE_DBD_MASK 8 |
| 189 | #define MODE_SENSE_DBD_SHIFT 3 |
| 190 | #define MODE_SENSE10_MPH_SIZE 8 |
| 191 | #define MODE_SENSE10_ALLOC_LEN_OFFSET 7 |
| 192 | #define MODE_SELECT_CDB_PAGE_FORMAT_OFFSET 1 |
| 193 | #define MODE_SELECT_CDB_SAVE_PAGES_OFFSET 1 |
| 194 | #define MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET 4 |
| 195 | #define MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET 7 |
| 196 | #define MODE_SELECT_CDB_PAGE_FORMAT_MASK 0x10 |
| 197 | #define MODE_SELECT_CDB_SAVE_PAGES_MASK 0x1 |
| 198 | #define MODE_SELECT_6_BD_OFFSET 3 |
| 199 | #define MODE_SELECT_10_BD_OFFSET 6 |
| 200 | #define MODE_SELECT_10_LLBAA_OFFSET 4 |
| 201 | #define MODE_SELECT_10_LLBAA_MASK 1 |
| 202 | #define MODE_SELECT_6_MPH_SIZE 4 |
| 203 | #define MODE_SELECT_10_MPH_SIZE 8 |
| 204 | #define CACHING_MODE_PAGE_WCE_MASK 0x04 |
| 205 | #define MODE_SENSE_BLK_DESC_ENABLED 0 |
| 206 | #define MODE_SENSE_BLK_DESC_COUNT 1 |
| 207 | #define MODE_SELECT_PAGE_CODE_MASK 0x3F |
| 208 | #define SHORT_DESC_BLOCK 8 |
| 209 | #define LONG_DESC_BLOCK 16 |
| 210 | #define MODE_PAGE_POW_CND_LEN_FIELD 0x26 |
| 211 | #define MODE_PAGE_INF_EXC_LEN_FIELD 0x0A |
| 212 | #define MODE_PAGE_CACHING_LEN_FIELD 0x12 |
| 213 | #define MODE_PAGE_CONTROL_LEN_FIELD 0x0A |
| 214 | #define MODE_SENSE_PC_CURRENT_VALUES 0 |
| 215 | |
| 216 | /* Log Sense defines */ |
| 217 | #define LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE 0x00 |
| 218 | #define LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH 0x07 |
| 219 | #define LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE 0x2F |
| 220 | #define LOG_PAGE_TEMPERATURE_PAGE 0x0D |
| 221 | #define LOG_SENSE_CDB_SP_OFFSET 1 |
| 222 | #define LOG_SENSE_CDB_SP_NOT_ENABLED 0 |
| 223 | #define LOG_SENSE_CDB_PC_OFFSET 2 |
| 224 | #define LOG_SENSE_CDB_PC_MASK 0xC0 |
| 225 | #define LOG_SENSE_CDB_PC_SHIFT 6 |
| 226 | #define LOG_SENSE_CDB_PC_CUMULATIVE_VALUES 1 |
| 227 | #define LOG_SENSE_CDB_PAGE_CODE_MASK 0x3F |
| 228 | #define LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET 7 |
| 229 | #define REMAINING_INFO_EXCP_PAGE_LENGTH 0x8 |
| 230 | #define LOG_INFO_EXCP_PAGE_LENGTH 0xC |
| 231 | #define REMAINING_TEMP_PAGE_LENGTH 0xC |
| 232 | #define LOG_TEMP_PAGE_LENGTH 0x10 |
| 233 | #define LOG_TEMP_UNKNOWN 0xFF |
| 234 | #define SUPPORTED_LOG_PAGES_PAGE_LENGTH 0x3 |
| 235 | |
| 236 | /* Read Capacity defines */ |
| 237 | #define READ_CAP_10_RESP_SIZE 8 |
| 238 | #define READ_CAP_16_RESP_SIZE 32 |
| 239 | |
| 240 | /* NVMe Namespace and Command Defines */ |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 241 | #define BYTES_TO_DWORDS 4 |
| 242 | #define NVME_MAX_FIRMWARE_SLOT 7 |
| 243 | |
| 244 | /* Report LUNs defines */ |
| 245 | #define REPORT_LUNS_FIRST_LUN_OFFSET 8 |
| 246 | |
| 247 | /* SCSI ADDITIONAL SENSE Codes */ |
| 248 | |
| 249 | #define SCSI_ASC_NO_SENSE 0x00 |
| 250 | #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03 |
| 251 | #define SCSI_ASC_LUN_NOT_READY 0x04 |
| 252 | #define SCSI_ASC_WARNING 0x0B |
| 253 | #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10 |
| 254 | #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10 |
| 255 | #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10 |
| 256 | #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11 |
| 257 | #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D |
| 258 | #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20 |
| 259 | #define SCSI_ASC_ILLEGAL_COMMAND 0x20 |
| 260 | #define SCSI_ASC_ILLEGAL_BLOCK 0x21 |
| 261 | #define SCSI_ASC_INVALID_CDB 0x24 |
| 262 | #define SCSI_ASC_INVALID_LUN 0x25 |
| 263 | #define SCSI_ASC_INVALID_PARAMETER 0x26 |
| 264 | #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31 |
| 265 | #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44 |
| 266 | |
| 267 | /* SCSI ADDITIONAL SENSE Code Qualifiers */ |
| 268 | |
| 269 | #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00 |
| 270 | #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01 |
| 271 | #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01 |
| 272 | #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02 |
| 273 | #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03 |
| 274 | #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04 |
| 275 | #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08 |
| 276 | #define SCSI_ASCQ_INVALID_LUN_ID 0x09 |
| 277 | |
| 278 | /** |
| 279 | * DEVICE_SPECIFIC_PARAMETER in mode parameter header (see sbc2r16) to |
| 280 | * enable DPOFUA support type 0x10 value. |
| 281 | */ |
| 282 | #define DEVICE_SPECIFIC_PARAMETER 0 |
| 283 | #define VPD_ID_DESCRIPTOR_LENGTH sizeof(VPD_IDENTIFICATION_DESCRIPTOR) |
| 284 | |
| 285 | /* MACROs to extract information from CDBs */ |
| 286 | |
| 287 | #define GET_OPCODE(cdb) cdb[0] |
| 288 | |
| 289 | #define GET_U8_FROM_CDB(cdb, index) (cdb[index] << 0) |
| 290 | |
| 291 | #define GET_U16_FROM_CDB(cdb, index) ((cdb[index] << 8) | (cdb[index + 1] << 0)) |
| 292 | |
| 293 | #define GET_U24_FROM_CDB(cdb, index) ((cdb[index] << 16) | \ |
| 294 | (cdb[index + 1] << 8) | \ |
| 295 | (cdb[index + 2] << 0)) |
| 296 | |
| 297 | #define GET_U32_FROM_CDB(cdb, index) ((cdb[index] << 24) | \ |
| 298 | (cdb[index + 1] << 16) | \ |
| 299 | (cdb[index + 2] << 8) | \ |
| 300 | (cdb[index + 3] << 0)) |
| 301 | |
| 302 | #define GET_U64_FROM_CDB(cdb, index) ((((u64)cdb[index]) << 56) | \ |
| 303 | (((u64)cdb[index + 1]) << 48) | \ |
| 304 | (((u64)cdb[index + 2]) << 40) | \ |
| 305 | (((u64)cdb[index + 3]) << 32) | \ |
| 306 | (((u64)cdb[index + 4]) << 24) | \ |
| 307 | (((u64)cdb[index + 5]) << 16) | \ |
| 308 | (((u64)cdb[index + 6]) << 8) | \ |
| 309 | (((u64)cdb[index + 7]) << 0)) |
| 310 | |
| 311 | /* Inquiry Helper Macros */ |
| 312 | #define GET_INQ_EVPD_BIT(cdb) \ |
| 313 | ((GET_U8_FROM_CDB(cdb, INQUIRY_EVPD_BYTE_OFFSET) & \ |
| 314 | INQUIRY_EVPD_BIT_MASK) ? 1 : 0) |
| 315 | |
| 316 | #define GET_INQ_PAGE_CODE(cdb) \ |
| 317 | (GET_U8_FROM_CDB(cdb, INQUIRY_PAGE_CODE_BYTE_OFFSET)) |
| 318 | |
| 319 | #define GET_INQ_ALLOC_LENGTH(cdb) \ |
| 320 | (GET_U16_FROM_CDB(cdb, INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET)) |
| 321 | |
| 322 | /* Report LUNs Helper Macros */ |
| 323 | #define GET_REPORT_LUNS_ALLOC_LENGTH(cdb) \ |
| 324 | (GET_U32_FROM_CDB(cdb, REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET)) |
| 325 | |
| 326 | /* Read Capacity Helper Macros */ |
| 327 | #define GET_READ_CAP_16_ALLOC_LENGTH(cdb) \ |
| 328 | (GET_U32_FROM_CDB(cdb, READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET)) |
| 329 | |
| 330 | #define IS_READ_CAP_16(cdb) \ |
Hannes Reinecke | eb846d9 | 2014-11-17 14:25:19 +0100 | [diff] [blame] | 331 | ((cdb[0] == SERVICE_ACTION_IN_16 && cdb[1] == SAI_READ_CAPACITY_16) ? 1 : 0) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 332 | |
| 333 | /* Request Sense Helper Macros */ |
| 334 | #define GET_REQUEST_SENSE_ALLOC_LENGTH(cdb) \ |
| 335 | (GET_U8_FROM_CDB(cdb, REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET)) |
| 336 | |
| 337 | /* Mode Sense Helper Macros */ |
| 338 | #define GET_MODE_SENSE_DBD(cdb) \ |
| 339 | ((GET_U8_FROM_CDB(cdb, MODE_SENSE_DBD_OFFSET) & MODE_SENSE_DBD_MASK) >> \ |
| 340 | MODE_SENSE_DBD_SHIFT) |
| 341 | |
| 342 | #define GET_MODE_SENSE_LLBAA(cdb) \ |
| 343 | ((GET_U8_FROM_CDB(cdb, MODE_SENSE_LLBAA_OFFSET) & \ |
| 344 | MODE_SENSE_LLBAA_MASK) >> MODE_SENSE_LLBAA_SHIFT) |
| 345 | |
| 346 | #define GET_MODE_SENSE_MPH_SIZE(cdb10) \ |
| 347 | (cdb10 ? MODE_SENSE10_MPH_SIZE : MODE_SENSE6_MPH_SIZE) |
| 348 | |
| 349 | |
| 350 | /* Struct to gather data that needs to be extracted from a SCSI CDB. |
| 351 | Not conforming to any particular CDB variant, but compatible with all. */ |
| 352 | |
| 353 | struct nvme_trans_io_cdb { |
| 354 | u8 fua; |
| 355 | u8 prot_info; |
| 356 | u64 lba; |
| 357 | u32 xfer_len; |
| 358 | }; |
| 359 | |
| 360 | |
| 361 | /* Internal Helper Functions */ |
| 362 | |
| 363 | |
| 364 | /* Copy data to userspace memory */ |
| 365 | |
| 366 | static int nvme_trans_copy_to_user(struct sg_io_hdr *hdr, void *from, |
| 367 | unsigned long n) |
| 368 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 369 | int i; |
| 370 | void *index = from; |
| 371 | size_t remaining = n; |
| 372 | size_t xfer_len; |
| 373 | |
| 374 | if (hdr->iovec_count > 0) { |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 375 | struct sg_iovec sgl; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 376 | |
| 377 | for (i = 0; i < hdr->iovec_count; i++) { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 378 | if (copy_from_user(&sgl, hdr->dxferp + |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 379 | i * sizeof(struct sg_iovec), |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 380 | sizeof(struct sg_iovec))) |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 381 | return -EFAULT; |
| 382 | xfer_len = min(remaining, sgl.iov_len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 383 | if (copy_to_user(sgl.iov_base, index, xfer_len)) |
| 384 | return -EFAULT; |
| 385 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 386 | index += xfer_len; |
| 387 | remaining -= xfer_len; |
| 388 | if (remaining == 0) |
| 389 | break; |
| 390 | } |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 391 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 392 | } |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 393 | |
| 394 | if (copy_to_user(hdr->dxferp, from, n)) |
| 395 | return -EFAULT; |
| 396 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | /* Copy data from userspace memory */ |
| 400 | |
| 401 | static int nvme_trans_copy_from_user(struct sg_io_hdr *hdr, void *to, |
| 402 | unsigned long n) |
| 403 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 404 | int i; |
| 405 | void *index = to; |
| 406 | size_t remaining = n; |
| 407 | size_t xfer_len; |
| 408 | |
| 409 | if (hdr->iovec_count > 0) { |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 410 | struct sg_iovec sgl; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 411 | |
| 412 | for (i = 0; i < hdr->iovec_count; i++) { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 413 | if (copy_from_user(&sgl, hdr->dxferp + |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 414 | i * sizeof(struct sg_iovec), |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 415 | sizeof(struct sg_iovec))) |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 416 | return -EFAULT; |
| 417 | xfer_len = min(remaining, sgl.iov_len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 418 | if (copy_from_user(index, sgl.iov_base, xfer_len)) |
| 419 | return -EFAULT; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 420 | index += xfer_len; |
| 421 | remaining -= xfer_len; |
| 422 | if (remaining == 0) |
| 423 | break; |
| 424 | } |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 425 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 426 | } |
| 427 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 428 | if (copy_from_user(to, hdr->dxferp, n)) |
| 429 | return -EFAULT; |
| 430 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | /* Status/Sense Buffer Writeback */ |
| 434 | |
| 435 | static int nvme_trans_completion(struct sg_io_hdr *hdr, u8 status, u8 sense_key, |
| 436 | u8 asc, u8 ascq) |
| 437 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 438 | u8 xfer_len; |
| 439 | u8 resp[DESC_FMT_SENSE_DATA_SIZE]; |
| 440 | |
| 441 | if (scsi_status_is_good(status)) { |
| 442 | hdr->status = SAM_STAT_GOOD; |
| 443 | hdr->masked_status = GOOD; |
| 444 | hdr->host_status = DID_OK; |
| 445 | hdr->driver_status = DRIVER_OK; |
| 446 | hdr->sb_len_wr = 0; |
| 447 | } else { |
| 448 | hdr->status = status; |
| 449 | hdr->masked_status = status >> 1; |
| 450 | hdr->host_status = DID_OK; |
| 451 | hdr->driver_status = DRIVER_OK; |
| 452 | |
| 453 | memset(resp, 0, DESC_FMT_SENSE_DATA_SIZE); |
| 454 | resp[0] = DESC_FORMAT_SENSE_DATA; |
| 455 | resp[1] = sense_key; |
| 456 | resp[2] = asc; |
| 457 | resp[3] = ascq; |
| 458 | |
| 459 | xfer_len = min_t(u8, hdr->mx_sb_len, DESC_FMT_SENSE_DATA_SIZE); |
| 460 | hdr->sb_len_wr = xfer_len; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 461 | if (copy_to_user(hdr->sbp, resp, xfer_len) > 0) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 462 | return -EFAULT; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 463 | } |
| 464 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 465 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 466 | } |
| 467 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 468 | /* |
| 469 | * Take a status code from a lowlevel routine, and if it was a positive NVMe |
| 470 | * error code update the sense data based on it. In either case the passed |
| 471 | * in value is returned again, unless an -EFAULT from copy_to_user overrides |
| 472 | * it. |
| 473 | */ |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 474 | static int nvme_trans_status_code(struct sg_io_hdr *hdr, int nvme_sc) |
| 475 | { |
| 476 | u8 status, sense_key, asc, ascq; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 477 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 478 | |
| 479 | /* For non-nvme (Linux) errors, simply return the error code */ |
| 480 | if (nvme_sc < 0) |
| 481 | return nvme_sc; |
| 482 | |
| 483 | /* Mask DNR, More, and reserved fields */ |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 484 | switch (nvme_sc & 0x7FF) { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 485 | /* Generic Command Status */ |
| 486 | case NVME_SC_SUCCESS: |
| 487 | status = SAM_STAT_GOOD; |
| 488 | sense_key = NO_SENSE; |
| 489 | asc = SCSI_ASC_NO_SENSE; |
| 490 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 491 | break; |
| 492 | case NVME_SC_INVALID_OPCODE: |
| 493 | status = SAM_STAT_CHECK_CONDITION; |
| 494 | sense_key = ILLEGAL_REQUEST; |
| 495 | asc = SCSI_ASC_ILLEGAL_COMMAND; |
| 496 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 497 | break; |
| 498 | case NVME_SC_INVALID_FIELD: |
| 499 | status = SAM_STAT_CHECK_CONDITION; |
| 500 | sense_key = ILLEGAL_REQUEST; |
| 501 | asc = SCSI_ASC_INVALID_CDB; |
| 502 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 503 | break; |
| 504 | case NVME_SC_DATA_XFER_ERROR: |
| 505 | status = SAM_STAT_CHECK_CONDITION; |
| 506 | sense_key = MEDIUM_ERROR; |
| 507 | asc = SCSI_ASC_NO_SENSE; |
| 508 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 509 | break; |
| 510 | case NVME_SC_POWER_LOSS: |
| 511 | status = SAM_STAT_TASK_ABORTED; |
| 512 | sense_key = ABORTED_COMMAND; |
| 513 | asc = SCSI_ASC_WARNING; |
| 514 | ascq = SCSI_ASCQ_POWER_LOSS_EXPECTED; |
| 515 | break; |
| 516 | case NVME_SC_INTERNAL: |
| 517 | status = SAM_STAT_CHECK_CONDITION; |
| 518 | sense_key = HARDWARE_ERROR; |
| 519 | asc = SCSI_ASC_INTERNAL_TARGET_FAILURE; |
| 520 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 521 | break; |
| 522 | case NVME_SC_ABORT_REQ: |
| 523 | status = SAM_STAT_TASK_ABORTED; |
| 524 | sense_key = ABORTED_COMMAND; |
| 525 | asc = SCSI_ASC_NO_SENSE; |
| 526 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 527 | break; |
| 528 | case NVME_SC_ABORT_QUEUE: |
| 529 | status = SAM_STAT_TASK_ABORTED; |
| 530 | sense_key = ABORTED_COMMAND; |
| 531 | asc = SCSI_ASC_NO_SENSE; |
| 532 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 533 | break; |
| 534 | case NVME_SC_FUSED_FAIL: |
| 535 | status = SAM_STAT_TASK_ABORTED; |
| 536 | sense_key = ABORTED_COMMAND; |
| 537 | asc = SCSI_ASC_NO_SENSE; |
| 538 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 539 | break; |
| 540 | case NVME_SC_FUSED_MISSING: |
| 541 | status = SAM_STAT_TASK_ABORTED; |
| 542 | sense_key = ABORTED_COMMAND; |
| 543 | asc = SCSI_ASC_NO_SENSE; |
| 544 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 545 | break; |
| 546 | case NVME_SC_INVALID_NS: |
| 547 | status = SAM_STAT_CHECK_CONDITION; |
| 548 | sense_key = ILLEGAL_REQUEST; |
| 549 | asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID; |
| 550 | ascq = SCSI_ASCQ_INVALID_LUN_ID; |
| 551 | break; |
| 552 | case NVME_SC_LBA_RANGE: |
| 553 | status = SAM_STAT_CHECK_CONDITION; |
| 554 | sense_key = ILLEGAL_REQUEST; |
| 555 | asc = SCSI_ASC_ILLEGAL_BLOCK; |
| 556 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 557 | break; |
| 558 | case NVME_SC_CAP_EXCEEDED: |
| 559 | status = SAM_STAT_CHECK_CONDITION; |
| 560 | sense_key = MEDIUM_ERROR; |
| 561 | asc = SCSI_ASC_NO_SENSE; |
| 562 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 563 | break; |
| 564 | case NVME_SC_NS_NOT_READY: |
| 565 | status = SAM_STAT_CHECK_CONDITION; |
| 566 | sense_key = NOT_READY; |
| 567 | asc = SCSI_ASC_LUN_NOT_READY; |
| 568 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 569 | break; |
| 570 | |
| 571 | /* Command Specific Status */ |
| 572 | case NVME_SC_INVALID_FORMAT: |
| 573 | status = SAM_STAT_CHECK_CONDITION; |
| 574 | sense_key = ILLEGAL_REQUEST; |
| 575 | asc = SCSI_ASC_FORMAT_COMMAND_FAILED; |
| 576 | ascq = SCSI_ASCQ_FORMAT_COMMAND_FAILED; |
| 577 | break; |
| 578 | case NVME_SC_BAD_ATTRIBUTES: |
| 579 | status = SAM_STAT_CHECK_CONDITION; |
| 580 | sense_key = ILLEGAL_REQUEST; |
| 581 | asc = SCSI_ASC_INVALID_CDB; |
| 582 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 583 | break; |
| 584 | |
| 585 | /* Media Errors */ |
| 586 | case NVME_SC_WRITE_FAULT: |
| 587 | status = SAM_STAT_CHECK_CONDITION; |
| 588 | sense_key = MEDIUM_ERROR; |
| 589 | asc = SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT; |
| 590 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 591 | break; |
| 592 | case NVME_SC_READ_ERROR: |
| 593 | status = SAM_STAT_CHECK_CONDITION; |
| 594 | sense_key = MEDIUM_ERROR; |
| 595 | asc = SCSI_ASC_UNRECOVERED_READ_ERROR; |
| 596 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 597 | break; |
| 598 | case NVME_SC_GUARD_CHECK: |
| 599 | status = SAM_STAT_CHECK_CONDITION; |
| 600 | sense_key = MEDIUM_ERROR; |
| 601 | asc = SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED; |
| 602 | ascq = SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED; |
| 603 | break; |
| 604 | case NVME_SC_APPTAG_CHECK: |
| 605 | status = SAM_STAT_CHECK_CONDITION; |
| 606 | sense_key = MEDIUM_ERROR; |
| 607 | asc = SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED; |
| 608 | ascq = SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED; |
| 609 | break; |
| 610 | case NVME_SC_REFTAG_CHECK: |
| 611 | status = SAM_STAT_CHECK_CONDITION; |
| 612 | sense_key = MEDIUM_ERROR; |
| 613 | asc = SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED; |
| 614 | ascq = SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED; |
| 615 | break; |
| 616 | case NVME_SC_COMPARE_FAILED: |
| 617 | status = SAM_STAT_CHECK_CONDITION; |
| 618 | sense_key = MISCOMPARE; |
| 619 | asc = SCSI_ASC_MISCOMPARE_DURING_VERIFY; |
| 620 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 621 | break; |
| 622 | case NVME_SC_ACCESS_DENIED: |
| 623 | status = SAM_STAT_CHECK_CONDITION; |
| 624 | sense_key = ILLEGAL_REQUEST; |
| 625 | asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID; |
| 626 | ascq = SCSI_ASCQ_INVALID_LUN_ID; |
| 627 | break; |
| 628 | |
| 629 | /* Unspecified/Default */ |
| 630 | case NVME_SC_CMDID_CONFLICT: |
| 631 | case NVME_SC_CMD_SEQ_ERROR: |
| 632 | case NVME_SC_CQ_INVALID: |
| 633 | case NVME_SC_QID_INVALID: |
| 634 | case NVME_SC_QUEUE_SIZE: |
| 635 | case NVME_SC_ABORT_LIMIT: |
| 636 | case NVME_SC_ABORT_MISSING: |
| 637 | case NVME_SC_ASYNC_LIMIT: |
| 638 | case NVME_SC_FIRMWARE_SLOT: |
| 639 | case NVME_SC_FIRMWARE_IMAGE: |
| 640 | case NVME_SC_INVALID_VECTOR: |
| 641 | case NVME_SC_INVALID_LOG_PAGE: |
| 642 | default: |
| 643 | status = SAM_STAT_CHECK_CONDITION; |
| 644 | sense_key = ILLEGAL_REQUEST; |
| 645 | asc = SCSI_ASC_NO_SENSE; |
| 646 | ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 647 | break; |
| 648 | } |
| 649 | |
| 650 | res = nvme_trans_completion(hdr, status, sense_key, asc, ascq); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 651 | return res ? res : nvme_sc; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | /* INQUIRY Helper Functions */ |
| 655 | |
| 656 | static int nvme_trans_standard_inquiry_page(struct nvme_ns *ns, |
| 657 | struct sg_io_hdr *hdr, u8 *inq_response, |
| 658 | int alloc_len) |
| 659 | { |
| 660 | struct nvme_dev *dev = ns->dev; |
| 661 | dma_addr_t dma_addr; |
| 662 | void *mem; |
| 663 | struct nvme_id_ns *id_ns; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 664 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 665 | int nvme_sc; |
| 666 | int xfer_len; |
| 667 | u8 resp_data_format = 0x02; |
| 668 | u8 protect; |
| 669 | u8 cmdque = 0x01 << 1; |
Keith Busch | dedf4b1 | 2014-04-29 15:52:27 -0600 | [diff] [blame] | 670 | u8 fw_offset = sizeof(dev->firmware_rev); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 671 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 672 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 673 | &dma_addr, GFP_KERNEL); |
| 674 | if (mem == NULL) { |
| 675 | res = -ENOMEM; |
| 676 | goto out_dma; |
| 677 | } |
| 678 | |
| 679 | /* nvme ns identify - use DPS value for PROTECT field */ |
| 680 | nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); |
| 681 | res = nvme_trans_status_code(hdr, nvme_sc); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 682 | if (res) |
| 683 | goto out_free; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 684 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 685 | id_ns = mem; |
| 686 | (id_ns->dps) ? (protect = 0x01) : (protect = 0); |
| 687 | |
| 688 | memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); |
| 689 | inq_response[2] = VERSION_SPC_4; |
| 690 | inq_response[3] = resp_data_format; /*normaca=0 | hisup=0 */ |
| 691 | inq_response[4] = ADDITIONAL_STD_INQ_LENGTH; |
| 692 | inq_response[5] = protect; /* sccs=0 | acc=0 | tpgs=0 | pc3=0 */ |
| 693 | inq_response[7] = cmdque; /* wbus16=0 | sync=0 | vs=0 */ |
| 694 | strncpy(&inq_response[8], "NVMe ", 8); |
| 695 | strncpy(&inq_response[16], dev->model, 16); |
Keith Busch | dedf4b1 | 2014-04-29 15:52:27 -0600 | [diff] [blame] | 696 | |
| 697 | while (dev->firmware_rev[fw_offset - 1] == ' ' && fw_offset > 4) |
| 698 | fw_offset--; |
| 699 | fw_offset -= 4; |
| 700 | strncpy(&inq_response[32], dev->firmware_rev + fw_offset, 4); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 701 | |
| 702 | xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH); |
| 703 | res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); |
| 704 | |
| 705 | out_free: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 706 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 707 | out_dma: |
| 708 | return res; |
| 709 | } |
| 710 | |
| 711 | static int nvme_trans_supported_vpd_pages(struct nvme_ns *ns, |
| 712 | struct sg_io_hdr *hdr, u8 *inq_response, |
| 713 | int alloc_len) |
| 714 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 715 | int xfer_len; |
| 716 | |
| 717 | memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); |
| 718 | inq_response[1] = INQ_SUPPORTED_VPD_PAGES_PAGE; /* Page Code */ |
| 719 | inq_response[3] = INQ_NUM_SUPPORTED_VPD_PAGES; /* Page Length */ |
| 720 | inq_response[4] = INQ_SUPPORTED_VPD_PAGES_PAGE; |
| 721 | inq_response[5] = INQ_UNIT_SERIAL_NUMBER_PAGE; |
| 722 | inq_response[6] = INQ_DEVICE_IDENTIFICATION_PAGE; |
| 723 | inq_response[7] = INQ_EXTENDED_INQUIRY_DATA_PAGE; |
| 724 | inq_response[8] = INQ_BDEV_CHARACTERISTICS_PAGE; |
Keith Busch | 7f749d9 | 2015-04-07 15:34:18 -0600 | [diff] [blame] | 725 | inq_response[9] = INQ_BDEV_LIMITS_PAGE; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 726 | |
| 727 | xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 728 | return nvme_trans_copy_to_user(hdr, inq_response, xfer_len); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | static int nvme_trans_unit_serial_page(struct nvme_ns *ns, |
| 732 | struct sg_io_hdr *hdr, u8 *inq_response, |
| 733 | int alloc_len) |
| 734 | { |
| 735 | struct nvme_dev *dev = ns->dev; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 736 | int xfer_len; |
| 737 | |
| 738 | memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); |
| 739 | inq_response[1] = INQ_UNIT_SERIAL_NUMBER_PAGE; /* Page Code */ |
| 740 | inq_response[3] = INQ_SERIAL_NUMBER_LENGTH; /* Page Length */ |
| 741 | strncpy(&inq_response[4], dev->serial, INQ_SERIAL_NUMBER_LENGTH); |
| 742 | |
| 743 | xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 744 | return nvme_trans_copy_to_user(hdr, inq_response, xfer_len); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 745 | } |
| 746 | |
| 747 | static int nvme_trans_device_id_page(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 748 | u8 *inq_response, int alloc_len) |
| 749 | { |
| 750 | struct nvme_dev *dev = ns->dev; |
| 751 | dma_addr_t dma_addr; |
| 752 | void *mem; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 753 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 754 | int nvme_sc; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 755 | int xfer_len; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 756 | __be32 tmp_id = cpu_to_be32(ns->ns_id); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 757 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 758 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 759 | &dma_addr, GFP_KERNEL); |
| 760 | if (mem == NULL) { |
| 761 | res = -ENOMEM; |
| 762 | goto out_dma; |
| 763 | } |
| 764 | |
Keith Busch | 4f1982b | 2015-02-19 13:42:14 -0700 | [diff] [blame] | 765 | memset(inq_response, 0, alloc_len); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 766 | inq_response[1] = INQ_DEVICE_IDENTIFICATION_PAGE; /* Page Code */ |
Keith Busch | 4f1982b | 2015-02-19 13:42:14 -0700 | [diff] [blame] | 767 | if (readl(&dev->bar->vs) >= NVME_VS(1, 1)) { |
| 768 | struct nvme_id_ns *id_ns = mem; |
| 769 | void *eui = id_ns->eui64; |
| 770 | int len = sizeof(id_ns->eui64); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 771 | |
Keith Busch | 4f1982b | 2015-02-19 13:42:14 -0700 | [diff] [blame] | 772 | nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); |
| 773 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 774 | if (res) |
| 775 | goto out_free; |
Keith Busch | 4f1982b | 2015-02-19 13:42:14 -0700 | [diff] [blame] | 776 | |
| 777 | if (readl(&dev->bar->vs) >= NVME_VS(1, 2)) { |
| 778 | if (bitmap_empty(eui, len * 8)) { |
| 779 | eui = id_ns->nguid; |
| 780 | len = sizeof(id_ns->nguid); |
| 781 | } |
| 782 | } |
| 783 | if (bitmap_empty(eui, len * 8)) |
| 784 | goto scsi_string; |
| 785 | |
| 786 | inq_response[3] = 4 + len; /* Page Length */ |
| 787 | /* Designation Descriptor start */ |
| 788 | inq_response[4] = 0x01; /* Proto ID=0h | Code set=1h */ |
| 789 | inq_response[5] = 0x02; /* PIV=0b | Asso=00b | Designator Type=2h */ |
| 790 | inq_response[6] = 0x00; /* Rsvd */ |
| 791 | inq_response[7] = len; /* Designator Length */ |
| 792 | memcpy(&inq_response[8], eui, len); |
| 793 | } else { |
| 794 | scsi_string: |
| 795 | if (alloc_len < 72) { |
| 796 | res = nvme_trans_completion(hdr, |
| 797 | SAM_STAT_CHECK_CONDITION, |
| 798 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 799 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 800 | goto out_free; |
| 801 | } |
| 802 | inq_response[3] = 0x48; /* Page Length */ |
| 803 | /* Designation Descriptor start */ |
| 804 | inq_response[4] = 0x03; /* Proto ID=0h | Code set=3h */ |
| 805 | inq_response[5] = 0x08; /* PIV=0b | Asso=00b | Designator Type=8h */ |
| 806 | inq_response[6] = 0x00; /* Rsvd */ |
| 807 | inq_response[7] = 0x44; /* Designator Length */ |
| 808 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 809 | sprintf(&inq_response[8], "%04x", to_pci_dev(dev->dev)->vendor); |
Keith Busch | 4f1982b | 2015-02-19 13:42:14 -0700 | [diff] [blame] | 810 | memcpy(&inq_response[12], dev->model, sizeof(dev->model)); |
| 811 | sprintf(&inq_response[52], "%04x", tmp_id); |
| 812 | memcpy(&inq_response[56], dev->serial, sizeof(dev->serial)); |
| 813 | } |
| 814 | xfer_len = alloc_len; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 815 | res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); |
| 816 | |
| 817 | out_free: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 818 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 819 | out_dma: |
| 820 | return res; |
| 821 | } |
| 822 | |
| 823 | static int nvme_trans_ext_inq_page(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 824 | int alloc_len) |
| 825 | { |
| 826 | u8 *inq_response; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 827 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 828 | int nvme_sc; |
| 829 | struct nvme_dev *dev = ns->dev; |
| 830 | dma_addr_t dma_addr; |
| 831 | void *mem; |
| 832 | struct nvme_id_ctrl *id_ctrl; |
| 833 | struct nvme_id_ns *id_ns; |
| 834 | int xfer_len; |
| 835 | u8 microcode = 0x80; |
| 836 | u8 spt; |
| 837 | u8 spt_lut[8] = {0, 0, 2, 1, 4, 6, 5, 7}; |
| 838 | u8 grd_chk, app_chk, ref_chk, protect; |
| 839 | u8 uask_sup = 0x20; |
| 840 | u8 v_sup; |
| 841 | u8 luiclr = 0x01; |
| 842 | |
| 843 | inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL); |
| 844 | if (inq_response == NULL) { |
| 845 | res = -ENOMEM; |
| 846 | goto out_mem; |
| 847 | } |
| 848 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 849 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 850 | &dma_addr, GFP_KERNEL); |
| 851 | if (mem == NULL) { |
| 852 | res = -ENOMEM; |
| 853 | goto out_dma; |
| 854 | } |
| 855 | |
| 856 | /* nvme ns identify */ |
| 857 | nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); |
| 858 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 859 | if (res) |
| 860 | goto out_free; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 861 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 862 | id_ns = mem; |
| 863 | spt = spt_lut[(id_ns->dpc) & 0x07] << 3; |
| 864 | (id_ns->dps) ? (protect = 0x01) : (protect = 0); |
| 865 | grd_chk = protect << 2; |
| 866 | app_chk = protect << 1; |
| 867 | ref_chk = protect; |
| 868 | |
| 869 | /* nvme controller identify */ |
| 870 | nvme_sc = nvme_identify(dev, 0, 1, dma_addr); |
| 871 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 872 | if (res) |
| 873 | goto out_free; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 874 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 875 | id_ctrl = mem; |
| 876 | v_sup = id_ctrl->vwc; |
| 877 | |
| 878 | memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH); |
| 879 | inq_response[1] = INQ_EXTENDED_INQUIRY_DATA_PAGE; /* Page Code */ |
| 880 | inq_response[2] = 0x00; /* Page Length MSB */ |
| 881 | inq_response[3] = 0x3C; /* Page Length LSB */ |
| 882 | inq_response[4] = microcode | spt | grd_chk | app_chk | ref_chk; |
| 883 | inq_response[5] = uask_sup; |
| 884 | inq_response[6] = v_sup; |
| 885 | inq_response[7] = luiclr; |
| 886 | inq_response[8] = 0; |
| 887 | inq_response[9] = 0; |
| 888 | |
| 889 | xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH); |
| 890 | res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); |
| 891 | |
| 892 | out_free: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 893 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 894 | out_dma: |
| 895 | kfree(inq_response); |
| 896 | out_mem: |
| 897 | return res; |
| 898 | } |
| 899 | |
Keith Busch | 7f749d9 | 2015-04-07 15:34:18 -0600 | [diff] [blame] | 900 | static int nvme_trans_bdev_limits_page(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 901 | u8 *inq_response, int alloc_len) |
| 902 | { |
| 903 | __be32 max_sectors = cpu_to_be32(queue_max_hw_sectors(ns->queue)); |
| 904 | __be32 max_discard = cpu_to_be32(ns->queue->limits.max_discard_sectors); |
| 905 | __be32 discard_desc_count = cpu_to_be32(0x100); |
| 906 | |
| 907 | memset(inq_response, 0, STANDARD_INQUIRY_LENGTH); |
| 908 | inq_response[1] = VPD_BLOCK_LIMITS; |
| 909 | inq_response[3] = 0x3c; /* Page Length */ |
| 910 | memcpy(&inq_response[8], &max_sectors, sizeof(u32)); |
| 911 | memcpy(&inq_response[20], &max_discard, sizeof(u32)); |
| 912 | |
| 913 | if (max_discard) |
| 914 | memcpy(&inq_response[24], &discard_desc_count, sizeof(u32)); |
| 915 | |
| 916 | return nvme_trans_copy_to_user(hdr, inq_response, 0x3c); |
| 917 | } |
| 918 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 919 | static int nvme_trans_bdev_char_page(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 920 | int alloc_len) |
| 921 | { |
| 922 | u8 *inq_response; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 923 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 924 | int xfer_len; |
| 925 | |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 926 | inq_response = kzalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 927 | if (inq_response == NULL) { |
| 928 | res = -ENOMEM; |
| 929 | goto out_mem; |
| 930 | } |
| 931 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 932 | inq_response[1] = INQ_BDEV_CHARACTERISTICS_PAGE; /* Page Code */ |
| 933 | inq_response[2] = 0x00; /* Page Length MSB */ |
| 934 | inq_response[3] = 0x3C; /* Page Length LSB */ |
| 935 | inq_response[4] = 0x00; /* Medium Rotation Rate MSB */ |
| 936 | inq_response[5] = 0x01; /* Medium Rotation Rate LSB */ |
| 937 | inq_response[6] = 0x00; /* Form Factor */ |
| 938 | |
| 939 | xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH); |
| 940 | res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len); |
| 941 | |
| 942 | kfree(inq_response); |
| 943 | out_mem: |
| 944 | return res; |
| 945 | } |
| 946 | |
| 947 | /* LOG SENSE Helper Functions */ |
| 948 | |
| 949 | static int nvme_trans_log_supp_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 950 | int alloc_len) |
| 951 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 952 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 953 | int xfer_len; |
| 954 | u8 *log_response; |
| 955 | |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 956 | log_response = kzalloc(LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 957 | if (log_response == NULL) { |
| 958 | res = -ENOMEM; |
| 959 | goto out_mem; |
| 960 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 961 | |
| 962 | log_response[0] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE; |
| 963 | /* Subpage=0x00, Page Length MSB=0 */ |
| 964 | log_response[3] = SUPPORTED_LOG_PAGES_PAGE_LENGTH; |
| 965 | log_response[4] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE; |
| 966 | log_response[5] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE; |
| 967 | log_response[6] = LOG_PAGE_TEMPERATURE_PAGE; |
| 968 | |
| 969 | xfer_len = min(alloc_len, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH); |
| 970 | res = nvme_trans_copy_to_user(hdr, log_response, xfer_len); |
| 971 | |
| 972 | kfree(log_response); |
| 973 | out_mem: |
| 974 | return res; |
| 975 | } |
| 976 | |
| 977 | static int nvme_trans_log_info_exceptions(struct nvme_ns *ns, |
| 978 | struct sg_io_hdr *hdr, int alloc_len) |
| 979 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 980 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 981 | int xfer_len; |
| 982 | u8 *log_response; |
| 983 | struct nvme_command c; |
| 984 | struct nvme_dev *dev = ns->dev; |
| 985 | struct nvme_smart_log *smart_log; |
| 986 | dma_addr_t dma_addr; |
| 987 | void *mem; |
| 988 | u8 temp_c; |
| 989 | u16 temp_k; |
| 990 | |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 991 | log_response = kzalloc(LOG_INFO_EXCP_PAGE_LENGTH, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 992 | if (log_response == NULL) { |
| 993 | res = -ENOMEM; |
| 994 | goto out_mem; |
| 995 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 996 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 997 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_smart_log), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 998 | &dma_addr, GFP_KERNEL); |
| 999 | if (mem == NULL) { |
| 1000 | res = -ENOMEM; |
| 1001 | goto out_dma; |
| 1002 | } |
| 1003 | |
| 1004 | /* Get SMART Log Page */ |
| 1005 | memset(&c, 0, sizeof(c)); |
| 1006 | c.common.opcode = nvme_admin_get_log_page; |
| 1007 | c.common.nsid = cpu_to_le32(0xFFFFFFFF); |
| 1008 | c.common.prp1 = cpu_to_le64(dma_addr); |
Indraneel Mukherjee | 4131f2f | 2014-05-29 12:02:03 +0530 | [diff] [blame] | 1009 | c.common.cdw10[0] = cpu_to_le32((((sizeof(struct nvme_smart_log) / |
Matthew Wilcox | ef351b9 | 2014-06-13 10:54:21 -0400 | [diff] [blame] | 1010 | BYTES_TO_DWORDS) - 1) << 16) | NVME_LOG_SMART); |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 1011 | res = nvme_submit_sync_cmd(dev->admin_q, &c); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1012 | if (res != NVME_SC_SUCCESS) { |
| 1013 | temp_c = LOG_TEMP_UNKNOWN; |
| 1014 | } else { |
| 1015 | smart_log = mem; |
| 1016 | temp_k = (smart_log->temperature[1] << 8) + |
| 1017 | (smart_log->temperature[0]); |
| 1018 | temp_c = temp_k - KELVIN_TEMP_FACTOR; |
| 1019 | } |
| 1020 | |
| 1021 | log_response[0] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE; |
| 1022 | /* Subpage=0x00, Page Length MSB=0 */ |
| 1023 | log_response[3] = REMAINING_INFO_EXCP_PAGE_LENGTH; |
| 1024 | /* Informational Exceptions Log Parameter 1 Start */ |
| 1025 | /* Parameter Code=0x0000 bytes 4,5 */ |
| 1026 | log_response[6] = 0x23; /* DU=0, TSD=1, ETC=0, TMC=0, FMT_AND_LNK=11b */ |
| 1027 | log_response[7] = 0x04; /* PARAMETER LENGTH */ |
| 1028 | /* Add sense Code and qualifier = 0x00 each */ |
| 1029 | /* Use Temperature from NVMe Get Log Page, convert to C from K */ |
| 1030 | log_response[10] = temp_c; |
| 1031 | |
| 1032 | xfer_len = min(alloc_len, LOG_INFO_EXCP_PAGE_LENGTH); |
| 1033 | res = nvme_trans_copy_to_user(hdr, log_response, xfer_len); |
| 1034 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1035 | dma_free_coherent(dev->dev, sizeof(struct nvme_smart_log), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1036 | mem, dma_addr); |
| 1037 | out_dma: |
| 1038 | kfree(log_response); |
| 1039 | out_mem: |
| 1040 | return res; |
| 1041 | } |
| 1042 | |
| 1043 | static int nvme_trans_log_temperature(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1044 | int alloc_len) |
| 1045 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1046 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1047 | int xfer_len; |
| 1048 | u8 *log_response; |
| 1049 | struct nvme_command c; |
| 1050 | struct nvme_dev *dev = ns->dev; |
| 1051 | struct nvme_smart_log *smart_log; |
| 1052 | dma_addr_t dma_addr; |
| 1053 | void *mem; |
| 1054 | u32 feature_resp; |
| 1055 | u8 temp_c_cur, temp_c_thresh; |
| 1056 | u16 temp_k; |
| 1057 | |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 1058 | log_response = kzalloc(LOG_TEMP_PAGE_LENGTH, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1059 | if (log_response == NULL) { |
| 1060 | res = -ENOMEM; |
| 1061 | goto out_mem; |
| 1062 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1063 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1064 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_smart_log), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1065 | &dma_addr, GFP_KERNEL); |
| 1066 | if (mem == NULL) { |
| 1067 | res = -ENOMEM; |
| 1068 | goto out_dma; |
| 1069 | } |
| 1070 | |
| 1071 | /* Get SMART Log Page */ |
| 1072 | memset(&c, 0, sizeof(c)); |
| 1073 | c.common.opcode = nvme_admin_get_log_page; |
| 1074 | c.common.nsid = cpu_to_le32(0xFFFFFFFF); |
| 1075 | c.common.prp1 = cpu_to_le64(dma_addr); |
Indraneel Mukherjee | 4131f2f | 2014-05-29 12:02:03 +0530 | [diff] [blame] | 1076 | c.common.cdw10[0] = cpu_to_le32((((sizeof(struct nvme_smart_log) / |
Matthew Wilcox | ef351b9 | 2014-06-13 10:54:21 -0400 | [diff] [blame] | 1077 | BYTES_TO_DWORDS) - 1) << 16) | NVME_LOG_SMART); |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 1078 | res = nvme_submit_sync_cmd(dev->admin_q, &c); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1079 | if (res != NVME_SC_SUCCESS) { |
| 1080 | temp_c_cur = LOG_TEMP_UNKNOWN; |
| 1081 | } else { |
| 1082 | smart_log = mem; |
| 1083 | temp_k = (smart_log->temperature[1] << 8) + |
| 1084 | (smart_log->temperature[0]); |
| 1085 | temp_c_cur = temp_k - KELVIN_TEMP_FACTOR; |
| 1086 | } |
| 1087 | |
| 1088 | /* Get Features for Temp Threshold */ |
| 1089 | res = nvme_get_features(dev, NVME_FEAT_TEMP_THRESH, 0, 0, |
| 1090 | &feature_resp); |
| 1091 | if (res != NVME_SC_SUCCESS) |
| 1092 | temp_c_thresh = LOG_TEMP_UNKNOWN; |
| 1093 | else |
| 1094 | temp_c_thresh = (feature_resp & 0xFFFF) - KELVIN_TEMP_FACTOR; |
| 1095 | |
| 1096 | log_response[0] = LOG_PAGE_TEMPERATURE_PAGE; |
| 1097 | /* Subpage=0x00, Page Length MSB=0 */ |
| 1098 | log_response[3] = REMAINING_TEMP_PAGE_LENGTH; |
| 1099 | /* Temperature Log Parameter 1 (Temperature) Start */ |
| 1100 | /* Parameter Code = 0x0000 */ |
| 1101 | log_response[6] = 0x01; /* Format and Linking = 01b */ |
| 1102 | log_response[7] = 0x02; /* Parameter Length */ |
| 1103 | /* Use Temperature from NVMe Get Log Page, convert to C from K */ |
| 1104 | log_response[9] = temp_c_cur; |
| 1105 | /* Temperature Log Parameter 2 (Reference Temperature) Start */ |
| 1106 | log_response[11] = 0x01; /* Parameter Code = 0x0001 */ |
| 1107 | log_response[12] = 0x01; /* Format and Linking = 01b */ |
| 1108 | log_response[13] = 0x02; /* Parameter Length */ |
| 1109 | /* Use Temperature Thresh from NVMe Get Log Page, convert to C from K */ |
| 1110 | log_response[15] = temp_c_thresh; |
| 1111 | |
| 1112 | xfer_len = min(alloc_len, LOG_TEMP_PAGE_LENGTH); |
| 1113 | res = nvme_trans_copy_to_user(hdr, log_response, xfer_len); |
| 1114 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1115 | dma_free_coherent(dev->dev, sizeof(struct nvme_smart_log), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1116 | mem, dma_addr); |
| 1117 | out_dma: |
| 1118 | kfree(log_response); |
| 1119 | out_mem: |
| 1120 | return res; |
| 1121 | } |
| 1122 | |
| 1123 | /* MODE SENSE Helper Functions */ |
| 1124 | |
| 1125 | static int nvme_trans_fill_mode_parm_hdr(u8 *resp, int len, u8 cdb10, u8 llbaa, |
| 1126 | u16 mode_data_length, u16 blk_desc_len) |
| 1127 | { |
| 1128 | /* Quick check to make sure I don't stomp on my own memory... */ |
| 1129 | if ((cdb10 && len < 8) || (!cdb10 && len < 4)) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1130 | return -EINVAL; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1131 | |
| 1132 | if (cdb10) { |
| 1133 | resp[0] = (mode_data_length & 0xFF00) >> 8; |
| 1134 | resp[1] = (mode_data_length & 0x00FF); |
| 1135 | /* resp[2] and [3] are zero */ |
| 1136 | resp[4] = llbaa; |
| 1137 | resp[5] = RESERVED_FIELD; |
| 1138 | resp[6] = (blk_desc_len & 0xFF00) >> 8; |
| 1139 | resp[7] = (blk_desc_len & 0x00FF); |
| 1140 | } else { |
| 1141 | resp[0] = (mode_data_length & 0x00FF); |
| 1142 | /* resp[1] and [2] are zero */ |
| 1143 | resp[3] = (blk_desc_len & 0x00FF); |
| 1144 | } |
| 1145 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1146 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1147 | } |
| 1148 | |
| 1149 | static int nvme_trans_fill_blk_desc(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1150 | u8 *resp, int len, u8 llbaa) |
| 1151 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1152 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1153 | int nvme_sc; |
| 1154 | struct nvme_dev *dev = ns->dev; |
| 1155 | dma_addr_t dma_addr; |
| 1156 | void *mem; |
| 1157 | struct nvme_id_ns *id_ns; |
| 1158 | u8 flbas; |
| 1159 | u32 lba_length; |
| 1160 | |
| 1161 | if (llbaa == 0 && len < MODE_PAGE_BLK_DES_LEN) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1162 | return -EINVAL; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1163 | else if (llbaa > 0 && len < MODE_PAGE_LLBAA_BLK_DES_LEN) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1164 | return -EINVAL; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1165 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1166 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1167 | &dma_addr, GFP_KERNEL); |
| 1168 | if (mem == NULL) { |
| 1169 | res = -ENOMEM; |
| 1170 | goto out; |
| 1171 | } |
| 1172 | |
| 1173 | /* nvme ns identify */ |
| 1174 | nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); |
| 1175 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 1176 | if (res) |
| 1177 | goto out_dma; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1178 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1179 | id_ns = mem; |
| 1180 | flbas = (id_ns->flbas) & 0x0F; |
| 1181 | lba_length = (1 << (id_ns->lbaf[flbas].ds)); |
| 1182 | |
| 1183 | if (llbaa == 0) { |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1184 | __be32 tmp_cap = cpu_to_be32(le64_to_cpu(id_ns->ncap)); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1185 | /* Byte 4 is reserved */ |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1186 | __be32 tmp_len = cpu_to_be32(lba_length & 0x00FFFFFF); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1187 | |
| 1188 | memcpy(resp, &tmp_cap, sizeof(u32)); |
| 1189 | memcpy(&resp[4], &tmp_len, sizeof(u32)); |
| 1190 | } else { |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1191 | __be64 tmp_cap = cpu_to_be64(le64_to_cpu(id_ns->ncap)); |
| 1192 | __be32 tmp_len = cpu_to_be32(lba_length); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1193 | |
| 1194 | memcpy(resp, &tmp_cap, sizeof(u64)); |
| 1195 | /* Bytes 8, 9, 10, 11 are reserved */ |
| 1196 | memcpy(&resp[12], &tmp_len, sizeof(u32)); |
| 1197 | } |
| 1198 | |
| 1199 | out_dma: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1200 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1201 | out: |
| 1202 | return res; |
| 1203 | } |
| 1204 | |
| 1205 | static int nvme_trans_fill_control_page(struct nvme_ns *ns, |
| 1206 | struct sg_io_hdr *hdr, u8 *resp, |
| 1207 | int len) |
| 1208 | { |
| 1209 | if (len < MODE_PAGE_CONTROL_LEN) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1210 | return -EINVAL; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1211 | |
| 1212 | resp[0] = MODE_PAGE_CONTROL; |
| 1213 | resp[1] = MODE_PAGE_CONTROL_LEN_FIELD; |
| 1214 | resp[2] = 0x0E; /* TST=000b, TMF_ONLY=0, DPICZ=1, |
| 1215 | * D_SENSE=1, GLTSD=1, RLEC=0 */ |
| 1216 | resp[3] = 0x12; /* Q_ALGO_MODIFIER=1h, NUAR=0, QERR=01b */ |
| 1217 | /* Byte 4: VS=0, RAC=0, UA_INT=0, SWP=0 */ |
| 1218 | resp[5] = 0x40; /* ATO=0, TAS=1, ATMPE=0, RWWP=0, AUTOLOAD=0 */ |
| 1219 | /* resp[6] and [7] are obsolete, thus zero */ |
| 1220 | resp[8] = 0xFF; /* Busy timeout period = 0xffff */ |
| 1221 | resp[9] = 0xFF; |
| 1222 | /* Bytes 10,11: Extended selftest completion time = 0x0000 */ |
| 1223 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1224 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1225 | } |
| 1226 | |
| 1227 | static int nvme_trans_fill_caching_page(struct nvme_ns *ns, |
| 1228 | struct sg_io_hdr *hdr, |
| 1229 | u8 *resp, int len) |
| 1230 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1231 | int res = 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1232 | int nvme_sc; |
| 1233 | struct nvme_dev *dev = ns->dev; |
| 1234 | u32 feature_resp; |
| 1235 | u8 vwc; |
| 1236 | |
| 1237 | if (len < MODE_PAGE_CACHING_LEN) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1238 | return -EINVAL; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1239 | |
| 1240 | nvme_sc = nvme_get_features(dev, NVME_FEAT_VOLATILE_WC, 0, 0, |
| 1241 | &feature_resp); |
| 1242 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 1243 | if (res) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1244 | return res; |
| 1245 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1246 | vwc = feature_resp & 0x00000001; |
| 1247 | |
| 1248 | resp[0] = MODE_PAGE_CACHING; |
| 1249 | resp[1] = MODE_PAGE_CACHING_LEN_FIELD; |
| 1250 | resp[2] = vwc << 2; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1251 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1252 | } |
| 1253 | |
| 1254 | static int nvme_trans_fill_pow_cnd_page(struct nvme_ns *ns, |
| 1255 | struct sg_io_hdr *hdr, u8 *resp, |
| 1256 | int len) |
| 1257 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1258 | if (len < MODE_PAGE_POW_CND_LEN) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1259 | return -EINVAL; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1260 | |
| 1261 | resp[0] = MODE_PAGE_POWER_CONDITION; |
| 1262 | resp[1] = MODE_PAGE_POW_CND_LEN_FIELD; |
| 1263 | /* All other bytes are zero */ |
| 1264 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1265 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1266 | } |
| 1267 | |
| 1268 | static int nvme_trans_fill_inf_exc_page(struct nvme_ns *ns, |
| 1269 | struct sg_io_hdr *hdr, u8 *resp, |
| 1270 | int len) |
| 1271 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1272 | if (len < MODE_PAGE_INF_EXC_LEN) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1273 | return -EINVAL; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1274 | |
| 1275 | resp[0] = MODE_PAGE_INFO_EXCEP; |
| 1276 | resp[1] = MODE_PAGE_INF_EXC_LEN_FIELD; |
| 1277 | resp[2] = 0x88; |
| 1278 | /* All other bytes are zero */ |
| 1279 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1280 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1281 | } |
| 1282 | |
| 1283 | static int nvme_trans_fill_all_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1284 | u8 *resp, int len) |
| 1285 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1286 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1287 | u16 mode_pages_offset_1 = 0; |
| 1288 | u16 mode_pages_offset_2, mode_pages_offset_3, mode_pages_offset_4; |
| 1289 | |
| 1290 | mode_pages_offset_2 = mode_pages_offset_1 + MODE_PAGE_CACHING_LEN; |
| 1291 | mode_pages_offset_3 = mode_pages_offset_2 + MODE_PAGE_CONTROL_LEN; |
| 1292 | mode_pages_offset_4 = mode_pages_offset_3 + MODE_PAGE_POW_CND_LEN; |
| 1293 | |
| 1294 | res = nvme_trans_fill_caching_page(ns, hdr, &resp[mode_pages_offset_1], |
| 1295 | MODE_PAGE_CACHING_LEN); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1296 | if (res) |
| 1297 | return res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1298 | res = nvme_trans_fill_control_page(ns, hdr, &resp[mode_pages_offset_2], |
| 1299 | MODE_PAGE_CONTROL_LEN); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1300 | if (res) |
| 1301 | return res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1302 | res = nvme_trans_fill_pow_cnd_page(ns, hdr, &resp[mode_pages_offset_3], |
| 1303 | MODE_PAGE_POW_CND_LEN); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1304 | if (res) |
| 1305 | return res; |
| 1306 | return nvme_trans_fill_inf_exc_page(ns, hdr, &resp[mode_pages_offset_4], |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1307 | MODE_PAGE_INF_EXC_LEN); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1308 | } |
| 1309 | |
| 1310 | static inline int nvme_trans_get_blk_desc_len(u8 dbd, u8 llbaa) |
| 1311 | { |
| 1312 | if (dbd == MODE_SENSE_BLK_DESC_ENABLED) { |
| 1313 | /* SPC-4: len = 8 x Num_of_descriptors if llbaa = 0, 16x if 1 */ |
| 1314 | return 8 * (llbaa + 1) * MODE_SENSE_BLK_DESC_COUNT; |
| 1315 | } else { |
| 1316 | return 0; |
| 1317 | } |
| 1318 | } |
| 1319 | |
| 1320 | static int nvme_trans_mode_page_create(struct nvme_ns *ns, |
| 1321 | struct sg_io_hdr *hdr, u8 *cmd, |
| 1322 | u16 alloc_len, u8 cdb10, |
| 1323 | int (*mode_page_fill_func) |
| 1324 | (struct nvme_ns *, |
| 1325 | struct sg_io_hdr *hdr, u8 *, int), |
| 1326 | u16 mode_pages_tot_len) |
| 1327 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1328 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1329 | int xfer_len; |
| 1330 | u8 *response; |
| 1331 | u8 dbd, llbaa; |
| 1332 | u16 resp_size; |
| 1333 | int mph_size; |
| 1334 | u16 mode_pages_offset_1; |
| 1335 | u16 blk_desc_len, blk_desc_offset, mode_data_length; |
| 1336 | |
| 1337 | dbd = GET_MODE_SENSE_DBD(cmd); |
| 1338 | llbaa = GET_MODE_SENSE_LLBAA(cmd); |
| 1339 | mph_size = GET_MODE_SENSE_MPH_SIZE(cdb10); |
| 1340 | blk_desc_len = nvme_trans_get_blk_desc_len(dbd, llbaa); |
| 1341 | |
| 1342 | resp_size = mph_size + blk_desc_len + mode_pages_tot_len; |
| 1343 | /* Refer spc4r34 Table 440 for calculation of Mode data Length field */ |
| 1344 | mode_data_length = 3 + (3 * cdb10) + blk_desc_len + mode_pages_tot_len; |
| 1345 | |
| 1346 | blk_desc_offset = mph_size; |
| 1347 | mode_pages_offset_1 = blk_desc_offset + blk_desc_len; |
| 1348 | |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 1349 | response = kzalloc(resp_size, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1350 | if (response == NULL) { |
| 1351 | res = -ENOMEM; |
| 1352 | goto out_mem; |
| 1353 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1354 | |
| 1355 | res = nvme_trans_fill_mode_parm_hdr(&response[0], mph_size, cdb10, |
| 1356 | llbaa, mode_data_length, blk_desc_len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1357 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1358 | goto out_free; |
| 1359 | if (blk_desc_len > 0) { |
| 1360 | res = nvme_trans_fill_blk_desc(ns, hdr, |
| 1361 | &response[blk_desc_offset], |
| 1362 | blk_desc_len, llbaa); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1363 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1364 | goto out_free; |
| 1365 | } |
| 1366 | res = mode_page_fill_func(ns, hdr, &response[mode_pages_offset_1], |
| 1367 | mode_pages_tot_len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1368 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1369 | goto out_free; |
| 1370 | |
| 1371 | xfer_len = min(alloc_len, resp_size); |
| 1372 | res = nvme_trans_copy_to_user(hdr, response, xfer_len); |
| 1373 | |
| 1374 | out_free: |
| 1375 | kfree(response); |
| 1376 | out_mem: |
| 1377 | return res; |
| 1378 | } |
| 1379 | |
| 1380 | /* Read Capacity Helper Functions */ |
| 1381 | |
| 1382 | static void nvme_trans_fill_read_cap(u8 *response, struct nvme_id_ns *id_ns, |
| 1383 | u8 cdb16) |
| 1384 | { |
| 1385 | u8 flbas; |
| 1386 | u32 lba_length; |
| 1387 | u64 rlba; |
| 1388 | u8 prot_en; |
| 1389 | u8 p_type_lut[4] = {0, 0, 1, 2}; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1390 | __be64 tmp_rlba; |
| 1391 | __be32 tmp_rlba_32; |
| 1392 | __be32 tmp_len; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1393 | |
| 1394 | flbas = (id_ns->flbas) & 0x0F; |
| 1395 | lba_length = (1 << (id_ns->lbaf[flbas].ds)); |
| 1396 | rlba = le64_to_cpup(&id_ns->nsze) - 1; |
| 1397 | (id_ns->dps) ? (prot_en = 0x01) : (prot_en = 0); |
| 1398 | |
| 1399 | if (!cdb16) { |
| 1400 | if (rlba > 0xFFFFFFFF) |
| 1401 | rlba = 0xFFFFFFFF; |
| 1402 | tmp_rlba_32 = cpu_to_be32(rlba); |
| 1403 | tmp_len = cpu_to_be32(lba_length); |
| 1404 | memcpy(response, &tmp_rlba_32, sizeof(u32)); |
| 1405 | memcpy(&response[4], &tmp_len, sizeof(u32)); |
| 1406 | } else { |
| 1407 | tmp_rlba = cpu_to_be64(rlba); |
| 1408 | tmp_len = cpu_to_be32(lba_length); |
| 1409 | memcpy(response, &tmp_rlba, sizeof(u64)); |
| 1410 | memcpy(&response[8], &tmp_len, sizeof(u32)); |
| 1411 | response[12] = (p_type_lut[id_ns->dps & 0x3] << 1) | prot_en; |
| 1412 | /* P_I_Exponent = 0x0 | LBPPBE = 0x0 */ |
| 1413 | /* LBPME = 0 | LBPRZ = 0 | LALBA = 0x00 */ |
| 1414 | /* Bytes 16-31 - Reserved */ |
| 1415 | } |
| 1416 | } |
| 1417 | |
| 1418 | /* Start Stop Unit Helper Functions */ |
| 1419 | |
| 1420 | static int nvme_trans_power_state(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1421 | u8 pc, u8 pcmod, u8 start) |
| 1422 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1423 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1424 | int nvme_sc; |
| 1425 | struct nvme_dev *dev = ns->dev; |
| 1426 | dma_addr_t dma_addr; |
| 1427 | void *mem; |
| 1428 | struct nvme_id_ctrl *id_ctrl; |
| 1429 | int lowest_pow_st; /* max npss = lowest power consumption */ |
| 1430 | unsigned ps_desired = 0; |
| 1431 | |
| 1432 | /* NVMe Controller Identify */ |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1433 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ctrl), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1434 | &dma_addr, GFP_KERNEL); |
| 1435 | if (mem == NULL) { |
| 1436 | res = -ENOMEM; |
| 1437 | goto out; |
| 1438 | } |
| 1439 | nvme_sc = nvme_identify(dev, 0, 1, dma_addr); |
| 1440 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 1441 | if (res) |
| 1442 | goto out_dma; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1443 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1444 | id_ctrl = mem; |
Dan McLeran | b8e0808 | 2014-06-06 08:27:27 -0600 | [diff] [blame] | 1445 | lowest_pow_st = max(POWER_STATE_0, (int)(id_ctrl->npss - 1)); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1446 | |
| 1447 | switch (pc) { |
| 1448 | case NVME_POWER_STATE_START_VALID: |
| 1449 | /* Action unspecified if POWER CONDITION MODIFIER != 0 */ |
| 1450 | if (pcmod == 0 && start == 0x1) |
| 1451 | ps_desired = POWER_STATE_0; |
| 1452 | if (pcmod == 0 && start == 0x0) |
| 1453 | ps_desired = lowest_pow_st; |
| 1454 | break; |
| 1455 | case NVME_POWER_STATE_ACTIVE: |
| 1456 | /* Action unspecified if POWER CONDITION MODIFIER != 0 */ |
| 1457 | if (pcmod == 0) |
| 1458 | ps_desired = POWER_STATE_0; |
| 1459 | break; |
| 1460 | case NVME_POWER_STATE_IDLE: |
| 1461 | /* Action unspecified if POWER CONDITION MODIFIER != [0,1,2] */ |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1462 | if (pcmod == 0x0) |
Dan McLeran | b8e0808 | 2014-06-06 08:27:27 -0600 | [diff] [blame] | 1463 | ps_desired = POWER_STATE_1; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1464 | else if (pcmod == 0x1) |
Dan McLeran | b8e0808 | 2014-06-06 08:27:27 -0600 | [diff] [blame] | 1465 | ps_desired = POWER_STATE_2; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1466 | else if (pcmod == 0x2) |
Dan McLeran | b8e0808 | 2014-06-06 08:27:27 -0600 | [diff] [blame] | 1467 | ps_desired = POWER_STATE_3; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1468 | break; |
| 1469 | case NVME_POWER_STATE_STANDBY: |
| 1470 | /* Action unspecified if POWER CONDITION MODIFIER != [0,1] */ |
| 1471 | if (pcmod == 0x0) |
Dan McLeran | b8e0808 | 2014-06-06 08:27:27 -0600 | [diff] [blame] | 1472 | ps_desired = max(POWER_STATE_0, (lowest_pow_st - 2)); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1473 | else if (pcmod == 0x1) |
Dan McLeran | b8e0808 | 2014-06-06 08:27:27 -0600 | [diff] [blame] | 1474 | ps_desired = max(POWER_STATE_0, (lowest_pow_st - 1)); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1475 | break; |
| 1476 | case NVME_POWER_STATE_LU_CONTROL: |
| 1477 | default: |
| 1478 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 1479 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 1480 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 1481 | break; |
| 1482 | } |
| 1483 | nvme_sc = nvme_set_features(dev, NVME_FEAT_POWER_MGMT, ps_desired, 0, |
| 1484 | NULL); |
| 1485 | res = nvme_trans_status_code(hdr, nvme_sc); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1486 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1487 | out_dma: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1488 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ctrl), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1489 | out: |
| 1490 | return res; |
| 1491 | } |
| 1492 | |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 1493 | static int nvme_trans_send_activate_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1494 | u8 buffer_id) |
| 1495 | { |
| 1496 | struct nvme_command c; |
| 1497 | int nvme_sc; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1498 | |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 1499 | memset(&c, 0, sizeof(c)); |
| 1500 | c.common.opcode = nvme_admin_activate_fw; |
| 1501 | c.common.cdw10[0] = cpu_to_le32(buffer_id | NVME_FWACT_REPL_ACTV); |
| 1502 | |
| 1503 | nvme_sc = nvme_submit_sync_cmd(ns->queue, &c); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1504 | return nvme_trans_status_code(hdr, nvme_sc); |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 1505 | } |
| 1506 | |
| 1507 | static int nvme_trans_send_download_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1508 | u8 opcode, u32 tot_len, u32 offset, |
| 1509 | u8 buffer_id) |
| 1510 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1511 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1512 | int nvme_sc; |
| 1513 | struct nvme_dev *dev = ns->dev; |
| 1514 | struct nvme_command c; |
| 1515 | struct nvme_iod *iod = NULL; |
| 1516 | unsigned length; |
| 1517 | |
| 1518 | memset(&c, 0, sizeof(c)); |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 1519 | c.common.opcode = nvme_admin_download_fw; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1520 | |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 1521 | if (hdr->iovec_count > 0) { |
| 1522 | /* Assuming SGL is not allowed for this command */ |
| 1523 | return nvme_trans_completion(hdr, |
| 1524 | SAM_STAT_CHECK_CONDITION, |
| 1525 | ILLEGAL_REQUEST, |
| 1526 | SCSI_ASC_INVALID_CDB, |
| 1527 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1528 | } |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 1529 | iod = nvme_map_user_pages(dev, DMA_TO_DEVICE, |
| 1530 | (unsigned long)hdr->dxferp, tot_len); |
| 1531 | if (IS_ERR(iod)) |
| 1532 | return PTR_ERR(iod); |
| 1533 | length = nvme_setup_prps(dev, iod, tot_len, GFP_KERNEL); |
| 1534 | if (length != tot_len) { |
| 1535 | res = -ENOMEM; |
| 1536 | goto out_unmap; |
| 1537 | } |
| 1538 | |
| 1539 | c.dlfw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
| 1540 | c.dlfw.prp2 = cpu_to_le64(iod->first_dma); |
| 1541 | c.dlfw.numd = cpu_to_le32((tot_len/BYTES_TO_DWORDS) - 1); |
| 1542 | c.dlfw.offset = cpu_to_le32(offset/BYTES_TO_DWORDS); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1543 | |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 1544 | nvme_sc = nvme_submit_sync_cmd(dev->admin_q, &c); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1545 | res = nvme_trans_status_code(hdr, nvme_sc); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1546 | |
| 1547 | out_unmap: |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 1548 | nvme_unmap_user_pages(dev, DMA_TO_DEVICE, iod); |
| 1549 | nvme_free_iod(dev, iod); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1550 | return res; |
| 1551 | } |
| 1552 | |
| 1553 | /* Mode Select Helper Functions */ |
| 1554 | |
| 1555 | static inline void nvme_trans_modesel_get_bd_len(u8 *parm_list, u8 cdb10, |
| 1556 | u16 *bd_len, u8 *llbaa) |
| 1557 | { |
| 1558 | if (cdb10) { |
| 1559 | /* 10 Byte CDB */ |
| 1560 | *bd_len = (parm_list[MODE_SELECT_10_BD_OFFSET] << 8) + |
| 1561 | parm_list[MODE_SELECT_10_BD_OFFSET + 1]; |
Keith Busch | 9ac1693 | 2015-01-09 16:52:08 -0700 | [diff] [blame] | 1562 | *llbaa = parm_list[MODE_SELECT_10_LLBAA_OFFSET] & |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1563 | MODE_SELECT_10_LLBAA_MASK; |
| 1564 | } else { |
| 1565 | /* 6 Byte CDB */ |
| 1566 | *bd_len = parm_list[MODE_SELECT_6_BD_OFFSET]; |
| 1567 | } |
| 1568 | } |
| 1569 | |
| 1570 | static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list, |
| 1571 | u16 idx, u16 bd_len, u8 llbaa) |
| 1572 | { |
| 1573 | u16 bd_num; |
| 1574 | |
| 1575 | bd_num = bd_len / ((llbaa == 0) ? |
| 1576 | SHORT_DESC_BLOCK : LONG_DESC_BLOCK); |
| 1577 | /* Store block descriptor info if a FORMAT UNIT comes later */ |
| 1578 | /* TODO Saving 1st BD info; what to do if multiple BD received? */ |
| 1579 | if (llbaa == 0) { |
| 1580 | /* Standard Block Descriptor - spc4r34 7.5.5.1 */ |
| 1581 | ns->mode_select_num_blocks = |
| 1582 | (parm_list[idx + 1] << 16) + |
| 1583 | (parm_list[idx + 2] << 8) + |
| 1584 | (parm_list[idx + 3]); |
| 1585 | |
| 1586 | ns->mode_select_block_len = |
| 1587 | (parm_list[idx + 5] << 16) + |
| 1588 | (parm_list[idx + 6] << 8) + |
| 1589 | (parm_list[idx + 7]); |
| 1590 | } else { |
| 1591 | /* Long LBA Block Descriptor - sbc3r27 6.4.2.3 */ |
| 1592 | ns->mode_select_num_blocks = |
| 1593 | (((u64)parm_list[idx + 0]) << 56) + |
| 1594 | (((u64)parm_list[idx + 1]) << 48) + |
| 1595 | (((u64)parm_list[idx + 2]) << 40) + |
| 1596 | (((u64)parm_list[idx + 3]) << 32) + |
| 1597 | (((u64)parm_list[idx + 4]) << 24) + |
| 1598 | (((u64)parm_list[idx + 5]) << 16) + |
| 1599 | (((u64)parm_list[idx + 6]) << 8) + |
| 1600 | ((u64)parm_list[idx + 7]); |
| 1601 | |
| 1602 | ns->mode_select_block_len = |
| 1603 | (parm_list[idx + 12] << 24) + |
| 1604 | (parm_list[idx + 13] << 16) + |
| 1605 | (parm_list[idx + 14] << 8) + |
| 1606 | (parm_list[idx + 15]); |
| 1607 | } |
| 1608 | } |
| 1609 | |
Vishal Verma | 710a143 | 2013-05-13 14:55:18 -0600 | [diff] [blame] | 1610 | static int nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1611 | u8 *mode_page, u8 page_code) |
| 1612 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1613 | int res = 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1614 | int nvme_sc; |
| 1615 | struct nvme_dev *dev = ns->dev; |
| 1616 | unsigned dword11; |
| 1617 | |
| 1618 | switch (page_code) { |
| 1619 | case MODE_PAGE_CACHING: |
| 1620 | dword11 = ((mode_page[2] & CACHING_MODE_PAGE_WCE_MASK) ? 1 : 0); |
| 1621 | nvme_sc = nvme_set_features(dev, NVME_FEAT_VOLATILE_WC, dword11, |
| 1622 | 0, NULL); |
| 1623 | res = nvme_trans_status_code(hdr, nvme_sc); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1624 | break; |
| 1625 | case MODE_PAGE_CONTROL: |
| 1626 | break; |
| 1627 | case MODE_PAGE_POWER_CONDITION: |
| 1628 | /* Verify the OS is not trying to set timers */ |
| 1629 | if ((mode_page[2] & 0x01) != 0 || (mode_page[3] & 0x0F) != 0) { |
| 1630 | res = nvme_trans_completion(hdr, |
| 1631 | SAM_STAT_CHECK_CONDITION, |
| 1632 | ILLEGAL_REQUEST, |
| 1633 | SCSI_ASC_INVALID_PARAMETER, |
| 1634 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1635 | break; |
| 1636 | } |
| 1637 | break; |
| 1638 | default: |
| 1639 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 1640 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 1641 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1642 | break; |
| 1643 | } |
| 1644 | |
| 1645 | return res; |
| 1646 | } |
| 1647 | |
| 1648 | static int nvme_trans_modesel_data(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1649 | u8 *cmd, u16 parm_list_len, u8 pf, |
| 1650 | u8 sp, u8 cdb10) |
| 1651 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1652 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1653 | u8 *parm_list; |
| 1654 | u16 bd_len; |
| 1655 | u8 llbaa = 0; |
| 1656 | u16 index, saved_index; |
| 1657 | u8 page_code; |
| 1658 | u16 mp_size; |
| 1659 | |
| 1660 | /* Get parm list from data-in/out buffer */ |
| 1661 | parm_list = kmalloc(parm_list_len, GFP_KERNEL); |
| 1662 | if (parm_list == NULL) { |
| 1663 | res = -ENOMEM; |
| 1664 | goto out; |
| 1665 | } |
| 1666 | |
| 1667 | res = nvme_trans_copy_from_user(hdr, parm_list, parm_list_len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1668 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1669 | goto out_mem; |
| 1670 | |
| 1671 | nvme_trans_modesel_get_bd_len(parm_list, cdb10, &bd_len, &llbaa); |
| 1672 | index = (cdb10) ? (MODE_SELECT_10_MPH_SIZE) : (MODE_SELECT_6_MPH_SIZE); |
| 1673 | |
| 1674 | if (bd_len != 0) { |
| 1675 | /* Block Descriptors present, parse */ |
| 1676 | nvme_trans_modesel_save_bd(ns, parm_list, index, bd_len, llbaa); |
| 1677 | index += bd_len; |
| 1678 | } |
| 1679 | saved_index = index; |
| 1680 | |
| 1681 | /* Multiple mode pages may be present; iterate through all */ |
| 1682 | /* In 1st Iteration, don't do NVME Command, only check for CDB errors */ |
| 1683 | do { |
| 1684 | page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK; |
| 1685 | mp_size = parm_list[index + 1] + 2; |
| 1686 | if ((page_code != MODE_PAGE_CACHING) && |
| 1687 | (page_code != MODE_PAGE_CONTROL) && |
| 1688 | (page_code != MODE_PAGE_POWER_CONDITION)) { |
| 1689 | res = nvme_trans_completion(hdr, |
| 1690 | SAM_STAT_CHECK_CONDITION, |
| 1691 | ILLEGAL_REQUEST, |
| 1692 | SCSI_ASC_INVALID_CDB, |
| 1693 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 1694 | goto out_mem; |
| 1695 | } |
| 1696 | index += mp_size; |
| 1697 | } while (index < parm_list_len); |
| 1698 | |
| 1699 | /* In 2nd Iteration, do the NVME Commands */ |
| 1700 | index = saved_index; |
| 1701 | do { |
| 1702 | page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK; |
| 1703 | mp_size = parm_list[index + 1] + 2; |
| 1704 | res = nvme_trans_modesel_get_mp(ns, hdr, &parm_list[index], |
| 1705 | page_code); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1706 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1707 | break; |
| 1708 | index += mp_size; |
| 1709 | } while (index < parm_list_len); |
| 1710 | |
| 1711 | out_mem: |
| 1712 | kfree(parm_list); |
| 1713 | out: |
| 1714 | return res; |
| 1715 | } |
| 1716 | |
| 1717 | /* Format Unit Helper Functions */ |
| 1718 | |
| 1719 | static int nvme_trans_fmt_set_blk_size_count(struct nvme_ns *ns, |
| 1720 | struct sg_io_hdr *hdr) |
| 1721 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1722 | int res = 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1723 | int nvme_sc; |
| 1724 | struct nvme_dev *dev = ns->dev; |
| 1725 | dma_addr_t dma_addr; |
| 1726 | void *mem; |
| 1727 | struct nvme_id_ns *id_ns; |
| 1728 | u8 flbas; |
| 1729 | |
| 1730 | /* |
| 1731 | * SCSI Expects a MODE SELECT would have been issued prior to |
| 1732 | * a FORMAT UNIT, and the block size and number would be used |
| 1733 | * from the block descriptor in it. If a MODE SELECT had not |
| 1734 | * been issued, FORMAT shall use the current values for both. |
| 1735 | */ |
| 1736 | |
| 1737 | if (ns->mode_select_num_blocks == 0 || ns->mode_select_block_len == 0) { |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1738 | mem = dma_alloc_coherent(dev->dev, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1739 | sizeof(struct nvme_id_ns), &dma_addr, GFP_KERNEL); |
| 1740 | if (mem == NULL) { |
| 1741 | res = -ENOMEM; |
| 1742 | goto out; |
| 1743 | } |
| 1744 | /* nvme ns identify */ |
| 1745 | nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); |
| 1746 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 1747 | if (res) |
| 1748 | goto out_dma; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1749 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1750 | id_ns = mem; |
| 1751 | |
| 1752 | if (ns->mode_select_num_blocks == 0) |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1753 | ns->mode_select_num_blocks = le64_to_cpu(id_ns->ncap); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1754 | if (ns->mode_select_block_len == 0) { |
| 1755 | flbas = (id_ns->flbas) & 0x0F; |
| 1756 | ns->mode_select_block_len = |
| 1757 | (1 << (id_ns->lbaf[flbas].ds)); |
| 1758 | } |
| 1759 | out_dma: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1760 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1761 | mem, dma_addr); |
| 1762 | } |
| 1763 | out: |
| 1764 | return res; |
| 1765 | } |
| 1766 | |
| 1767 | static int nvme_trans_fmt_get_parm_header(struct sg_io_hdr *hdr, u8 len, |
| 1768 | u8 format_prot_info, u8 *nvme_pf_code) |
| 1769 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1770 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1771 | u8 *parm_list; |
| 1772 | u8 pf_usage, pf_code; |
| 1773 | |
| 1774 | parm_list = kmalloc(len, GFP_KERNEL); |
| 1775 | if (parm_list == NULL) { |
| 1776 | res = -ENOMEM; |
| 1777 | goto out; |
| 1778 | } |
| 1779 | res = nvme_trans_copy_from_user(hdr, parm_list, len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1780 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1781 | goto out_mem; |
| 1782 | |
| 1783 | if ((parm_list[FORMAT_UNIT_IMMED_OFFSET] & |
| 1784 | FORMAT_UNIT_IMMED_MASK) != 0) { |
| 1785 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 1786 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 1787 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 1788 | goto out_mem; |
| 1789 | } |
| 1790 | |
| 1791 | if (len == FORMAT_UNIT_LONG_PARM_LIST_LEN && |
| 1792 | (parm_list[FORMAT_UNIT_PROT_INT_OFFSET] & 0x0F) != 0) { |
| 1793 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 1794 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 1795 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 1796 | goto out_mem; |
| 1797 | } |
| 1798 | pf_usage = parm_list[FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET] & |
| 1799 | FORMAT_UNIT_PROT_FIELD_USAGE_MASK; |
| 1800 | pf_code = (pf_usage << 2) | format_prot_info; |
| 1801 | switch (pf_code) { |
| 1802 | case 0: |
| 1803 | *nvme_pf_code = 0; |
| 1804 | break; |
| 1805 | case 2: |
| 1806 | *nvme_pf_code = 1; |
| 1807 | break; |
| 1808 | case 3: |
| 1809 | *nvme_pf_code = 2; |
| 1810 | break; |
| 1811 | case 7: |
| 1812 | *nvme_pf_code = 3; |
| 1813 | break; |
| 1814 | default: |
| 1815 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 1816 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 1817 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 1818 | break; |
| 1819 | } |
| 1820 | |
| 1821 | out_mem: |
| 1822 | kfree(parm_list); |
| 1823 | out: |
| 1824 | return res; |
| 1825 | } |
| 1826 | |
| 1827 | static int nvme_trans_fmt_send_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1828 | u8 prot_info) |
| 1829 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1830 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1831 | int nvme_sc; |
| 1832 | struct nvme_dev *dev = ns->dev; |
| 1833 | dma_addr_t dma_addr; |
| 1834 | void *mem; |
| 1835 | struct nvme_id_ns *id_ns; |
| 1836 | u8 i; |
| 1837 | u8 flbas, nlbaf; |
| 1838 | u8 selected_lbaf = 0xFF; |
| 1839 | u32 cdw10 = 0; |
| 1840 | struct nvme_command c; |
| 1841 | |
| 1842 | /* Loop thru LBAF's in id_ns to match reqd lbaf, put in cdw10 */ |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1843 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1844 | &dma_addr, GFP_KERNEL); |
| 1845 | if (mem == NULL) { |
| 1846 | res = -ENOMEM; |
| 1847 | goto out; |
| 1848 | } |
| 1849 | /* nvme ns identify */ |
| 1850 | nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); |
| 1851 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 1852 | if (res) |
| 1853 | goto out_dma; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1854 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1855 | id_ns = mem; |
| 1856 | flbas = (id_ns->flbas) & 0x0F; |
| 1857 | nlbaf = id_ns->nlbaf; |
| 1858 | |
| 1859 | for (i = 0; i < nlbaf; i++) { |
| 1860 | if (ns->mode_select_block_len == (1 << (id_ns->lbaf[i].ds))) { |
| 1861 | selected_lbaf = i; |
| 1862 | break; |
| 1863 | } |
| 1864 | } |
| 1865 | if (selected_lbaf > 0x0F) { |
| 1866 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 1867 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER, |
| 1868 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 1869 | } |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1870 | if (ns->mode_select_num_blocks != le64_to_cpu(id_ns->ncap)) { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1871 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 1872 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER, |
| 1873 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 1874 | } |
| 1875 | |
| 1876 | cdw10 |= prot_info << 5; |
| 1877 | cdw10 |= selected_lbaf & 0x0F; |
| 1878 | memset(&c, 0, sizeof(c)); |
| 1879 | c.format.opcode = nvme_admin_format_nvm; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1880 | c.format.nsid = cpu_to_le32(ns->ns_id); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1881 | c.format.cdw10 = cpu_to_le32(cdw10); |
| 1882 | |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 1883 | nvme_sc = nvme_submit_sync_cmd(dev->admin_q, &c); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1884 | res = nvme_trans_status_code(hdr, nvme_sc); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1885 | |
| 1886 | out_dma: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 1887 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1888 | out: |
| 1889 | return res; |
| 1890 | } |
| 1891 | |
| 1892 | /* Read/Write Helper Functions */ |
| 1893 | |
| 1894 | static inline void nvme_trans_get_io_cdb6(u8 *cmd, |
| 1895 | struct nvme_trans_io_cdb *cdb_info) |
| 1896 | { |
| 1897 | cdb_info->fua = 0; |
| 1898 | cdb_info->prot_info = 0; |
| 1899 | cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_6_CDB_LBA_OFFSET) & |
| 1900 | IO_6_CDB_LBA_MASK; |
| 1901 | cdb_info->xfer_len = GET_U8_FROM_CDB(cmd, IO_6_CDB_TX_LEN_OFFSET); |
| 1902 | |
| 1903 | /* sbc3r27 sec 5.32 - TRANSFER LEN of 0 implies a 256 Block transfer */ |
| 1904 | if (cdb_info->xfer_len == 0) |
| 1905 | cdb_info->xfer_len = IO_6_DEFAULT_TX_LEN; |
| 1906 | } |
| 1907 | |
| 1908 | static inline void nvme_trans_get_io_cdb10(u8 *cmd, |
| 1909 | struct nvme_trans_io_cdb *cdb_info) |
| 1910 | { |
| 1911 | cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_10_CDB_FUA_OFFSET) & |
| 1912 | IO_CDB_FUA_MASK; |
| 1913 | cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_10_CDB_WP_OFFSET) & |
| 1914 | IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT; |
| 1915 | cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_10_CDB_LBA_OFFSET); |
| 1916 | cdb_info->xfer_len = GET_U16_FROM_CDB(cmd, IO_10_CDB_TX_LEN_OFFSET); |
| 1917 | } |
| 1918 | |
| 1919 | static inline void nvme_trans_get_io_cdb12(u8 *cmd, |
| 1920 | struct nvme_trans_io_cdb *cdb_info) |
| 1921 | { |
| 1922 | cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_12_CDB_FUA_OFFSET) & |
| 1923 | IO_CDB_FUA_MASK; |
| 1924 | cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_12_CDB_WP_OFFSET) & |
| 1925 | IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT; |
| 1926 | cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_12_CDB_LBA_OFFSET); |
| 1927 | cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_12_CDB_TX_LEN_OFFSET); |
| 1928 | } |
| 1929 | |
| 1930 | static inline void nvme_trans_get_io_cdb16(u8 *cmd, |
| 1931 | struct nvme_trans_io_cdb *cdb_info) |
| 1932 | { |
| 1933 | cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_16_CDB_FUA_OFFSET) & |
| 1934 | IO_CDB_FUA_MASK; |
| 1935 | cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_16_CDB_WP_OFFSET) & |
| 1936 | IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT; |
| 1937 | cdb_info->lba = GET_U64_FROM_CDB(cmd, IO_16_CDB_LBA_OFFSET); |
| 1938 | cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_16_CDB_TX_LEN_OFFSET); |
| 1939 | } |
| 1940 | |
| 1941 | static inline u32 nvme_trans_io_get_num_cmds(struct sg_io_hdr *hdr, |
| 1942 | struct nvme_trans_io_cdb *cdb_info, |
| 1943 | u32 max_blocks) |
| 1944 | { |
| 1945 | /* If using iovecs, send one nvme command per vector */ |
| 1946 | if (hdr->iovec_count > 0) |
| 1947 | return hdr->iovec_count; |
| 1948 | else if (cdb_info->xfer_len > max_blocks) |
| 1949 | return ((cdb_info->xfer_len - 1) / max_blocks) + 1; |
| 1950 | else |
| 1951 | return 1; |
| 1952 | } |
| 1953 | |
| 1954 | static u16 nvme_trans_io_get_control(struct nvme_ns *ns, |
| 1955 | struct nvme_trans_io_cdb *cdb_info) |
| 1956 | { |
| 1957 | u16 control = 0; |
| 1958 | |
| 1959 | /* When Protection information support is added, implement here */ |
| 1960 | |
| 1961 | if (cdb_info->fua > 0) |
| 1962 | control |= NVME_RW_FUA; |
| 1963 | |
| 1964 | return control; |
| 1965 | } |
| 1966 | |
| 1967 | static int nvme_trans_do_nvme_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 1968 | struct nvme_trans_io_cdb *cdb_info, u8 is_write) |
| 1969 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 1970 | int nvme_sc = NVME_SC_SUCCESS; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1971 | struct nvme_dev *dev = ns->dev; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1972 | u32 num_cmds; |
| 1973 | struct nvme_iod *iod; |
| 1974 | u64 unit_len; |
| 1975 | u64 unit_num_blocks; /* Number of blocks to xfer in each nvme cmd */ |
| 1976 | u32 retcode; |
| 1977 | u32 i = 0; |
| 1978 | u64 nvme_offset = 0; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1979 | void __user *next_mapping_addr; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1980 | struct nvme_command c; |
| 1981 | u8 opcode = (is_write ? nvme_cmd_write : nvme_cmd_read); |
| 1982 | u16 control; |
Keith Busch | ddcb776 | 2014-03-24 10:03:56 -0400 | [diff] [blame] | 1983 | u32 max_blocks = queue_max_hw_sectors(ns->queue); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 1984 | |
| 1985 | num_cmds = nvme_trans_io_get_num_cmds(hdr, cdb_info, max_blocks); |
| 1986 | |
| 1987 | /* |
| 1988 | * This loop handles two cases. |
| 1989 | * First, when an SGL is used in the form of an iovec list: |
| 1990 | * - Use iov_base as the next mapping address for the nvme command_id |
| 1991 | * - Use iov_len as the data transfer length for the command. |
| 1992 | * Second, when we have a single buffer |
| 1993 | * - If larger than max_blocks, split into chunks, offset |
| 1994 | * each nvme command accordingly. |
| 1995 | */ |
| 1996 | for (i = 0; i < num_cmds; i++) { |
| 1997 | memset(&c, 0, sizeof(c)); |
| 1998 | if (hdr->iovec_count > 0) { |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 1999 | struct sg_iovec sgl; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2000 | |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2001 | retcode = copy_from_user(&sgl, hdr->dxferp + |
| 2002 | i * sizeof(struct sg_iovec), |
| 2003 | sizeof(struct sg_iovec)); |
| 2004 | if (retcode) |
| 2005 | return -EFAULT; |
| 2006 | unit_len = sgl.iov_len; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2007 | unit_num_blocks = unit_len >> ns->lba_shift; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2008 | next_mapping_addr = sgl.iov_base; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2009 | } else { |
| 2010 | unit_num_blocks = min((u64)max_blocks, |
| 2011 | (cdb_info->xfer_len - nvme_offset)); |
| 2012 | unit_len = unit_num_blocks << ns->lba_shift; |
| 2013 | next_mapping_addr = hdr->dxferp + |
| 2014 | ((1 << ns->lba_shift) * nvme_offset); |
| 2015 | } |
| 2016 | |
| 2017 | c.rw.opcode = opcode; |
| 2018 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
| 2019 | c.rw.slba = cpu_to_le64(cdb_info->lba + nvme_offset); |
| 2020 | c.rw.length = cpu_to_le16(unit_num_blocks - 1); |
| 2021 | control = nvme_trans_io_get_control(ns, cdb_info); |
| 2022 | c.rw.control = cpu_to_le16(control); |
| 2023 | |
| 2024 | iod = nvme_map_user_pages(dev, |
| 2025 | (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE, |
| 2026 | (unsigned long)next_mapping_addr, unit_len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2027 | if (IS_ERR(iod)) |
| 2028 | return PTR_ERR(iod); |
| 2029 | |
Keith Busch | edd10d3 | 2014-04-03 16:45:23 -0600 | [diff] [blame] | 2030 | retcode = nvme_setup_prps(dev, iod, unit_len, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2031 | if (retcode != unit_len) { |
| 2032 | nvme_unmap_user_pages(dev, |
| 2033 | (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE, |
| 2034 | iod); |
| 2035 | nvme_free_iod(dev, iod); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2036 | return -ENOMEM; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2037 | } |
Keith Busch | edd10d3 | 2014-04-03 16:45:23 -0600 | [diff] [blame] | 2038 | c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
| 2039 | c.rw.prp2 = cpu_to_le64(iod->first_dma); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2040 | |
| 2041 | nvme_offset += unit_num_blocks; |
| 2042 | |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 2043 | nvme_sc = nvme_submit_sync_cmd(ns->queue, &c); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2044 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2045 | nvme_unmap_user_pages(dev, |
| 2046 | (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE, |
| 2047 | iod); |
| 2048 | nvme_free_iod(dev, iod); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2049 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2050 | |
| 2051 | if (nvme_sc != NVME_SC_SUCCESS) |
| 2052 | break; |
| 2053 | } |
| 2054 | |
| 2055 | return nvme_trans_status_code(hdr, nvme_sc); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2056 | } |
| 2057 | |
| 2058 | |
| 2059 | /* SCSI Command Translation Functions */ |
| 2060 | |
| 2061 | static int nvme_trans_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, u8 is_write, |
| 2062 | u8 *cmd) |
| 2063 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2064 | int res = 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2065 | struct nvme_trans_io_cdb cdb_info; |
| 2066 | u8 opcode = cmd[0]; |
| 2067 | u64 xfer_bytes; |
| 2068 | u64 sum_iov_len = 0; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2069 | struct sg_iovec sgl; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2070 | int i; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2071 | size_t not_copied; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2072 | |
| 2073 | /* Extract Fields from CDB */ |
| 2074 | switch (opcode) { |
| 2075 | case WRITE_6: |
| 2076 | case READ_6: |
| 2077 | nvme_trans_get_io_cdb6(cmd, &cdb_info); |
| 2078 | break; |
| 2079 | case WRITE_10: |
| 2080 | case READ_10: |
| 2081 | nvme_trans_get_io_cdb10(cmd, &cdb_info); |
| 2082 | break; |
| 2083 | case WRITE_12: |
| 2084 | case READ_12: |
| 2085 | nvme_trans_get_io_cdb12(cmd, &cdb_info); |
| 2086 | break; |
| 2087 | case WRITE_16: |
| 2088 | case READ_16: |
| 2089 | nvme_trans_get_io_cdb16(cmd, &cdb_info); |
| 2090 | break; |
| 2091 | default: |
| 2092 | /* Will never really reach here */ |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2093 | res = -EIO; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2094 | goto out; |
| 2095 | } |
| 2096 | |
| 2097 | /* Calculate total length of transfer (in bytes) */ |
| 2098 | if (hdr->iovec_count > 0) { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2099 | for (i = 0; i < hdr->iovec_count; i++) { |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2100 | not_copied = copy_from_user(&sgl, hdr->dxferp + |
| 2101 | i * sizeof(struct sg_iovec), |
| 2102 | sizeof(struct sg_iovec)); |
| 2103 | if (not_copied) |
| 2104 | return -EFAULT; |
| 2105 | sum_iov_len += sgl.iov_len; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2106 | /* IO vector sizes should be multiples of block size */ |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2107 | if (sgl.iov_len % (1 << ns->lba_shift) != 0) { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2108 | res = nvme_trans_completion(hdr, |
| 2109 | SAM_STAT_CHECK_CONDITION, |
| 2110 | ILLEGAL_REQUEST, |
| 2111 | SCSI_ASC_INVALID_PARAMETER, |
| 2112 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2113 | goto out; |
| 2114 | } |
| 2115 | } |
| 2116 | } else { |
| 2117 | sum_iov_len = hdr->dxfer_len; |
| 2118 | } |
| 2119 | |
| 2120 | /* As Per sg ioctl howto, if the lengths differ, use the lower one */ |
| 2121 | xfer_bytes = min(((u64)hdr->dxfer_len), sum_iov_len); |
| 2122 | |
| 2123 | /* If block count and actual data buffer size dont match, error out */ |
| 2124 | if (xfer_bytes != (cdb_info.xfer_len << ns->lba_shift)) { |
| 2125 | res = -EINVAL; |
| 2126 | goto out; |
| 2127 | } |
| 2128 | |
| 2129 | /* Check for 0 length transfer - it is not illegal */ |
| 2130 | if (cdb_info.xfer_len == 0) |
| 2131 | goto out; |
| 2132 | |
| 2133 | /* Send NVMe IO Command(s) */ |
| 2134 | res = nvme_trans_do_nvme_io(ns, hdr, &cdb_info, is_write); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2135 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2136 | goto out; |
| 2137 | |
| 2138 | out: |
| 2139 | return res; |
| 2140 | } |
| 2141 | |
| 2142 | static int nvme_trans_inquiry(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2143 | u8 *cmd) |
| 2144 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2145 | int res = 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2146 | u8 evpd; |
| 2147 | u8 page_code; |
| 2148 | int alloc_len; |
| 2149 | u8 *inq_response; |
| 2150 | |
| 2151 | evpd = GET_INQ_EVPD_BIT(cmd); |
| 2152 | page_code = GET_INQ_PAGE_CODE(cmd); |
| 2153 | alloc_len = GET_INQ_ALLOC_LENGTH(cmd); |
| 2154 | |
Keith Busch | 4f1982b | 2015-02-19 13:42:14 -0700 | [diff] [blame] | 2155 | inq_response = kmalloc(alloc_len, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2156 | if (inq_response == NULL) { |
| 2157 | res = -ENOMEM; |
| 2158 | goto out_mem; |
| 2159 | } |
| 2160 | |
| 2161 | if (evpd == 0) { |
| 2162 | if (page_code == INQ_STANDARD_INQUIRY_PAGE) { |
| 2163 | res = nvme_trans_standard_inquiry_page(ns, hdr, |
| 2164 | inq_response, alloc_len); |
| 2165 | } else { |
| 2166 | res = nvme_trans_completion(hdr, |
| 2167 | SAM_STAT_CHECK_CONDITION, |
| 2168 | ILLEGAL_REQUEST, |
| 2169 | SCSI_ASC_INVALID_CDB, |
| 2170 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2171 | } |
| 2172 | } else { |
| 2173 | switch (page_code) { |
| 2174 | case VPD_SUPPORTED_PAGES: |
| 2175 | res = nvme_trans_supported_vpd_pages(ns, hdr, |
| 2176 | inq_response, alloc_len); |
| 2177 | break; |
| 2178 | case VPD_SERIAL_NUMBER: |
| 2179 | res = nvme_trans_unit_serial_page(ns, hdr, inq_response, |
| 2180 | alloc_len); |
| 2181 | break; |
| 2182 | case VPD_DEVICE_IDENTIFIERS: |
| 2183 | res = nvme_trans_device_id_page(ns, hdr, inq_response, |
| 2184 | alloc_len); |
| 2185 | break; |
| 2186 | case VPD_EXTENDED_INQUIRY: |
| 2187 | res = nvme_trans_ext_inq_page(ns, hdr, alloc_len); |
| 2188 | break; |
Keith Busch | 7f749d9 | 2015-04-07 15:34:18 -0600 | [diff] [blame] | 2189 | case VPD_BLOCK_LIMITS: |
| 2190 | res = nvme_trans_bdev_limits_page(ns, hdr, inq_response, |
| 2191 | alloc_len); |
| 2192 | break; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2193 | case VPD_BLOCK_DEV_CHARACTERISTICS: |
| 2194 | res = nvme_trans_bdev_char_page(ns, hdr, alloc_len); |
| 2195 | break; |
| 2196 | default: |
| 2197 | res = nvme_trans_completion(hdr, |
| 2198 | SAM_STAT_CHECK_CONDITION, |
| 2199 | ILLEGAL_REQUEST, |
| 2200 | SCSI_ASC_INVALID_CDB, |
| 2201 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2202 | break; |
| 2203 | } |
| 2204 | } |
| 2205 | kfree(inq_response); |
| 2206 | out_mem: |
| 2207 | return res; |
| 2208 | } |
| 2209 | |
| 2210 | static int nvme_trans_log_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2211 | u8 *cmd) |
| 2212 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2213 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2214 | u16 alloc_len; |
| 2215 | u8 sp; |
| 2216 | u8 pc; |
| 2217 | u8 page_code; |
| 2218 | |
| 2219 | sp = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_SP_OFFSET); |
| 2220 | if (sp != LOG_SENSE_CDB_SP_NOT_ENABLED) { |
| 2221 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2222 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2223 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2224 | goto out; |
| 2225 | } |
| 2226 | pc = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_PC_OFFSET); |
| 2227 | page_code = pc & LOG_SENSE_CDB_PAGE_CODE_MASK; |
| 2228 | pc = (pc & LOG_SENSE_CDB_PC_MASK) >> LOG_SENSE_CDB_PC_SHIFT; |
| 2229 | if (pc != LOG_SENSE_CDB_PC_CUMULATIVE_VALUES) { |
| 2230 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2231 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2232 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2233 | goto out; |
| 2234 | } |
| 2235 | alloc_len = GET_U16_FROM_CDB(cmd, LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET); |
| 2236 | switch (page_code) { |
| 2237 | case LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE: |
| 2238 | res = nvme_trans_log_supp_pages(ns, hdr, alloc_len); |
| 2239 | break; |
| 2240 | case LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE: |
| 2241 | res = nvme_trans_log_info_exceptions(ns, hdr, alloc_len); |
| 2242 | break; |
| 2243 | case LOG_PAGE_TEMPERATURE_PAGE: |
| 2244 | res = nvme_trans_log_temperature(ns, hdr, alloc_len); |
| 2245 | break; |
| 2246 | default: |
| 2247 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2248 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2249 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2250 | break; |
| 2251 | } |
| 2252 | |
| 2253 | out: |
| 2254 | return res; |
| 2255 | } |
| 2256 | |
| 2257 | static int nvme_trans_mode_select(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2258 | u8 *cmd) |
| 2259 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2260 | u8 cdb10 = 0; |
| 2261 | u16 parm_list_len; |
| 2262 | u8 page_format; |
| 2263 | u8 save_pages; |
| 2264 | |
| 2265 | page_format = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_PAGE_FORMAT_OFFSET); |
| 2266 | page_format &= MODE_SELECT_CDB_PAGE_FORMAT_MASK; |
| 2267 | |
| 2268 | save_pages = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_SAVE_PAGES_OFFSET); |
| 2269 | save_pages &= MODE_SELECT_CDB_SAVE_PAGES_MASK; |
| 2270 | |
| 2271 | if (GET_OPCODE(cmd) == MODE_SELECT) { |
| 2272 | parm_list_len = GET_U8_FROM_CDB(cmd, |
| 2273 | MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET); |
| 2274 | } else { |
| 2275 | parm_list_len = GET_U16_FROM_CDB(cmd, |
| 2276 | MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET); |
| 2277 | cdb10 = 1; |
| 2278 | } |
| 2279 | |
| 2280 | if (parm_list_len != 0) { |
| 2281 | /* |
| 2282 | * According to SPC-4 r24, a paramter list length field of 0 |
| 2283 | * shall not be considered an error |
| 2284 | */ |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2285 | return nvme_trans_modesel_data(ns, hdr, cmd, parm_list_len, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2286 | page_format, save_pages, cdb10); |
| 2287 | } |
| 2288 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2289 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2290 | } |
| 2291 | |
| 2292 | static int nvme_trans_mode_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2293 | u8 *cmd) |
| 2294 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2295 | int res = 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2296 | u16 alloc_len; |
| 2297 | u8 cdb10 = 0; |
| 2298 | u8 page_code; |
| 2299 | u8 pc; |
| 2300 | |
| 2301 | if (GET_OPCODE(cmd) == MODE_SENSE) { |
| 2302 | alloc_len = GET_U8_FROM_CDB(cmd, MODE_SENSE6_ALLOC_LEN_OFFSET); |
| 2303 | } else { |
| 2304 | alloc_len = GET_U16_FROM_CDB(cmd, |
| 2305 | MODE_SENSE10_ALLOC_LEN_OFFSET); |
| 2306 | cdb10 = 1; |
| 2307 | } |
| 2308 | |
| 2309 | pc = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CONTROL_OFFSET) & |
| 2310 | MODE_SENSE_PAGE_CONTROL_MASK; |
| 2311 | if (pc != MODE_SENSE_PC_CURRENT_VALUES) { |
| 2312 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2313 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2314 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2315 | goto out; |
| 2316 | } |
| 2317 | |
| 2318 | page_code = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CODE_OFFSET) & |
| 2319 | MODE_SENSE_PAGE_CODE_MASK; |
| 2320 | switch (page_code) { |
| 2321 | case MODE_PAGE_CACHING: |
| 2322 | res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, |
| 2323 | cdb10, |
| 2324 | &nvme_trans_fill_caching_page, |
| 2325 | MODE_PAGE_CACHING_LEN); |
| 2326 | break; |
| 2327 | case MODE_PAGE_CONTROL: |
| 2328 | res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, |
| 2329 | cdb10, |
| 2330 | &nvme_trans_fill_control_page, |
| 2331 | MODE_PAGE_CONTROL_LEN); |
| 2332 | break; |
| 2333 | case MODE_PAGE_POWER_CONDITION: |
| 2334 | res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, |
| 2335 | cdb10, |
| 2336 | &nvme_trans_fill_pow_cnd_page, |
| 2337 | MODE_PAGE_POW_CND_LEN); |
| 2338 | break; |
| 2339 | case MODE_PAGE_INFO_EXCEP: |
| 2340 | res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, |
| 2341 | cdb10, |
| 2342 | &nvme_trans_fill_inf_exc_page, |
| 2343 | MODE_PAGE_INF_EXC_LEN); |
| 2344 | break; |
| 2345 | case MODE_PAGE_RETURN_ALL: |
| 2346 | res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len, |
| 2347 | cdb10, |
| 2348 | &nvme_trans_fill_all_pages, |
| 2349 | MODE_PAGE_ALL_LEN); |
| 2350 | break; |
| 2351 | default: |
| 2352 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2353 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2354 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2355 | break; |
| 2356 | } |
| 2357 | |
| 2358 | out: |
| 2359 | return res; |
| 2360 | } |
| 2361 | |
| 2362 | static int nvme_trans_read_capacity(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2363 | u8 *cmd) |
| 2364 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2365 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2366 | int nvme_sc; |
| 2367 | u32 alloc_len = READ_CAP_10_RESP_SIZE; |
| 2368 | u32 resp_size = READ_CAP_10_RESP_SIZE; |
| 2369 | u32 xfer_len; |
| 2370 | u8 cdb16; |
| 2371 | struct nvme_dev *dev = ns->dev; |
| 2372 | dma_addr_t dma_addr; |
| 2373 | void *mem; |
| 2374 | struct nvme_id_ns *id_ns; |
| 2375 | u8 *response; |
| 2376 | |
| 2377 | cdb16 = IS_READ_CAP_16(cmd); |
| 2378 | if (cdb16) { |
| 2379 | alloc_len = GET_READ_CAP_16_ALLOC_LENGTH(cmd); |
| 2380 | resp_size = READ_CAP_16_RESP_SIZE; |
| 2381 | } |
| 2382 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 2383 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ns), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2384 | &dma_addr, GFP_KERNEL); |
| 2385 | if (mem == NULL) { |
| 2386 | res = -ENOMEM; |
| 2387 | goto out; |
| 2388 | } |
| 2389 | /* nvme ns identify */ |
| 2390 | nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr); |
| 2391 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 2392 | if (res) |
| 2393 | goto out_dma; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2394 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2395 | id_ns = mem; |
| 2396 | |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 2397 | response = kzalloc(resp_size, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2398 | if (response == NULL) { |
| 2399 | res = -ENOMEM; |
| 2400 | goto out_dma; |
| 2401 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2402 | nvme_trans_fill_read_cap(response, id_ns, cdb16); |
| 2403 | |
| 2404 | xfer_len = min(alloc_len, resp_size); |
| 2405 | res = nvme_trans_copy_to_user(hdr, response, xfer_len); |
| 2406 | |
| 2407 | kfree(response); |
| 2408 | out_dma: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 2409 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ns), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2410 | out: |
| 2411 | return res; |
| 2412 | } |
| 2413 | |
| 2414 | static int nvme_trans_report_luns(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2415 | u8 *cmd) |
| 2416 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2417 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2418 | int nvme_sc; |
| 2419 | u32 alloc_len, xfer_len, resp_size; |
| 2420 | u8 select_report; |
| 2421 | u8 *response; |
| 2422 | struct nvme_dev *dev = ns->dev; |
| 2423 | dma_addr_t dma_addr; |
| 2424 | void *mem; |
| 2425 | struct nvme_id_ctrl *id_ctrl; |
| 2426 | u32 ll_length, lun_id; |
| 2427 | u8 lun_id_offset = REPORT_LUNS_FIRST_LUN_OFFSET; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2428 | __be32 tmp_len; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2429 | |
| 2430 | alloc_len = GET_REPORT_LUNS_ALLOC_LENGTH(cmd); |
| 2431 | select_report = GET_U8_FROM_CDB(cmd, REPORT_LUNS_SR_OFFSET); |
| 2432 | |
| 2433 | if ((select_report != ALL_LUNS_RETURNED) && |
| 2434 | (select_report != ALL_WELL_KNOWN_LUNS_RETURNED) && |
| 2435 | (select_report != RESTRICTED_LUNS_RETURNED)) { |
| 2436 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2437 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2438 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2439 | goto out; |
| 2440 | } else { |
| 2441 | /* NVMe Controller Identify */ |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 2442 | mem = dma_alloc_coherent(dev->dev, sizeof(struct nvme_id_ctrl), |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2443 | &dma_addr, GFP_KERNEL); |
| 2444 | if (mem == NULL) { |
| 2445 | res = -ENOMEM; |
| 2446 | goto out; |
| 2447 | } |
| 2448 | nvme_sc = nvme_identify(dev, 0, 1, dma_addr); |
| 2449 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 2450 | if (res) |
| 2451 | goto out_dma; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2452 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2453 | id_ctrl = mem; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2454 | ll_length = le32_to_cpu(id_ctrl->nn) * LUN_ENTRY_SIZE; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2455 | resp_size = ll_length + LUN_DATA_HEADER_SIZE; |
| 2456 | |
| 2457 | if (alloc_len < resp_size) { |
| 2458 | res = nvme_trans_completion(hdr, |
| 2459 | SAM_STAT_CHECK_CONDITION, |
| 2460 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2461 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2462 | goto out_dma; |
| 2463 | } |
| 2464 | |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 2465 | response = kzalloc(resp_size, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2466 | if (response == NULL) { |
| 2467 | res = -ENOMEM; |
| 2468 | goto out_dma; |
| 2469 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2470 | |
| 2471 | /* The first LUN ID will always be 0 per the SAM spec */ |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2472 | for (lun_id = 0; lun_id < le32_to_cpu(id_ctrl->nn); lun_id++) { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2473 | /* |
| 2474 | * Set the LUN Id and then increment to the next LUN |
| 2475 | * location in the parameter data. |
| 2476 | */ |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2477 | __be64 tmp_id = cpu_to_be64(lun_id); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2478 | memcpy(&response[lun_id_offset], &tmp_id, sizeof(u64)); |
| 2479 | lun_id_offset += LUN_ENTRY_SIZE; |
| 2480 | } |
| 2481 | tmp_len = cpu_to_be32(ll_length); |
| 2482 | memcpy(response, &tmp_len, sizeof(u32)); |
| 2483 | } |
| 2484 | |
| 2485 | xfer_len = min(alloc_len, resp_size); |
| 2486 | res = nvme_trans_copy_to_user(hdr, response, xfer_len); |
| 2487 | |
| 2488 | kfree(response); |
| 2489 | out_dma: |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 2490 | dma_free_coherent(dev->dev, sizeof(struct nvme_id_ctrl), mem, dma_addr); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2491 | out: |
| 2492 | return res; |
| 2493 | } |
| 2494 | |
| 2495 | static int nvme_trans_request_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2496 | u8 *cmd) |
| 2497 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2498 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2499 | u8 alloc_len, xfer_len, resp_size; |
| 2500 | u8 desc_format; |
| 2501 | u8 *response; |
| 2502 | |
| 2503 | alloc_len = GET_REQUEST_SENSE_ALLOC_LENGTH(cmd); |
| 2504 | desc_format = GET_U8_FROM_CDB(cmd, REQUEST_SENSE_DESC_OFFSET); |
| 2505 | desc_format &= REQUEST_SENSE_DESC_MASK; |
| 2506 | |
| 2507 | resp_size = ((desc_format) ? (DESC_FMT_SENSE_DATA_SIZE) : |
| 2508 | (FIXED_FMT_SENSE_DATA_SIZE)); |
Tushar Behera | 03ea83e | 2013-06-10 10:20:55 +0530 | [diff] [blame] | 2509 | response = kzalloc(resp_size, GFP_KERNEL); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2510 | if (response == NULL) { |
| 2511 | res = -ENOMEM; |
| 2512 | goto out; |
| 2513 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2514 | |
| 2515 | if (desc_format == DESCRIPTOR_FORMAT_SENSE_DATA_TYPE) { |
| 2516 | /* Descriptor Format Sense Data */ |
| 2517 | response[0] = DESC_FORMAT_SENSE_DATA; |
| 2518 | response[1] = NO_SENSE; |
| 2519 | /* TODO How is LOW POWER CONDITION ON handled? (byte 2) */ |
| 2520 | response[2] = SCSI_ASC_NO_SENSE; |
| 2521 | response[3] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 2522 | /* SDAT_OVFL = 0 | Additional Sense Length = 0 */ |
| 2523 | } else { |
| 2524 | /* Fixed Format Sense Data */ |
| 2525 | response[0] = FIXED_SENSE_DATA; |
| 2526 | /* Byte 1 = Obsolete */ |
| 2527 | response[2] = NO_SENSE; /* FM, EOM, ILI, SDAT_OVFL = 0 */ |
| 2528 | /* Bytes 3-6 - Information - set to zero */ |
| 2529 | response[7] = FIXED_SENSE_DATA_ADD_LENGTH; |
| 2530 | /* Bytes 8-11 - Cmd Specific Information - set to zero */ |
| 2531 | response[12] = SCSI_ASC_NO_SENSE; |
| 2532 | response[13] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE; |
| 2533 | /* Byte 14 = Field Replaceable Unit Code = 0 */ |
| 2534 | /* Bytes 15-17 - SKSV=0; Sense Key Specific = 0 */ |
| 2535 | } |
| 2536 | |
| 2537 | xfer_len = min(alloc_len, resp_size); |
| 2538 | res = nvme_trans_copy_to_user(hdr, response, xfer_len); |
| 2539 | |
| 2540 | kfree(response); |
| 2541 | out: |
| 2542 | return res; |
| 2543 | } |
| 2544 | |
| 2545 | static int nvme_trans_security_protocol(struct nvme_ns *ns, |
| 2546 | struct sg_io_hdr *hdr, |
| 2547 | u8 *cmd) |
| 2548 | { |
| 2549 | return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2550 | ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND, |
| 2551 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2552 | } |
| 2553 | |
| 2554 | static int nvme_trans_start_stop(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2555 | u8 *cmd) |
| 2556 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2557 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2558 | int nvme_sc; |
Keith Busch | 14385de | 2013-04-25 14:39:27 -0600 | [diff] [blame] | 2559 | struct nvme_command c; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2560 | u8 immed, pcmod, pc, no_flush, start; |
| 2561 | |
| 2562 | immed = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_IMMED_OFFSET); |
| 2563 | pcmod = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET); |
| 2564 | pc = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_OFFSET); |
| 2565 | no_flush = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_NO_FLUSH_OFFSET); |
| 2566 | start = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_START_OFFSET); |
| 2567 | |
| 2568 | immed &= START_STOP_UNIT_CDB_IMMED_MASK; |
| 2569 | pcmod &= START_STOP_UNIT_CDB_POWER_COND_MOD_MASK; |
| 2570 | pc = (pc & START_STOP_UNIT_CDB_POWER_COND_MASK) >> NIBBLE_SHIFT; |
| 2571 | no_flush &= START_STOP_UNIT_CDB_NO_FLUSH_MASK; |
| 2572 | start &= START_STOP_UNIT_CDB_START_MASK; |
| 2573 | |
| 2574 | if (immed != 0) { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2575 | return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2576 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2577 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2578 | } else { |
| 2579 | if (no_flush == 0) { |
| 2580 | /* Issue NVME FLUSH command prior to START STOP UNIT */ |
Keith Busch | 14385de | 2013-04-25 14:39:27 -0600 | [diff] [blame] | 2581 | memset(&c, 0, sizeof(c)); |
| 2582 | c.common.opcode = nvme_cmd_flush; |
| 2583 | c.common.nsid = cpu_to_le32(ns->ns_id); |
| 2584 | |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 2585 | nvme_sc = nvme_submit_sync_cmd(ns->queue, &c); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2586 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 2587 | if (res) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2588 | return res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2589 | } |
| 2590 | /* Setup the expected power state transition */ |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2591 | return nvme_trans_power_state(ns, hdr, pc, pcmod, start); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2592 | } |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2593 | } |
| 2594 | |
| 2595 | static int nvme_trans_synchronize_cache(struct nvme_ns *ns, |
| 2596 | struct sg_io_hdr *hdr, u8 *cmd) |
| 2597 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2598 | int nvme_sc; |
Keith Busch | 14385de | 2013-04-25 14:39:27 -0600 | [diff] [blame] | 2599 | struct nvme_command c; |
Keith Busch | 14385de | 2013-04-25 14:39:27 -0600 | [diff] [blame] | 2600 | |
| 2601 | memset(&c, 0, sizeof(c)); |
| 2602 | c.common.opcode = nvme_cmd_flush; |
| 2603 | c.common.nsid = cpu_to_le32(ns->ns_id); |
| 2604 | |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 2605 | nvme_sc = nvme_submit_sync_cmd(ns->queue, &c); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2606 | return nvme_trans_status_code(hdr, nvme_sc); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2607 | } |
| 2608 | |
| 2609 | static int nvme_trans_format_unit(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2610 | u8 *cmd) |
| 2611 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2612 | int res; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2613 | u8 parm_hdr_len = 0; |
| 2614 | u8 nvme_pf_code = 0; |
| 2615 | u8 format_prot_info, long_list, format_data; |
| 2616 | |
| 2617 | format_prot_info = GET_U8_FROM_CDB(cmd, |
| 2618 | FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET); |
| 2619 | long_list = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_LONG_LIST_OFFSET); |
| 2620 | format_data = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET); |
| 2621 | |
| 2622 | format_prot_info = (format_prot_info & |
| 2623 | FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK) >> |
| 2624 | FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT; |
| 2625 | long_list &= FORMAT_UNIT_CDB_LONG_LIST_MASK; |
| 2626 | format_data &= FORMAT_UNIT_CDB_FORMAT_DATA_MASK; |
| 2627 | |
| 2628 | if (format_data != 0) { |
| 2629 | if (format_prot_info != 0) { |
| 2630 | if (long_list == 0) |
| 2631 | parm_hdr_len = FORMAT_UNIT_SHORT_PARM_LIST_LEN; |
| 2632 | else |
| 2633 | parm_hdr_len = FORMAT_UNIT_LONG_PARM_LIST_LEN; |
| 2634 | } |
| 2635 | } else if (format_data == 0 && format_prot_info != 0) { |
| 2636 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2637 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2638 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2639 | goto out; |
| 2640 | } |
| 2641 | |
| 2642 | /* Get parm header from data-in/out buffer */ |
| 2643 | /* |
| 2644 | * According to the translation spec, the only fields in the parameter |
| 2645 | * list we are concerned with are in the header. So allocate only that. |
| 2646 | */ |
| 2647 | if (parm_hdr_len > 0) { |
| 2648 | res = nvme_trans_fmt_get_parm_header(hdr, parm_hdr_len, |
| 2649 | format_prot_info, &nvme_pf_code); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2650 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2651 | goto out; |
| 2652 | } |
| 2653 | |
| 2654 | /* Attempt to activate any previously downloaded firmware image */ |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 2655 | res = nvme_trans_send_activate_fw_cmd(ns, hdr, 0); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2656 | |
| 2657 | /* Determine Block size and count and send format command */ |
| 2658 | res = nvme_trans_fmt_set_blk_size_count(ns, hdr); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2659 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2660 | goto out; |
| 2661 | |
| 2662 | res = nvme_trans_fmt_send_cmd(ns, hdr, nvme_pf_code); |
| 2663 | |
| 2664 | out: |
| 2665 | return res; |
| 2666 | } |
| 2667 | |
| 2668 | static int nvme_trans_test_unit_ready(struct nvme_ns *ns, |
| 2669 | struct sg_io_hdr *hdr, |
| 2670 | u8 *cmd) |
| 2671 | { |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2672 | struct nvme_dev *dev = ns->dev; |
| 2673 | |
| 2674 | if (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2675 | return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2676 | NOT_READY, SCSI_ASC_LUN_NOT_READY, |
| 2677 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2678 | else |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2679 | return nvme_trans_completion(hdr, SAM_STAT_GOOD, NO_SENSE, 0, 0); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2680 | } |
| 2681 | |
| 2682 | static int nvme_trans_write_buffer(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2683 | u8 *cmd) |
| 2684 | { |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2685 | int res = 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2686 | u32 buffer_offset, parm_list_length; |
| 2687 | u8 buffer_id, mode; |
| 2688 | |
| 2689 | parm_list_length = |
| 2690 | GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET); |
| 2691 | if (parm_list_length % BYTES_TO_DWORDS != 0) { |
| 2692 | /* NVMe expects Firmware file to be a whole number of DWORDS */ |
| 2693 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2694 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2695 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2696 | goto out; |
| 2697 | } |
| 2698 | buffer_id = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_ID_OFFSET); |
| 2699 | if (buffer_id > NVME_MAX_FIRMWARE_SLOT) { |
| 2700 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2701 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2702 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2703 | goto out; |
| 2704 | } |
| 2705 | mode = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_MODE_OFFSET) & |
| 2706 | WRITE_BUFFER_CDB_MODE_MASK; |
| 2707 | buffer_offset = |
| 2708 | GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET); |
| 2709 | |
| 2710 | switch (mode) { |
| 2711 | case DOWNLOAD_SAVE_ACTIVATE: |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 2712 | res = nvme_trans_send_download_fw_cmd(ns, hdr, nvme_admin_download_fw, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2713 | parm_list_length, buffer_offset, |
| 2714 | buffer_id); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2715 | if (res) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2716 | goto out; |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 2717 | res = nvme_trans_send_activate_fw_cmd(ns, hdr, buffer_id); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2718 | break; |
| 2719 | case DOWNLOAD_SAVE_DEFER_ACTIVATE: |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 2720 | res = nvme_trans_send_download_fw_cmd(ns, hdr, nvme_admin_download_fw, |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2721 | parm_list_length, buffer_offset, |
| 2722 | buffer_id); |
| 2723 | break; |
| 2724 | case ACTIVATE_DEFERRED_MICROCODE: |
Christoph Hellwig | b90c48d | 2015-05-22 11:12:40 +0200 | [diff] [blame] | 2725 | res = nvme_trans_send_activate_fw_cmd(ns, hdr, buffer_id); |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2726 | break; |
| 2727 | default: |
| 2728 | res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2729 | ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB, |
| 2730 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2731 | break; |
| 2732 | } |
| 2733 | |
| 2734 | out: |
| 2735 | return res; |
| 2736 | } |
| 2737 | |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 2738 | struct scsi_unmap_blk_desc { |
| 2739 | __be64 slba; |
| 2740 | __be32 nlb; |
| 2741 | u32 resv; |
| 2742 | }; |
| 2743 | |
| 2744 | struct scsi_unmap_parm_list { |
| 2745 | __be16 unmap_data_len; |
| 2746 | __be16 unmap_blk_desc_data_len; |
| 2747 | u32 resv; |
| 2748 | struct scsi_unmap_blk_desc desc[0]; |
| 2749 | }; |
| 2750 | |
| 2751 | static int nvme_trans_unmap(struct nvme_ns *ns, struct sg_io_hdr *hdr, |
| 2752 | u8 *cmd) |
| 2753 | { |
| 2754 | struct nvme_dev *dev = ns->dev; |
| 2755 | struct scsi_unmap_parm_list *plist; |
| 2756 | struct nvme_dsm_range *range; |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 2757 | struct nvme_command c; |
| 2758 | int i, nvme_sc, res = -ENOMEM; |
| 2759 | u16 ndesc, list_len; |
| 2760 | dma_addr_t dma_addr; |
| 2761 | |
| 2762 | list_len = GET_U16_FROM_CDB(cmd, UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET); |
| 2763 | if (!list_len) |
| 2764 | return -EINVAL; |
| 2765 | |
| 2766 | plist = kmalloc(list_len, GFP_KERNEL); |
| 2767 | if (!plist) |
| 2768 | return -ENOMEM; |
| 2769 | |
| 2770 | res = nvme_trans_copy_from_user(hdr, plist, list_len); |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2771 | if (res) |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 2772 | goto out; |
| 2773 | |
| 2774 | ndesc = be16_to_cpu(plist->unmap_blk_desc_data_len) >> 4; |
| 2775 | if (!ndesc || ndesc > 256) { |
| 2776 | res = -EINVAL; |
| 2777 | goto out; |
| 2778 | } |
| 2779 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 2780 | range = dma_alloc_coherent(dev->dev, ndesc * sizeof(*range), |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 2781 | &dma_addr, GFP_KERNEL); |
| 2782 | if (!range) |
| 2783 | goto out; |
| 2784 | |
| 2785 | for (i = 0; i < ndesc; i++) { |
| 2786 | range[i].nlb = cpu_to_le32(be32_to_cpu(plist->desc[i].nlb)); |
| 2787 | range[i].slba = cpu_to_le64(be64_to_cpu(plist->desc[i].slba)); |
| 2788 | range[i].cattr = 0; |
| 2789 | } |
| 2790 | |
| 2791 | memset(&c, 0, sizeof(c)); |
| 2792 | c.dsm.opcode = nvme_cmd_dsm; |
| 2793 | c.dsm.nsid = cpu_to_le32(ns->ns_id); |
| 2794 | c.dsm.prp1 = cpu_to_le64(dma_addr); |
| 2795 | c.dsm.nr = cpu_to_le32(ndesc - 1); |
| 2796 | c.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); |
| 2797 | |
Christoph Hellwig | f705f83 | 2015-05-22 11:12:38 +0200 | [diff] [blame] | 2798 | nvme_sc = nvme_submit_sync_cmd(ns->queue, &c); |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 2799 | res = nvme_trans_status_code(hdr, nvme_sc); |
| 2800 | |
Christoph Hellwig | e75ec75 | 2015-05-22 11:12:39 +0200 | [diff] [blame] | 2801 | dma_free_coherent(dev->dev, ndesc * sizeof(*range), range, dma_addr); |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 2802 | out: |
| 2803 | kfree(plist); |
| 2804 | return res; |
| 2805 | } |
| 2806 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2807 | static int nvme_scsi_translate(struct nvme_ns *ns, struct sg_io_hdr *hdr) |
| 2808 | { |
| 2809 | u8 cmd[BLK_MAX_CDB]; |
| 2810 | int retcode; |
| 2811 | unsigned int opcode; |
| 2812 | |
| 2813 | if (hdr->cmdp == NULL) |
| 2814 | return -EMSGSIZE; |
| 2815 | if (copy_from_user(cmd, hdr->cmdp, hdr->cmd_len)) |
| 2816 | return -EFAULT; |
| 2817 | |
Keith Busch | 695a4fe | 2014-08-27 13:55:39 -0600 | [diff] [blame] | 2818 | /* |
| 2819 | * Prime the hdr with good status for scsi commands that don't require |
| 2820 | * an nvme command for translation. |
| 2821 | */ |
| 2822 | retcode = nvme_trans_status_code(hdr, NVME_SC_SUCCESS); |
| 2823 | if (retcode) |
| 2824 | return retcode; |
| 2825 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2826 | opcode = cmd[0]; |
| 2827 | |
| 2828 | switch (opcode) { |
| 2829 | case READ_6: |
| 2830 | case READ_10: |
| 2831 | case READ_12: |
| 2832 | case READ_16: |
| 2833 | retcode = nvme_trans_io(ns, hdr, 0, cmd); |
| 2834 | break; |
| 2835 | case WRITE_6: |
| 2836 | case WRITE_10: |
| 2837 | case WRITE_12: |
| 2838 | case WRITE_16: |
| 2839 | retcode = nvme_trans_io(ns, hdr, 1, cmd); |
| 2840 | break; |
| 2841 | case INQUIRY: |
| 2842 | retcode = nvme_trans_inquiry(ns, hdr, cmd); |
| 2843 | break; |
| 2844 | case LOG_SENSE: |
| 2845 | retcode = nvme_trans_log_sense(ns, hdr, cmd); |
| 2846 | break; |
| 2847 | case MODE_SELECT: |
| 2848 | case MODE_SELECT_10: |
| 2849 | retcode = nvme_trans_mode_select(ns, hdr, cmd); |
| 2850 | break; |
| 2851 | case MODE_SENSE: |
| 2852 | case MODE_SENSE_10: |
| 2853 | retcode = nvme_trans_mode_sense(ns, hdr, cmd); |
| 2854 | break; |
| 2855 | case READ_CAPACITY: |
| 2856 | retcode = nvme_trans_read_capacity(ns, hdr, cmd); |
| 2857 | break; |
Hannes Reinecke | eb846d9 | 2014-11-17 14:25:19 +0100 | [diff] [blame] | 2858 | case SERVICE_ACTION_IN_16: |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2859 | if (IS_READ_CAP_16(cmd)) |
| 2860 | retcode = nvme_trans_read_capacity(ns, hdr, cmd); |
| 2861 | else |
| 2862 | goto out; |
| 2863 | break; |
| 2864 | case REPORT_LUNS: |
| 2865 | retcode = nvme_trans_report_luns(ns, hdr, cmd); |
| 2866 | break; |
| 2867 | case REQUEST_SENSE: |
| 2868 | retcode = nvme_trans_request_sense(ns, hdr, cmd); |
| 2869 | break; |
| 2870 | case SECURITY_PROTOCOL_IN: |
| 2871 | case SECURITY_PROTOCOL_OUT: |
| 2872 | retcode = nvme_trans_security_protocol(ns, hdr, cmd); |
| 2873 | break; |
| 2874 | case START_STOP: |
| 2875 | retcode = nvme_trans_start_stop(ns, hdr, cmd); |
| 2876 | break; |
| 2877 | case SYNCHRONIZE_CACHE: |
| 2878 | retcode = nvme_trans_synchronize_cache(ns, hdr, cmd); |
| 2879 | break; |
| 2880 | case FORMAT_UNIT: |
| 2881 | retcode = nvme_trans_format_unit(ns, hdr, cmd); |
| 2882 | break; |
| 2883 | case TEST_UNIT_READY: |
| 2884 | retcode = nvme_trans_test_unit_ready(ns, hdr, cmd); |
| 2885 | break; |
| 2886 | case WRITE_BUFFER: |
| 2887 | retcode = nvme_trans_write_buffer(ns, hdr, cmd); |
| 2888 | break; |
Keith Busch | ec50373 | 2013-04-24 15:44:24 -0600 | [diff] [blame] | 2889 | case UNMAP: |
| 2890 | retcode = nvme_trans_unmap(ns, hdr, cmd); |
| 2891 | break; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2892 | default: |
| 2893 | out: |
| 2894 | retcode = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION, |
| 2895 | ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND, |
| 2896 | SCSI_ASCQ_CAUSE_NOT_REPORTABLE); |
| 2897 | break; |
| 2898 | } |
| 2899 | return retcode; |
| 2900 | } |
| 2901 | |
| 2902 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr) |
| 2903 | { |
| 2904 | struct sg_io_hdr hdr; |
| 2905 | int retcode; |
| 2906 | |
| 2907 | if (!capable(CAP_SYS_ADMIN)) |
| 2908 | return -EACCES; |
| 2909 | if (copy_from_user(&hdr, u_hdr, sizeof(hdr))) |
| 2910 | return -EFAULT; |
| 2911 | if (hdr.interface_id != 'S') |
| 2912 | return -EINVAL; |
| 2913 | if (hdr.cmd_len > BLK_MAX_CDB) |
| 2914 | return -EINVAL; |
| 2915 | |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2916 | /* |
| 2917 | * A positive return code means a NVMe status, which has been |
| 2918 | * translated to sense data. |
| 2919 | */ |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2920 | retcode = nvme_scsi_translate(ns, &hdr); |
| 2921 | if (retcode < 0) |
| 2922 | return retcode; |
Vishal Verma | 8741ee4 | 2013-04-04 17:52:27 -0600 | [diff] [blame] | 2923 | if (copy_to_user(u_hdr, &hdr, sizeof(sg_io_hdr_t)) > 0) |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2924 | return -EFAULT; |
Christoph Hellwig | e61b0a8 | 2015-05-22 11:12:41 +0200 | [diff] [blame^] | 2925 | return 0; |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2926 | } |
| 2927 | |
Vishal Verma | 5d0f613 | 2013-03-04 18:40:58 -0700 | [diff] [blame] | 2928 | int nvme_sg_get_version_num(int __user *ip) |
| 2929 | { |
| 2930 | return put_user(sg_version_num, ip); |
| 2931 | } |