Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 12 | #include "msm_drv.h" |
| 13 | #include "sde_hw_mdss.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 14 | #include "sde_hw_util.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 15 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 16 | /* using a file static variables for debugfs access */ |
| 17 | static u32 sde_hw_util_log_mask = SDE_DBG_MASK_NONE; |
| 18 | |
| 19 | void SDE_REG_WRITE(struct sde_hw_blk_reg_map *c, u32 reg_off, u32 val) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 20 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 21 | /* don't need to mutex protect this */ |
| 22 | if (c->log_mask & sde_hw_util_log_mask) |
| 23 | DBG("[0x%X] <= 0x%X", c->blk_off + reg_off, val); |
| 24 | writel_relaxed(val, c->base_off + c->blk_off + reg_off); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 25 | } |
| 26 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 27 | int SDE_REG_READ(struct sde_hw_blk_reg_map *c, u32 reg_off) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 28 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 29 | return readl_relaxed(c->base_off + c->blk_off + reg_off); |
| 30 | } |
| 31 | |
| 32 | u32 *sde_hw_util_get_log_mask_ptr(void) |
| 33 | { |
| 34 | return &sde_hw_util_log_mask; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 35 | } |
| 36 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 37 | void sde_hw_csc_setup(struct sde_hw_blk_reg_map *c, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 38 | u32 csc_reg_off, |
| 39 | struct sde_csc_cfg *data) |
| 40 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 41 | static const u32 matrix_shift = 7; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 42 | u32 val; |
| 43 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 44 | /* matrix coeff - convert S15.16 to S4.9 */ |
| 45 | val = ((data->csc_mv[0] >> matrix_shift) & 0x1FFF) | |
| 46 | (((data->csc_mv[1] >> matrix_shift) & 0x1FFF) << 16); |
| 47 | SDE_REG_WRITE(c, csc_reg_off, val); |
| 48 | val = ((data->csc_mv[2] >> matrix_shift) & 0x1FFF) | |
| 49 | (((data->csc_mv[3] >> matrix_shift) & 0x1FFF) << 16); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 50 | SDE_REG_WRITE(c, csc_reg_off + 0x4, val); |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 51 | val = ((data->csc_mv[4] >> matrix_shift) & 0x1FFF) | |
| 52 | (((data->csc_mv[5] >> matrix_shift) & 0x1FFF) << 16); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 53 | SDE_REG_WRITE(c, csc_reg_off + 0x8, val); |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 54 | val = ((data->csc_mv[6] >> matrix_shift) & 0x1FFF) | |
| 55 | (((data->csc_mv[7] >> matrix_shift) & 0x1FFF) << 16); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 56 | SDE_REG_WRITE(c, csc_reg_off + 0xc, val); |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 57 | val = (data->csc_mv[8] >> matrix_shift) & 0x1FFF; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 58 | SDE_REG_WRITE(c, csc_reg_off + 0x10, val); |
| 59 | |
| 60 | /* Pre clamp */ |
| 61 | val = (data->csc_pre_lv[0] << 8) | data->csc_pre_lv[1]; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 62 | SDE_REG_WRITE(c, csc_reg_off + 0x14, val); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 63 | val = (data->csc_pre_lv[2] << 8) | data->csc_pre_lv[3]; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 64 | SDE_REG_WRITE(c, csc_reg_off + 0x18, val); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 65 | val = (data->csc_pre_lv[4] << 8) | data->csc_pre_lv[5]; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 66 | SDE_REG_WRITE(c, csc_reg_off + 0x1c, val); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 67 | |
| 68 | /* Post clamp */ |
| 69 | val = (data->csc_post_lv[0] << 8) | data->csc_post_lv[1]; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 70 | SDE_REG_WRITE(c, csc_reg_off + 0x20, val); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 71 | val = (data->csc_post_lv[2] << 8) | data->csc_post_lv[3]; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 72 | SDE_REG_WRITE(c, csc_reg_off + 0x24, val); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 73 | val = (data->csc_post_lv[4] << 8) | data->csc_post_lv[5]; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 74 | SDE_REG_WRITE(c, csc_reg_off + 0x28, val); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 75 | |
| 76 | /* Pre-Bias */ |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 77 | SDE_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 78 | SDE_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]); |
| 79 | SDE_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]); |
| 80 | |
| 81 | /* Post-Bias */ |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame^] | 82 | SDE_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 83 | SDE_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]); |
| 84 | SDE_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]); |
| 85 | } |
| 86 | |