blob: 5dce13e429f3daae015b7f5e3b1ddbd27650de48 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-shark/irq.c
3 *
4 * by Alexander Schulz
5 *
6 * derived from linux/arch/ppc/kernel/i8259.c and:
Russell Kinga09e64f2008-08-05 16:14:15 +01007 * arch/arm/mach-ebsa110/include/mach/irq.h
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 * Copyright (C) 1996-1998 Russell King
9 */
10
11#include <linux/init.h>
12#include <linux/fs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/interrupt.h>
Russell Kingfced80c2008-09-06 12:10:45 +010014#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16#include <asm/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <asm/mach/irq.h>
18
19/*
20 * 8259A PIC functions to handle ISA devices:
21 */
22
23/*
24 * This contains the irq mask for both 8259A irq controllers,
25 * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb)
26 */
27static unsigned char cached_irq_mask[2] = { 0xfb, 0xff };
28
29/*
30 * These have to be protected by the irq controller spinlock
31 * before being called.
32 */
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010033static void shark_disable_8259A_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070034{
35 unsigned int mask;
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010036 if (d->irq<8) {
37 mask = 1 << d->irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070038 cached_irq_mask[0] |= mask;
39 outb(cached_irq_mask[1],0xA1);
40 } else {
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010041 mask = 1 << (d->irq-8);
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 cached_irq_mask[1] |= mask;
43 outb(cached_irq_mask[0],0x21);
44 }
45}
46
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010047static void shark_enable_8259A_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070048{
49 unsigned int mask;
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010050 if (d->irq<8) {
51 mask = ~(1 << d->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070052 cached_irq_mask[0] &= mask;
53 outb(cached_irq_mask[0],0x21);
54 } else {
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010055 mask = ~(1 << (d->irq-8));
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 cached_irq_mask[1] &= mask;
57 outb(cached_irq_mask[1],0xA1);
58 }
59}
60
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010061static void shark_ack_8259A_irq(struct irq_data *d){}
Linus Torvalds1da177e2005-04-16 15:20:36 -070062
Linus Torvalds0cd61b62006-10-06 10:53:39 -070063static irqreturn_t bogus_int(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -070064{
65 printk("Got interrupt %i!\n",irq);
66 return IRQ_NONE;
67}
68
69static struct irqaction cascade;
70
David Brownell38c677c2006-08-01 22:26:25 +010071static struct irq_chip fb_chip = {
Lennert Buytenhekaab0c632010-11-29 11:12:34 +010072 .name = "XT-PIC",
73 .irq_ack = shark_ack_8259A_irq,
74 .irq_mask = shark_disable_8259A_irq,
75 .irq_unmask = shark_enable_8259A_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070076};
77
78void __init shark_init_irq(void)
79{
80 int irq;
81
82 for (irq = 0; irq < NR_IRQS; irq++) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +010083 irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
85 }
86
87 /* init master interrupt controller */
88 outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/
89 outb(0x00, 0x21); /* Vector base */
90 outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */
91 outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/
92 outb(0x0A, 0x20);
93 /* init slave interrupt controller */
94 outb(0x11, 0xA0); /* Start init sequence, edge triggered */
95 outb(0x08, 0xA1); /* Vector base */
96 outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */
97 outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */
98 outb(0x0A, 0xA0);
99 outb(cached_irq_mask[1],0xA1);
100 outb(cached_irq_mask[0],0x21);
101 //request_region(0x20,0x2,"pic1");
102 //request_region(0xA0,0x2,"pic2");
103
104 cascade.handler = bogus_int;
105 cascade.name = "cascade";
106 setup_irq(2,&cascade);
107}
108