Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | |
| 29 | #include <linux/console.h> |
| 30 | #include <drm/drmP.h> |
| 31 | #include <drm/drm_crtc_helper.h> |
| 32 | #include <drm/radeon_drm.h> |
| 33 | #include <linux/vgaarb.h> |
| 34 | #include <linux/vga_switcheroo.h> |
| 35 | #include "radeon_reg.h" |
| 36 | #include "radeon.h" |
| 37 | #include "radeon_asic.h" |
| 38 | #include "atom.h" |
| 39 | |
| 40 | /* |
| 41 | * Registers accessors functions. |
| 42 | */ |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 43 | /** |
| 44 | * radeon_invalid_rreg - dummy reg read function |
| 45 | * |
| 46 | * @rdev: radeon device pointer |
| 47 | * @reg: offset of register |
| 48 | * |
| 49 | * Dummy register read function. Used for register blocks |
| 50 | * that certain asics don't have (all asics). |
| 51 | * Returns the value in the register. |
| 52 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
| 54 | { |
| 55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
| 56 | BUG_ON(1); |
| 57 | return 0; |
| 58 | } |
| 59 | |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 60 | /** |
| 61 | * radeon_invalid_wreg - dummy reg write function |
| 62 | * |
| 63 | * @rdev: radeon device pointer |
| 64 | * @reg: offset of register |
| 65 | * @v: value to write to the register |
| 66 | * |
| 67 | * Dummy register read function. Used for register blocks |
| 68 | * that certain asics don't have (all asics). |
| 69 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 71 | { |
| 72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
| 73 | reg, v); |
| 74 | BUG_ON(1); |
| 75 | } |
| 76 | |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 77 | /** |
| 78 | * radeon_register_accessor_init - sets up the register accessor callbacks |
| 79 | * |
| 80 | * @rdev: radeon device pointer |
| 81 | * |
| 82 | * Sets up the register accessor callbacks for various register |
| 83 | * apertures. Not all asics have all apertures (all asics). |
| 84 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
| 86 | { |
| 87 | rdev->mc_rreg = &radeon_invalid_rreg; |
| 88 | rdev->mc_wreg = &radeon_invalid_wreg; |
| 89 | rdev->pll_rreg = &radeon_invalid_rreg; |
| 90 | rdev->pll_wreg = &radeon_invalid_wreg; |
| 91 | rdev->pciep_rreg = &radeon_invalid_rreg; |
| 92 | rdev->pciep_wreg = &radeon_invalid_wreg; |
| 93 | |
| 94 | /* Don't change order as we are overridding accessor. */ |
| 95 | if (rdev->family < CHIP_RV515) { |
| 96 | rdev->pcie_reg_mask = 0xff; |
| 97 | } else { |
| 98 | rdev->pcie_reg_mask = 0x7ff; |
| 99 | } |
| 100 | /* FIXME: not sure here */ |
| 101 | if (rdev->family <= CHIP_R580) { |
| 102 | rdev->pll_rreg = &r100_pll_rreg; |
| 103 | rdev->pll_wreg = &r100_pll_wreg; |
| 104 | } |
| 105 | if (rdev->family >= CHIP_R420) { |
| 106 | rdev->mc_rreg = &r420_mc_rreg; |
| 107 | rdev->mc_wreg = &r420_mc_wreg; |
| 108 | } |
| 109 | if (rdev->family >= CHIP_RV515) { |
| 110 | rdev->mc_rreg = &rv515_mc_rreg; |
| 111 | rdev->mc_wreg = &rv515_mc_wreg; |
| 112 | } |
| 113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
| 114 | rdev->mc_rreg = &rs400_mc_rreg; |
| 115 | rdev->mc_wreg = &rs400_mc_wreg; |
| 116 | } |
| 117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| 118 | rdev->mc_rreg = &rs690_mc_rreg; |
| 119 | rdev->mc_wreg = &rs690_mc_wreg; |
| 120 | } |
| 121 | if (rdev->family == CHIP_RS600) { |
| 122 | rdev->mc_rreg = &rs600_mc_rreg; |
| 123 | rdev->mc_wreg = &rs600_mc_wreg; |
| 124 | } |
Alex Deucher | b4df8be | 2011-04-12 13:40:18 -0400 | [diff] [blame] | 125 | if (rdev->family >= CHIP_R600) { |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 126 | rdev->pciep_rreg = &r600_pciep_rreg; |
| 127 | rdev->pciep_wreg = &r600_pciep_wreg; |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | |
| 132 | /* helper to disable agp */ |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 133 | /** |
| 134 | * radeon_agp_disable - AGP disable helper function |
| 135 | * |
| 136 | * @rdev: radeon device pointer |
| 137 | * |
| 138 | * Removes AGP flags and changes the gart callbacks on AGP |
| 139 | * cards when using the internal gart rather than AGP (all asics). |
| 140 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 141 | void radeon_agp_disable(struct radeon_device *rdev) |
| 142 | { |
| 143 | rdev->flags &= ~RADEON_IS_AGP; |
| 144 | if (rdev->family >= CHIP_R600) { |
| 145 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 146 | rdev->flags |= RADEON_IS_PCIE; |
| 147 | } else if (rdev->family >= CHIP_RV515 || |
| 148 | rdev->family == CHIP_RV380 || |
| 149 | rdev->family == CHIP_RV410 || |
| 150 | rdev->family == CHIP_R423) { |
| 151 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
| 152 | rdev->flags |= RADEON_IS_PCIE; |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 153 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
| 154 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 155 | } else { |
| 156 | DRM_INFO("Forcing AGP to PCI mode\n"); |
| 157 | rdev->flags |= RADEON_IS_PCI; |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 158 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
| 159 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 160 | } |
| 161 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * ASIC |
| 166 | */ |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 167 | static struct radeon_asic r100_asic = { |
| 168 | .init = &r100_init, |
| 169 | .fini = &r100_fini, |
| 170 | .suspend = &r100_suspend, |
| 171 | .resume = &r100_resume, |
| 172 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 173 | .asic_reset = &r100_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 174 | .ioctl_wait_idle = NULL, |
| 175 | .gui_idle = &r100_gui_idle, |
| 176 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 177 | .gart = { |
| 178 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 179 | .set_page = &r100_pci_gart_set_page, |
| 180 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 181 | .ring = { |
| 182 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 183 | .ib_execute = &r100_ring_ib_execute, |
| 184 | .emit_fence = &r100_fence_ring_emit, |
| 185 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 186 | .cs_parse = &r100_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 187 | .ring_start = &r100_ring_start, |
| 188 | .ring_test = &r100_ring_test, |
| 189 | .ib_test = &r100_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 190 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 191 | } |
| 192 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 193 | .irq = { |
| 194 | .set = &r100_irq_set, |
| 195 | .process = &r100_irq_process, |
| 196 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 197 | .display = { |
| 198 | .bandwidth_update = &r100_bandwidth_update, |
| 199 | .get_vblank_counter = &r100_get_vblank_counter, |
| 200 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 201 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 202 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 203 | .copy = { |
| 204 | .blit = &r100_copy_blit, |
| 205 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 206 | .dma = NULL, |
| 207 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 208 | .copy = &r100_copy_blit, |
| 209 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 210 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 211 | .surface = { |
| 212 | .set_reg = r100_set_surface_reg, |
| 213 | .clear_reg = r100_clear_surface_reg, |
| 214 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 215 | .hpd = { |
| 216 | .init = &r100_hpd_init, |
| 217 | .fini = &r100_hpd_fini, |
| 218 | .sense = &r100_hpd_sense, |
| 219 | .set_polarity = &r100_hpd_set_polarity, |
| 220 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 221 | .pm = { |
| 222 | .misc = &r100_pm_misc, |
| 223 | .prepare = &r100_pm_prepare, |
| 224 | .finish = &r100_pm_finish, |
| 225 | .init_profile = &r100_pm_init_profile, |
| 226 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 227 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 228 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 229 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 230 | .set_memory_clock = NULL, |
| 231 | .get_pcie_lanes = NULL, |
| 232 | .set_pcie_lanes = NULL, |
| 233 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 234 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 235 | .pflip = { |
| 236 | .pre_page_flip = &r100_pre_page_flip, |
| 237 | .page_flip = &r100_page_flip, |
| 238 | .post_page_flip = &r100_post_page_flip, |
| 239 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 240 | }; |
| 241 | |
| 242 | static struct radeon_asic r200_asic = { |
| 243 | .init = &r100_init, |
| 244 | .fini = &r100_fini, |
| 245 | .suspend = &r100_suspend, |
| 246 | .resume = &r100_resume, |
| 247 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 248 | .asic_reset = &r100_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 249 | .ioctl_wait_idle = NULL, |
| 250 | .gui_idle = &r100_gui_idle, |
| 251 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 252 | .gart = { |
| 253 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 254 | .set_page = &r100_pci_gart_set_page, |
| 255 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 256 | .ring = { |
| 257 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 258 | .ib_execute = &r100_ring_ib_execute, |
| 259 | .emit_fence = &r100_fence_ring_emit, |
| 260 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 261 | .cs_parse = &r100_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 262 | .ring_start = &r100_ring_start, |
| 263 | .ring_test = &r100_ring_test, |
| 264 | .ib_test = &r100_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 265 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 266 | } |
| 267 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 268 | .irq = { |
| 269 | .set = &r100_irq_set, |
| 270 | .process = &r100_irq_process, |
| 271 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 272 | .display = { |
| 273 | .bandwidth_update = &r100_bandwidth_update, |
| 274 | .get_vblank_counter = &r100_get_vblank_counter, |
| 275 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 276 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 277 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 278 | .copy = { |
| 279 | .blit = &r100_copy_blit, |
| 280 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 281 | .dma = &r200_copy_dma, |
| 282 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 283 | .copy = &r100_copy_blit, |
| 284 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 285 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 286 | .surface = { |
| 287 | .set_reg = r100_set_surface_reg, |
| 288 | .clear_reg = r100_clear_surface_reg, |
| 289 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 290 | .hpd = { |
| 291 | .init = &r100_hpd_init, |
| 292 | .fini = &r100_hpd_fini, |
| 293 | .sense = &r100_hpd_sense, |
| 294 | .set_polarity = &r100_hpd_set_polarity, |
| 295 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 296 | .pm = { |
| 297 | .misc = &r100_pm_misc, |
| 298 | .prepare = &r100_pm_prepare, |
| 299 | .finish = &r100_pm_finish, |
| 300 | .init_profile = &r100_pm_init_profile, |
| 301 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 302 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 303 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 304 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 305 | .set_memory_clock = NULL, |
| 306 | .get_pcie_lanes = NULL, |
| 307 | .set_pcie_lanes = NULL, |
| 308 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 309 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 310 | .pflip = { |
| 311 | .pre_page_flip = &r100_pre_page_flip, |
| 312 | .page_flip = &r100_page_flip, |
| 313 | .post_page_flip = &r100_post_page_flip, |
| 314 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 315 | }; |
| 316 | |
| 317 | static struct radeon_asic r300_asic = { |
| 318 | .init = &r300_init, |
| 319 | .fini = &r300_fini, |
| 320 | .suspend = &r300_suspend, |
| 321 | .resume = &r300_resume, |
| 322 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 323 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 324 | .ioctl_wait_idle = NULL, |
| 325 | .gui_idle = &r100_gui_idle, |
| 326 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 327 | .gart = { |
| 328 | .tlb_flush = &r100_pci_gart_tlb_flush, |
| 329 | .set_page = &r100_pci_gart_set_page, |
| 330 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 331 | .ring = { |
| 332 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 333 | .ib_execute = &r100_ring_ib_execute, |
| 334 | .emit_fence = &r300_fence_ring_emit, |
| 335 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 336 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 337 | .ring_start = &r300_ring_start, |
| 338 | .ring_test = &r100_ring_test, |
| 339 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 340 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 341 | } |
| 342 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 343 | .irq = { |
| 344 | .set = &r100_irq_set, |
| 345 | .process = &r100_irq_process, |
| 346 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 347 | .display = { |
| 348 | .bandwidth_update = &r100_bandwidth_update, |
| 349 | .get_vblank_counter = &r100_get_vblank_counter, |
| 350 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 351 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 352 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 353 | .copy = { |
| 354 | .blit = &r100_copy_blit, |
| 355 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 356 | .dma = &r200_copy_dma, |
| 357 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 358 | .copy = &r100_copy_blit, |
| 359 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 360 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 361 | .surface = { |
| 362 | .set_reg = r100_set_surface_reg, |
| 363 | .clear_reg = r100_clear_surface_reg, |
| 364 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 365 | .hpd = { |
| 366 | .init = &r100_hpd_init, |
| 367 | .fini = &r100_hpd_fini, |
| 368 | .sense = &r100_hpd_sense, |
| 369 | .set_polarity = &r100_hpd_set_polarity, |
| 370 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 371 | .pm = { |
| 372 | .misc = &r100_pm_misc, |
| 373 | .prepare = &r100_pm_prepare, |
| 374 | .finish = &r100_pm_finish, |
| 375 | .init_profile = &r100_pm_init_profile, |
| 376 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 377 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 378 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 379 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 380 | .set_memory_clock = NULL, |
| 381 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 382 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 383 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 384 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 385 | .pflip = { |
| 386 | .pre_page_flip = &r100_pre_page_flip, |
| 387 | .page_flip = &r100_page_flip, |
| 388 | .post_page_flip = &r100_post_page_flip, |
| 389 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 390 | }; |
| 391 | |
| 392 | static struct radeon_asic r300_asic_pcie = { |
| 393 | .init = &r300_init, |
| 394 | .fini = &r300_fini, |
| 395 | .suspend = &r300_suspend, |
| 396 | .resume = &r300_resume, |
| 397 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 398 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 399 | .ioctl_wait_idle = NULL, |
| 400 | .gui_idle = &r100_gui_idle, |
| 401 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 402 | .gart = { |
| 403 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 404 | .set_page = &rv370_pcie_gart_set_page, |
| 405 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 406 | .ring = { |
| 407 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 408 | .ib_execute = &r100_ring_ib_execute, |
| 409 | .emit_fence = &r300_fence_ring_emit, |
| 410 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 411 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 412 | .ring_start = &r300_ring_start, |
| 413 | .ring_test = &r100_ring_test, |
| 414 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 415 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 416 | } |
| 417 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 418 | .irq = { |
| 419 | .set = &r100_irq_set, |
| 420 | .process = &r100_irq_process, |
| 421 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 422 | .display = { |
| 423 | .bandwidth_update = &r100_bandwidth_update, |
| 424 | .get_vblank_counter = &r100_get_vblank_counter, |
| 425 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 426 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 427 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 428 | .copy = { |
| 429 | .blit = &r100_copy_blit, |
| 430 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 431 | .dma = &r200_copy_dma, |
| 432 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 433 | .copy = &r100_copy_blit, |
| 434 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 435 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 436 | .surface = { |
| 437 | .set_reg = r100_set_surface_reg, |
| 438 | .clear_reg = r100_clear_surface_reg, |
| 439 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 440 | .hpd = { |
| 441 | .init = &r100_hpd_init, |
| 442 | .fini = &r100_hpd_fini, |
| 443 | .sense = &r100_hpd_sense, |
| 444 | .set_polarity = &r100_hpd_set_polarity, |
| 445 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 446 | .pm = { |
| 447 | .misc = &r100_pm_misc, |
| 448 | .prepare = &r100_pm_prepare, |
| 449 | .finish = &r100_pm_finish, |
| 450 | .init_profile = &r100_pm_init_profile, |
| 451 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 452 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 453 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 454 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 455 | .set_memory_clock = NULL, |
| 456 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 457 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 458 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 459 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 460 | .pflip = { |
| 461 | .pre_page_flip = &r100_pre_page_flip, |
| 462 | .page_flip = &r100_page_flip, |
| 463 | .post_page_flip = &r100_post_page_flip, |
| 464 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 465 | }; |
| 466 | |
| 467 | static struct radeon_asic r420_asic = { |
| 468 | .init = &r420_init, |
| 469 | .fini = &r420_fini, |
| 470 | .suspend = &r420_suspend, |
| 471 | .resume = &r420_resume, |
| 472 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 473 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 474 | .ioctl_wait_idle = NULL, |
| 475 | .gui_idle = &r100_gui_idle, |
| 476 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 477 | .gart = { |
| 478 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 479 | .set_page = &rv370_pcie_gart_set_page, |
| 480 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 481 | .ring = { |
| 482 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 483 | .ib_execute = &r100_ring_ib_execute, |
| 484 | .emit_fence = &r300_fence_ring_emit, |
| 485 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 486 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 487 | .ring_start = &r300_ring_start, |
| 488 | .ring_test = &r100_ring_test, |
| 489 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 490 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 491 | } |
| 492 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 493 | .irq = { |
| 494 | .set = &r100_irq_set, |
| 495 | .process = &r100_irq_process, |
| 496 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 497 | .display = { |
| 498 | .bandwidth_update = &r100_bandwidth_update, |
| 499 | .get_vblank_counter = &r100_get_vblank_counter, |
| 500 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 501 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 502 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 503 | .copy = { |
| 504 | .blit = &r100_copy_blit, |
| 505 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 506 | .dma = &r200_copy_dma, |
| 507 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 508 | .copy = &r100_copy_blit, |
| 509 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 510 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 511 | .surface = { |
| 512 | .set_reg = r100_set_surface_reg, |
| 513 | .clear_reg = r100_clear_surface_reg, |
| 514 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 515 | .hpd = { |
| 516 | .init = &r100_hpd_init, |
| 517 | .fini = &r100_hpd_fini, |
| 518 | .sense = &r100_hpd_sense, |
| 519 | .set_polarity = &r100_hpd_set_polarity, |
| 520 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 521 | .pm = { |
| 522 | .misc = &r100_pm_misc, |
| 523 | .prepare = &r100_pm_prepare, |
| 524 | .finish = &r100_pm_finish, |
| 525 | .init_profile = &r420_pm_init_profile, |
| 526 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 527 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 528 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 529 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 530 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 531 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 532 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 533 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 534 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 535 | .pflip = { |
| 536 | .pre_page_flip = &r100_pre_page_flip, |
| 537 | .page_flip = &r100_page_flip, |
| 538 | .post_page_flip = &r100_post_page_flip, |
| 539 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 540 | }; |
| 541 | |
| 542 | static struct radeon_asic rs400_asic = { |
| 543 | .init = &rs400_init, |
| 544 | .fini = &rs400_fini, |
| 545 | .suspend = &rs400_suspend, |
| 546 | .resume = &rs400_resume, |
| 547 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 548 | .asic_reset = &r300_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 549 | .ioctl_wait_idle = NULL, |
| 550 | .gui_idle = &r100_gui_idle, |
| 551 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 552 | .gart = { |
| 553 | .tlb_flush = &rs400_gart_tlb_flush, |
| 554 | .set_page = &rs400_gart_set_page, |
| 555 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 556 | .ring = { |
| 557 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 558 | .ib_execute = &r100_ring_ib_execute, |
| 559 | .emit_fence = &r300_fence_ring_emit, |
| 560 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 561 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 562 | .ring_start = &r300_ring_start, |
| 563 | .ring_test = &r100_ring_test, |
| 564 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 565 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 566 | } |
| 567 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 568 | .irq = { |
| 569 | .set = &r100_irq_set, |
| 570 | .process = &r100_irq_process, |
| 571 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 572 | .display = { |
| 573 | .bandwidth_update = &r100_bandwidth_update, |
| 574 | .get_vblank_counter = &r100_get_vblank_counter, |
| 575 | .wait_for_vblank = &r100_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 576 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 577 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 578 | .copy = { |
| 579 | .blit = &r100_copy_blit, |
| 580 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 581 | .dma = &r200_copy_dma, |
| 582 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 583 | .copy = &r100_copy_blit, |
| 584 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 585 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 586 | .surface = { |
| 587 | .set_reg = r100_set_surface_reg, |
| 588 | .clear_reg = r100_clear_surface_reg, |
| 589 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 590 | .hpd = { |
| 591 | .init = &r100_hpd_init, |
| 592 | .fini = &r100_hpd_fini, |
| 593 | .sense = &r100_hpd_sense, |
| 594 | .set_polarity = &r100_hpd_set_polarity, |
| 595 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 596 | .pm = { |
| 597 | .misc = &r100_pm_misc, |
| 598 | .prepare = &r100_pm_prepare, |
| 599 | .finish = &r100_pm_finish, |
| 600 | .init_profile = &r100_pm_init_profile, |
| 601 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 602 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 603 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
| 604 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 605 | .set_memory_clock = NULL, |
| 606 | .get_pcie_lanes = NULL, |
| 607 | .set_pcie_lanes = NULL, |
| 608 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 609 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 610 | .pflip = { |
| 611 | .pre_page_flip = &r100_pre_page_flip, |
| 612 | .page_flip = &r100_page_flip, |
| 613 | .post_page_flip = &r100_post_page_flip, |
| 614 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 615 | }; |
| 616 | |
| 617 | static struct radeon_asic rs600_asic = { |
| 618 | .init = &rs600_init, |
| 619 | .fini = &rs600_fini, |
| 620 | .suspend = &rs600_suspend, |
| 621 | .resume = &rs600_resume, |
| 622 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 623 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 624 | .ioctl_wait_idle = NULL, |
| 625 | .gui_idle = &r100_gui_idle, |
| 626 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 627 | .gart = { |
| 628 | .tlb_flush = &rs600_gart_tlb_flush, |
| 629 | .set_page = &rs600_gart_set_page, |
| 630 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 631 | .ring = { |
| 632 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 633 | .ib_execute = &r100_ring_ib_execute, |
| 634 | .emit_fence = &r300_fence_ring_emit, |
| 635 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 636 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 637 | .ring_start = &r300_ring_start, |
| 638 | .ring_test = &r100_ring_test, |
| 639 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 640 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 641 | } |
| 642 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 643 | .irq = { |
| 644 | .set = &rs600_irq_set, |
| 645 | .process = &rs600_irq_process, |
| 646 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 647 | .display = { |
| 648 | .bandwidth_update = &rs600_bandwidth_update, |
| 649 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 650 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 651 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 652 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 653 | .copy = { |
| 654 | .blit = &r100_copy_blit, |
| 655 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 656 | .dma = &r200_copy_dma, |
| 657 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 658 | .copy = &r100_copy_blit, |
| 659 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 660 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 661 | .surface = { |
| 662 | .set_reg = r100_set_surface_reg, |
| 663 | .clear_reg = r100_clear_surface_reg, |
| 664 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 665 | .hpd = { |
| 666 | .init = &rs600_hpd_init, |
| 667 | .fini = &rs600_hpd_fini, |
| 668 | .sense = &rs600_hpd_sense, |
| 669 | .set_polarity = &rs600_hpd_set_polarity, |
| 670 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 671 | .pm = { |
| 672 | .misc = &rs600_pm_misc, |
| 673 | .prepare = &rs600_pm_prepare, |
| 674 | .finish = &rs600_pm_finish, |
| 675 | .init_profile = &r420_pm_init_profile, |
| 676 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 677 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 678 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 679 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 680 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 681 | .get_pcie_lanes = NULL, |
| 682 | .set_pcie_lanes = NULL, |
| 683 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 684 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 685 | .pflip = { |
| 686 | .pre_page_flip = &rs600_pre_page_flip, |
| 687 | .page_flip = &rs600_page_flip, |
| 688 | .post_page_flip = &rs600_post_page_flip, |
| 689 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 690 | }; |
| 691 | |
| 692 | static struct radeon_asic rs690_asic = { |
| 693 | .init = &rs690_init, |
| 694 | .fini = &rs690_fini, |
| 695 | .suspend = &rs690_suspend, |
| 696 | .resume = &rs690_resume, |
| 697 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 698 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 699 | .ioctl_wait_idle = NULL, |
| 700 | .gui_idle = &r100_gui_idle, |
| 701 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 702 | .gart = { |
| 703 | .tlb_flush = &rs400_gart_tlb_flush, |
| 704 | .set_page = &rs400_gart_set_page, |
| 705 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 706 | .ring = { |
| 707 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 708 | .ib_execute = &r100_ring_ib_execute, |
| 709 | .emit_fence = &r300_fence_ring_emit, |
| 710 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 711 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 712 | .ring_start = &r300_ring_start, |
| 713 | .ring_test = &r100_ring_test, |
| 714 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 715 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 716 | } |
| 717 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 718 | .irq = { |
| 719 | .set = &rs600_irq_set, |
| 720 | .process = &rs600_irq_process, |
| 721 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 722 | .display = { |
| 723 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 724 | .bandwidth_update = &rs690_bandwidth_update, |
| 725 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 726 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 727 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 728 | .copy = { |
| 729 | .blit = &r100_copy_blit, |
| 730 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 731 | .dma = &r200_copy_dma, |
| 732 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 733 | .copy = &r200_copy_dma, |
| 734 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 735 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 736 | .surface = { |
| 737 | .set_reg = r100_set_surface_reg, |
| 738 | .clear_reg = r100_clear_surface_reg, |
| 739 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 740 | .hpd = { |
| 741 | .init = &rs600_hpd_init, |
| 742 | .fini = &rs600_hpd_fini, |
| 743 | .sense = &rs600_hpd_sense, |
| 744 | .set_polarity = &rs600_hpd_set_polarity, |
| 745 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 746 | .pm = { |
| 747 | .misc = &rs600_pm_misc, |
| 748 | .prepare = &rs600_pm_prepare, |
| 749 | .finish = &rs600_pm_finish, |
| 750 | .init_profile = &r420_pm_init_profile, |
| 751 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 752 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 753 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 754 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 755 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 756 | .get_pcie_lanes = NULL, |
| 757 | .set_pcie_lanes = NULL, |
| 758 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 759 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 760 | .pflip = { |
| 761 | .pre_page_flip = &rs600_pre_page_flip, |
| 762 | .page_flip = &rs600_page_flip, |
| 763 | .post_page_flip = &rs600_post_page_flip, |
| 764 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 765 | }; |
| 766 | |
| 767 | static struct radeon_asic rv515_asic = { |
| 768 | .init = &rv515_init, |
| 769 | .fini = &rv515_fini, |
| 770 | .suspend = &rv515_suspend, |
| 771 | .resume = &rv515_resume, |
| 772 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 773 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 774 | .ioctl_wait_idle = NULL, |
| 775 | .gui_idle = &r100_gui_idle, |
| 776 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 777 | .gart = { |
| 778 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 779 | .set_page = &rv370_pcie_gart_set_page, |
| 780 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 781 | .ring = { |
| 782 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 783 | .ib_execute = &r100_ring_ib_execute, |
| 784 | .emit_fence = &r300_fence_ring_emit, |
| 785 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 786 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 787 | .ring_start = &rv515_ring_start, |
| 788 | .ring_test = &r100_ring_test, |
| 789 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 790 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 791 | } |
| 792 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 793 | .irq = { |
| 794 | .set = &rs600_irq_set, |
| 795 | .process = &rs600_irq_process, |
| 796 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 797 | .display = { |
| 798 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 799 | .bandwidth_update = &rv515_bandwidth_update, |
| 800 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 801 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 802 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 803 | .copy = { |
| 804 | .blit = &r100_copy_blit, |
| 805 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 806 | .dma = &r200_copy_dma, |
| 807 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 808 | .copy = &r100_copy_blit, |
| 809 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 810 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 811 | .surface = { |
| 812 | .set_reg = r100_set_surface_reg, |
| 813 | .clear_reg = r100_clear_surface_reg, |
| 814 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 815 | .hpd = { |
| 816 | .init = &rs600_hpd_init, |
| 817 | .fini = &rs600_hpd_fini, |
| 818 | .sense = &rs600_hpd_sense, |
| 819 | .set_polarity = &rs600_hpd_set_polarity, |
| 820 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 821 | .pm = { |
| 822 | .misc = &rs600_pm_misc, |
| 823 | .prepare = &rs600_pm_prepare, |
| 824 | .finish = &rs600_pm_finish, |
| 825 | .init_profile = &r420_pm_init_profile, |
| 826 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 827 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 828 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 829 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 830 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 831 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 832 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 833 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 834 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 835 | .pflip = { |
| 836 | .pre_page_flip = &rs600_pre_page_flip, |
| 837 | .page_flip = &rs600_page_flip, |
| 838 | .post_page_flip = &rs600_post_page_flip, |
| 839 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 840 | }; |
| 841 | |
| 842 | static struct radeon_asic r520_asic = { |
| 843 | .init = &r520_init, |
| 844 | .fini = &rv515_fini, |
| 845 | .suspend = &rv515_suspend, |
| 846 | .resume = &r520_resume, |
| 847 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 848 | .asic_reset = &rs600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 849 | .ioctl_wait_idle = NULL, |
| 850 | .gui_idle = &r100_gui_idle, |
| 851 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 852 | .gart = { |
| 853 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 854 | .set_page = &rv370_pcie_gart_set_page, |
| 855 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 856 | .ring = { |
| 857 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 858 | .ib_execute = &r100_ring_ib_execute, |
| 859 | .emit_fence = &r300_fence_ring_emit, |
| 860 | .emit_semaphore = &r100_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 861 | .cs_parse = &r300_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 862 | .ring_start = &rv515_ring_start, |
| 863 | .ring_test = &r100_ring_test, |
| 864 | .ib_test = &r100_ib_test, |
Christian König | 8ba957b | 2012-05-02 15:11:24 +0200 | [diff] [blame] | 865 | .is_lockup = &r100_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 866 | } |
| 867 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 868 | .irq = { |
| 869 | .set = &rs600_irq_set, |
| 870 | .process = &rs600_irq_process, |
| 871 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 872 | .display = { |
| 873 | .bandwidth_update = &rv515_bandwidth_update, |
| 874 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 875 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 876 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 877 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 878 | .copy = { |
| 879 | .blit = &r100_copy_blit, |
| 880 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 881 | .dma = &r200_copy_dma, |
| 882 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 883 | .copy = &r100_copy_blit, |
| 884 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 885 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 886 | .surface = { |
| 887 | .set_reg = r100_set_surface_reg, |
| 888 | .clear_reg = r100_clear_surface_reg, |
| 889 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 890 | .hpd = { |
| 891 | .init = &rs600_hpd_init, |
| 892 | .fini = &rs600_hpd_fini, |
| 893 | .sense = &rs600_hpd_sense, |
| 894 | .set_polarity = &rs600_hpd_set_polarity, |
| 895 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 896 | .pm = { |
| 897 | .misc = &rs600_pm_misc, |
| 898 | .prepare = &rs600_pm_prepare, |
| 899 | .finish = &rs600_pm_finish, |
| 900 | .init_profile = &r420_pm_init_profile, |
| 901 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 902 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 903 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 904 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 905 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 906 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
| 907 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 908 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 909 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 910 | .pflip = { |
| 911 | .pre_page_flip = &rs600_pre_page_flip, |
| 912 | .page_flip = &rs600_page_flip, |
| 913 | .post_page_flip = &rs600_post_page_flip, |
| 914 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 915 | }; |
| 916 | |
| 917 | static struct radeon_asic r600_asic = { |
| 918 | .init = &r600_init, |
| 919 | .fini = &r600_fini, |
| 920 | .suspend = &r600_suspend, |
| 921 | .resume = &r600_resume, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 922 | .vga_set_state = &r600_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 923 | .asic_reset = &r600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 924 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 925 | .gui_idle = &r600_gui_idle, |
| 926 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 927 | .gart = { |
| 928 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 929 | .set_page = &rs600_gart_set_page, |
| 930 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 931 | .ring = { |
| 932 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 933 | .ib_execute = &r600_ring_ib_execute, |
| 934 | .emit_fence = &r600_fence_ring_emit, |
| 935 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 936 | .cs_parse = &r600_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 937 | .ring_test = &r600_ring_test, |
| 938 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 939 | .is_lockup = &r600_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 940 | } |
| 941 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 942 | .irq = { |
| 943 | .set = &r600_irq_set, |
| 944 | .process = &r600_irq_process, |
| 945 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 946 | .display = { |
| 947 | .bandwidth_update = &rv515_bandwidth_update, |
| 948 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 949 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 950 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 951 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 952 | .copy = { |
| 953 | .blit = &r600_copy_blit, |
| 954 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 955 | .dma = NULL, |
| 956 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 957 | .copy = &r600_copy_blit, |
| 958 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 959 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 960 | .surface = { |
| 961 | .set_reg = r600_set_surface_reg, |
| 962 | .clear_reg = r600_clear_surface_reg, |
| 963 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 964 | .hpd = { |
| 965 | .init = &r600_hpd_init, |
| 966 | .fini = &r600_hpd_fini, |
| 967 | .sense = &r600_hpd_sense, |
| 968 | .set_polarity = &r600_hpd_set_polarity, |
| 969 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 970 | .pm = { |
| 971 | .misc = &r600_pm_misc, |
| 972 | .prepare = &rs600_pm_prepare, |
| 973 | .finish = &rs600_pm_finish, |
| 974 | .init_profile = &r600_pm_init_profile, |
| 975 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 976 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 977 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 978 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 979 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 980 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 981 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 982 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 983 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 984 | .pflip = { |
| 985 | .pre_page_flip = &rs600_pre_page_flip, |
| 986 | .page_flip = &rs600_page_flip, |
| 987 | .post_page_flip = &rs600_post_page_flip, |
| 988 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 989 | }; |
| 990 | |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 991 | static struct radeon_asic rs780_asic = { |
| 992 | .init = &r600_init, |
| 993 | .fini = &r600_fini, |
| 994 | .suspend = &r600_suspend, |
| 995 | .resume = &r600_resume, |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 996 | .vga_set_state = &r600_vga_set_state, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 997 | .asic_reset = &r600_asic_reset, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 998 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 999 | .gui_idle = &r600_gui_idle, |
| 1000 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1001 | .gart = { |
| 1002 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 1003 | .set_page = &rs600_gart_set_page, |
| 1004 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1005 | .ring = { |
| 1006 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1007 | .ib_execute = &r600_ring_ib_execute, |
| 1008 | .emit_fence = &r600_fence_ring_emit, |
| 1009 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1010 | .cs_parse = &r600_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1011 | .ring_test = &r600_ring_test, |
| 1012 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1013 | .is_lockup = &r600_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1014 | } |
| 1015 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1016 | .irq = { |
| 1017 | .set = &r600_irq_set, |
| 1018 | .process = &r600_irq_process, |
| 1019 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1020 | .display = { |
| 1021 | .bandwidth_update = &rs690_bandwidth_update, |
| 1022 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 1023 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1024 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1025 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1026 | .copy = { |
| 1027 | .blit = &r600_copy_blit, |
| 1028 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1029 | .dma = NULL, |
| 1030 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1031 | .copy = &r600_copy_blit, |
| 1032 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1033 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1034 | .surface = { |
| 1035 | .set_reg = r600_set_surface_reg, |
| 1036 | .clear_reg = r600_clear_surface_reg, |
| 1037 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1038 | .hpd = { |
| 1039 | .init = &r600_hpd_init, |
| 1040 | .fini = &r600_hpd_fini, |
| 1041 | .sense = &r600_hpd_sense, |
| 1042 | .set_polarity = &r600_hpd_set_polarity, |
| 1043 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1044 | .pm = { |
| 1045 | .misc = &r600_pm_misc, |
| 1046 | .prepare = &rs600_pm_prepare, |
| 1047 | .finish = &rs600_pm_finish, |
| 1048 | .init_profile = &rs780_pm_init_profile, |
| 1049 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1050 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1051 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1052 | .get_memory_clock = NULL, |
| 1053 | .set_memory_clock = NULL, |
| 1054 | .get_pcie_lanes = NULL, |
| 1055 | .set_pcie_lanes = NULL, |
| 1056 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1057 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1058 | .pflip = { |
| 1059 | .pre_page_flip = &rs600_pre_page_flip, |
| 1060 | .page_flip = &rs600_page_flip, |
| 1061 | .post_page_flip = &rs600_post_page_flip, |
| 1062 | }, |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1063 | }; |
| 1064 | |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1065 | static struct radeon_asic rv770_asic = { |
| 1066 | .init = &rv770_init, |
| 1067 | .fini = &rv770_fini, |
| 1068 | .suspend = &rv770_suspend, |
| 1069 | .resume = &rv770_resume, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1070 | .asic_reset = &r600_asic_reset, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1071 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1072 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1073 | .gui_idle = &r600_gui_idle, |
| 1074 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1075 | .gart = { |
| 1076 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
| 1077 | .set_page = &rs600_gart_set_page, |
| 1078 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1079 | .ring = { |
| 1080 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1081 | .ib_execute = &r600_ring_ib_execute, |
| 1082 | .emit_fence = &r600_fence_ring_emit, |
| 1083 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1084 | .cs_parse = &r600_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1085 | .ring_test = &r600_ring_test, |
| 1086 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1087 | .is_lockup = &r600_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1088 | } |
| 1089 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1090 | .irq = { |
| 1091 | .set = &r600_irq_set, |
| 1092 | .process = &r600_irq_process, |
| 1093 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1094 | .display = { |
| 1095 | .bandwidth_update = &rv515_bandwidth_update, |
| 1096 | .get_vblank_counter = &rs600_get_vblank_counter, |
| 1097 | .wait_for_vblank = &avivo_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1098 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1099 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1100 | .copy = { |
| 1101 | .blit = &r600_copy_blit, |
| 1102 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1103 | .dma = NULL, |
| 1104 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1105 | .copy = &r600_copy_blit, |
| 1106 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1107 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1108 | .surface = { |
| 1109 | .set_reg = r600_set_surface_reg, |
| 1110 | .clear_reg = r600_clear_surface_reg, |
| 1111 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1112 | .hpd = { |
| 1113 | .init = &r600_hpd_init, |
| 1114 | .fini = &r600_hpd_fini, |
| 1115 | .sense = &r600_hpd_sense, |
| 1116 | .set_polarity = &r600_hpd_set_polarity, |
| 1117 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1118 | .pm = { |
| 1119 | .misc = &rv770_pm_misc, |
| 1120 | .prepare = &rs600_pm_prepare, |
| 1121 | .finish = &rs600_pm_finish, |
| 1122 | .init_profile = &r600_pm_init_profile, |
| 1123 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1124 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1125 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1126 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1127 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1128 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 1129 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 1130 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1131 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1132 | .pflip = { |
| 1133 | .pre_page_flip = &rs600_pre_page_flip, |
| 1134 | .page_flip = &rv770_page_flip, |
| 1135 | .post_page_flip = &rs600_post_page_flip, |
| 1136 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1137 | }; |
| 1138 | |
| 1139 | static struct radeon_asic evergreen_asic = { |
| 1140 | .init = &evergreen_init, |
| 1141 | .fini = &evergreen_fini, |
| 1142 | .suspend = &evergreen_suspend, |
| 1143 | .resume = &evergreen_resume, |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1144 | .asic_reset = &evergreen_asic_reset, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1145 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1146 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1147 | .gui_idle = &r600_gui_idle, |
| 1148 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1149 | .gart = { |
| 1150 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1151 | .set_page = &rs600_gart_set_page, |
| 1152 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1153 | .ring = { |
| 1154 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1155 | .ib_execute = &evergreen_ring_ib_execute, |
| 1156 | .emit_fence = &r600_fence_ring_emit, |
| 1157 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1158 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1159 | .ring_test = &r600_ring_test, |
| 1160 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1161 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1162 | } |
| 1163 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1164 | .irq = { |
| 1165 | .set = &evergreen_irq_set, |
| 1166 | .process = &evergreen_irq_process, |
| 1167 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1168 | .display = { |
| 1169 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1170 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1171 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1172 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1173 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1174 | .copy = { |
| 1175 | .blit = &r600_copy_blit, |
| 1176 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1177 | .dma = NULL, |
| 1178 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1179 | .copy = &r600_copy_blit, |
| 1180 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1181 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1182 | .surface = { |
| 1183 | .set_reg = r600_set_surface_reg, |
| 1184 | .clear_reg = r600_clear_surface_reg, |
| 1185 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1186 | .hpd = { |
| 1187 | .init = &evergreen_hpd_init, |
| 1188 | .fini = &evergreen_hpd_fini, |
| 1189 | .sense = &evergreen_hpd_sense, |
| 1190 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1191 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1192 | .pm = { |
| 1193 | .misc = &evergreen_pm_misc, |
| 1194 | .prepare = &evergreen_pm_prepare, |
| 1195 | .finish = &evergreen_pm_finish, |
| 1196 | .init_profile = &r600_pm_init_profile, |
| 1197 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1198 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1199 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1200 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1201 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1202 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 1203 | .set_pcie_lanes = &r600_set_pcie_lanes, |
| 1204 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1205 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1206 | .pflip = { |
| 1207 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1208 | .page_flip = &evergreen_page_flip, |
| 1209 | .post_page_flip = &evergreen_post_page_flip, |
| 1210 | }, |
Daniel Vetter | 48e7a5f | 2010-03-11 21:19:15 +0000 | [diff] [blame] | 1211 | }; |
| 1212 | |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1213 | static struct radeon_asic sumo_asic = { |
| 1214 | .init = &evergreen_init, |
| 1215 | .fini = &evergreen_fini, |
| 1216 | .suspend = &evergreen_suspend, |
| 1217 | .resume = &evergreen_resume, |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1218 | .asic_reset = &evergreen_asic_reset, |
| 1219 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1220 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1221 | .gui_idle = &r600_gui_idle, |
| 1222 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1223 | .gart = { |
| 1224 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1225 | .set_page = &rs600_gart_set_page, |
| 1226 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1227 | .ring = { |
| 1228 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1229 | .ib_execute = &evergreen_ring_ib_execute, |
| 1230 | .emit_fence = &r600_fence_ring_emit, |
| 1231 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1232 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1233 | .ring_test = &r600_ring_test, |
| 1234 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1235 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1236 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1237 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1238 | .irq = { |
| 1239 | .set = &evergreen_irq_set, |
| 1240 | .process = &evergreen_irq_process, |
| 1241 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1242 | .display = { |
| 1243 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1244 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1245 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1246 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1247 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1248 | .copy = { |
| 1249 | .blit = &r600_copy_blit, |
| 1250 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1251 | .dma = NULL, |
| 1252 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1253 | .copy = &r600_copy_blit, |
| 1254 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1255 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1256 | .surface = { |
| 1257 | .set_reg = r600_set_surface_reg, |
| 1258 | .clear_reg = r600_clear_surface_reg, |
| 1259 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1260 | .hpd = { |
| 1261 | .init = &evergreen_hpd_init, |
| 1262 | .fini = &evergreen_hpd_fini, |
| 1263 | .sense = &evergreen_hpd_sense, |
| 1264 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1265 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1266 | .pm = { |
| 1267 | .misc = &evergreen_pm_misc, |
| 1268 | .prepare = &evergreen_pm_prepare, |
| 1269 | .finish = &evergreen_pm_finish, |
| 1270 | .init_profile = &sumo_pm_init_profile, |
| 1271 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1272 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1273 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1274 | .get_memory_clock = NULL, |
| 1275 | .set_memory_clock = NULL, |
| 1276 | .get_pcie_lanes = NULL, |
| 1277 | .set_pcie_lanes = NULL, |
| 1278 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1279 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1280 | .pflip = { |
| 1281 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1282 | .page_flip = &evergreen_page_flip, |
| 1283 | .post_page_flip = &evergreen_post_page_flip, |
| 1284 | }, |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1285 | }; |
| 1286 | |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1287 | static struct radeon_asic btc_asic = { |
| 1288 | .init = &evergreen_init, |
| 1289 | .fini = &evergreen_fini, |
| 1290 | .suspend = &evergreen_suspend, |
| 1291 | .resume = &evergreen_resume, |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1292 | .asic_reset = &evergreen_asic_reset, |
| 1293 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1294 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1295 | .gui_idle = &r600_gui_idle, |
| 1296 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1297 | .gart = { |
| 1298 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1299 | .set_page = &rs600_gart_set_page, |
| 1300 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1301 | .ring = { |
| 1302 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1303 | .ib_execute = &evergreen_ring_ib_execute, |
| 1304 | .emit_fence = &r600_fence_ring_emit, |
| 1305 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1306 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1307 | .ring_test = &r600_ring_test, |
| 1308 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1309 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1310 | } |
| 1311 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1312 | .irq = { |
| 1313 | .set = &evergreen_irq_set, |
| 1314 | .process = &evergreen_irq_process, |
| 1315 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1316 | .display = { |
| 1317 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1318 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1319 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1320 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1321 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1322 | .copy = { |
| 1323 | .blit = &r600_copy_blit, |
| 1324 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1325 | .dma = NULL, |
| 1326 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1327 | .copy = &r600_copy_blit, |
| 1328 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1329 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1330 | .surface = { |
| 1331 | .set_reg = r600_set_surface_reg, |
| 1332 | .clear_reg = r600_clear_surface_reg, |
| 1333 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1334 | .hpd = { |
| 1335 | .init = &evergreen_hpd_init, |
| 1336 | .fini = &evergreen_hpd_fini, |
| 1337 | .sense = &evergreen_hpd_sense, |
| 1338 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1339 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1340 | .pm = { |
| 1341 | .misc = &evergreen_pm_misc, |
| 1342 | .prepare = &evergreen_pm_prepare, |
| 1343 | .finish = &evergreen_pm_finish, |
| 1344 | .init_profile = &r600_pm_init_profile, |
| 1345 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1346 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1347 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1348 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1349 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1350 | .get_pcie_lanes = NULL, |
| 1351 | .set_pcie_lanes = NULL, |
| 1352 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1353 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1354 | .pflip = { |
| 1355 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1356 | .page_flip = &evergreen_page_flip, |
| 1357 | .post_page_flip = &evergreen_post_page_flip, |
| 1358 | }, |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1359 | }; |
| 1360 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1361 | static const struct radeon_vm_funcs cayman_vm_funcs = { |
| 1362 | .init = &cayman_vm_init, |
| 1363 | .fini = &cayman_vm_fini, |
| 1364 | .bind = &cayman_vm_bind, |
| 1365 | .unbind = &cayman_vm_unbind, |
| 1366 | .tlb_flush = &cayman_vm_tlb_flush, |
| 1367 | .page_flags = &cayman_vm_page_flags, |
| 1368 | .set_page = &cayman_vm_set_page, |
| 1369 | }; |
| 1370 | |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1371 | static struct radeon_asic cayman_asic = { |
| 1372 | .init = &cayman_init, |
| 1373 | .fini = &cayman_fini, |
| 1374 | .suspend = &cayman_suspend, |
| 1375 | .resume = &cayman_resume, |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1376 | .asic_reset = &cayman_asic_reset, |
| 1377 | .vga_set_state = &r600_vga_set_state, |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1378 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1379 | .gui_idle = &r600_gui_idle, |
| 1380 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1381 | .gart = { |
| 1382 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
| 1383 | .set_page = &rs600_gart_set_page, |
| 1384 | }, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1385 | .ring = { |
| 1386 | [RADEON_RING_TYPE_GFX_INDEX] = { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1387 | .ib_execute = &cayman_ring_ib_execute, |
| 1388 | .ib_parse = &evergreen_ib_parse, |
Alex Deucher | b40e7e1 | 2011-11-17 14:57:50 -0500 | [diff] [blame] | 1389 | .emit_fence = &cayman_fence_ring_emit, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1390 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1391 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1392 | .ring_test = &r600_ring_test, |
| 1393 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1394 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1395 | }, |
| 1396 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1397 | .ib_execute = &cayman_ring_ib_execute, |
| 1398 | .ib_parse = &evergreen_ib_parse, |
Alex Deucher | b40e7e1 | 2011-11-17 14:57:50 -0500 | [diff] [blame] | 1399 | .emit_fence = &cayman_fence_ring_emit, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1400 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1401 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1402 | .ring_test = &r600_ring_test, |
| 1403 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1404 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1405 | }, |
| 1406 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1407 | .ib_execute = &cayman_ring_ib_execute, |
| 1408 | .ib_parse = &evergreen_ib_parse, |
Alex Deucher | b40e7e1 | 2011-11-17 14:57:50 -0500 | [diff] [blame] | 1409 | .emit_fence = &cayman_fence_ring_emit, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1410 | .emit_semaphore = &r600_semaphore_ring_emit, |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1411 | .cs_parse = &evergreen_cs_parse, |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1412 | .ring_test = &r600_ring_test, |
| 1413 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1414 | .is_lockup = &evergreen_gpu_is_lockup, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1415 | } |
| 1416 | }, |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1417 | .irq = { |
| 1418 | .set = &evergreen_irq_set, |
| 1419 | .process = &evergreen_irq_process, |
| 1420 | }, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1421 | .display = { |
| 1422 | .bandwidth_update = &evergreen_bandwidth_update, |
| 1423 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1424 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1425 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1426 | }, |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1427 | .copy = { |
| 1428 | .blit = &r600_copy_blit, |
| 1429 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1430 | .dma = NULL, |
| 1431 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1432 | .copy = &r600_copy_blit, |
| 1433 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1434 | }, |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1435 | .surface = { |
| 1436 | .set_reg = r600_set_surface_reg, |
| 1437 | .clear_reg = r600_clear_surface_reg, |
| 1438 | }, |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1439 | .hpd = { |
| 1440 | .init = &evergreen_hpd_init, |
| 1441 | .fini = &evergreen_hpd_fini, |
| 1442 | .sense = &evergreen_hpd_sense, |
| 1443 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1444 | }, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1445 | .pm = { |
| 1446 | .misc = &evergreen_pm_misc, |
| 1447 | .prepare = &evergreen_pm_prepare, |
| 1448 | .finish = &evergreen_pm_finish, |
| 1449 | .init_profile = &r600_pm_init_profile, |
| 1450 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1451 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1452 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1453 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1454 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1455 | .get_pcie_lanes = NULL, |
| 1456 | .set_pcie_lanes = NULL, |
| 1457 | .set_clock_gating = NULL, |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1458 | }, |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1459 | .pflip = { |
| 1460 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1461 | .page_flip = &evergreen_page_flip, |
| 1462 | .post_page_flip = &evergreen_post_page_flip, |
| 1463 | }, |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1464 | }; |
| 1465 | |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1466 | static struct radeon_asic trinity_asic = { |
| 1467 | .init = &cayman_init, |
| 1468 | .fini = &cayman_fini, |
| 1469 | .suspend = &cayman_suspend, |
| 1470 | .resume = &cayman_resume, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1471 | .asic_reset = &cayman_asic_reset, |
| 1472 | .vga_set_state = &r600_vga_set_state, |
| 1473 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1474 | .gui_idle = &r600_gui_idle, |
| 1475 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
| 1476 | .gart = { |
| 1477 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
| 1478 | .set_page = &rs600_gart_set_page, |
| 1479 | }, |
| 1480 | .ring = { |
| 1481 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1482 | .ib_execute = &cayman_ring_ib_execute, |
| 1483 | .ib_parse = &evergreen_ib_parse, |
| 1484 | .emit_fence = &cayman_fence_ring_emit, |
| 1485 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1486 | .cs_parse = &evergreen_cs_parse, |
| 1487 | .ring_test = &r600_ring_test, |
| 1488 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1489 | .is_lockup = &evergreen_gpu_is_lockup, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1490 | }, |
| 1491 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
| 1492 | .ib_execute = &cayman_ring_ib_execute, |
| 1493 | .ib_parse = &evergreen_ib_parse, |
| 1494 | .emit_fence = &cayman_fence_ring_emit, |
| 1495 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1496 | .cs_parse = &evergreen_cs_parse, |
| 1497 | .ring_test = &r600_ring_test, |
| 1498 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1499 | .is_lockup = &evergreen_gpu_is_lockup, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1500 | }, |
| 1501 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
| 1502 | .ib_execute = &cayman_ring_ib_execute, |
| 1503 | .ib_parse = &evergreen_ib_parse, |
| 1504 | .emit_fence = &cayman_fence_ring_emit, |
| 1505 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1506 | .cs_parse = &evergreen_cs_parse, |
| 1507 | .ring_test = &r600_ring_test, |
| 1508 | .ib_test = &r600_ib_test, |
Christian König | abfaa44 | 2012-05-02 15:11:25 +0200 | [diff] [blame] | 1509 | .is_lockup = &evergreen_gpu_is_lockup, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1510 | } |
| 1511 | }, |
| 1512 | .irq = { |
| 1513 | .set = &evergreen_irq_set, |
| 1514 | .process = &evergreen_irq_process, |
| 1515 | }, |
| 1516 | .display = { |
| 1517 | .bandwidth_update = &dce6_bandwidth_update, |
| 1518 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1519 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1520 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1521 | }, |
| 1522 | .copy = { |
| 1523 | .blit = &r600_copy_blit, |
| 1524 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1525 | .dma = NULL, |
| 1526 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1527 | .copy = &r600_copy_blit, |
| 1528 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1529 | }, |
| 1530 | .surface = { |
| 1531 | .set_reg = r600_set_surface_reg, |
| 1532 | .clear_reg = r600_clear_surface_reg, |
| 1533 | }, |
| 1534 | .hpd = { |
| 1535 | .init = &evergreen_hpd_init, |
| 1536 | .fini = &evergreen_hpd_fini, |
| 1537 | .sense = &evergreen_hpd_sense, |
| 1538 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1539 | }, |
| 1540 | .pm = { |
| 1541 | .misc = &evergreen_pm_misc, |
| 1542 | .prepare = &evergreen_pm_prepare, |
| 1543 | .finish = &evergreen_pm_finish, |
| 1544 | .init_profile = &sumo_pm_init_profile, |
| 1545 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1546 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1547 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1548 | .get_memory_clock = NULL, |
| 1549 | .set_memory_clock = NULL, |
| 1550 | .get_pcie_lanes = NULL, |
| 1551 | .set_pcie_lanes = NULL, |
| 1552 | .set_clock_gating = NULL, |
| 1553 | }, |
| 1554 | .pflip = { |
| 1555 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1556 | .page_flip = &evergreen_page_flip, |
| 1557 | .post_page_flip = &evergreen_post_page_flip, |
| 1558 | }, |
| 1559 | }; |
| 1560 | |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1561 | static const struct radeon_vm_funcs si_vm_funcs = { |
| 1562 | .init = &si_vm_init, |
| 1563 | .fini = &si_vm_fini, |
| 1564 | .bind = &si_vm_bind, |
| 1565 | .unbind = &si_vm_unbind, |
| 1566 | .tlb_flush = &si_vm_tlb_flush, |
| 1567 | .page_flags = &cayman_vm_page_flags, |
| 1568 | .set_page = &cayman_vm_set_page, |
| 1569 | }; |
| 1570 | |
| 1571 | static struct radeon_asic si_asic = { |
| 1572 | .init = &si_init, |
| 1573 | .fini = &si_fini, |
| 1574 | .suspend = &si_suspend, |
| 1575 | .resume = &si_resume, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1576 | .asic_reset = &si_asic_reset, |
| 1577 | .vga_set_state = &r600_vga_set_state, |
| 1578 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
| 1579 | .gui_idle = &r600_gui_idle, |
| 1580 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
| 1581 | .gart = { |
| 1582 | .tlb_flush = &si_pcie_gart_tlb_flush, |
| 1583 | .set_page = &rs600_gart_set_page, |
| 1584 | }, |
| 1585 | .ring = { |
| 1586 | [RADEON_RING_TYPE_GFX_INDEX] = { |
| 1587 | .ib_execute = &si_ring_ib_execute, |
| 1588 | .ib_parse = &si_ib_parse, |
| 1589 | .emit_fence = &si_fence_ring_emit, |
| 1590 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1591 | .cs_parse = NULL, |
| 1592 | .ring_test = &r600_ring_test, |
| 1593 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1594 | .is_lockup = &si_gpu_is_lockup, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1595 | }, |
| 1596 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
| 1597 | .ib_execute = &si_ring_ib_execute, |
| 1598 | .ib_parse = &si_ib_parse, |
| 1599 | .emit_fence = &si_fence_ring_emit, |
| 1600 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1601 | .cs_parse = NULL, |
| 1602 | .ring_test = &r600_ring_test, |
| 1603 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1604 | .is_lockup = &si_gpu_is_lockup, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1605 | }, |
| 1606 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
| 1607 | .ib_execute = &si_ring_ib_execute, |
| 1608 | .ib_parse = &si_ib_parse, |
| 1609 | .emit_fence = &si_fence_ring_emit, |
| 1610 | .emit_semaphore = &r600_semaphore_ring_emit, |
| 1611 | .cs_parse = NULL, |
| 1612 | .ring_test = &r600_ring_test, |
| 1613 | .ib_test = &r600_ib_test, |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1614 | .is_lockup = &si_gpu_is_lockup, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1615 | } |
| 1616 | }, |
| 1617 | .irq = { |
| 1618 | .set = &si_irq_set, |
| 1619 | .process = &si_irq_process, |
| 1620 | }, |
| 1621 | .display = { |
| 1622 | .bandwidth_update = &dce6_bandwidth_update, |
| 1623 | .get_vblank_counter = &evergreen_get_vblank_counter, |
| 1624 | .wait_for_vblank = &dce4_wait_for_vblank, |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1625 | .set_backlight_level = &atombios_set_backlight_level, |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1626 | }, |
| 1627 | .copy = { |
| 1628 | .blit = NULL, |
| 1629 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1630 | .dma = NULL, |
| 1631 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1632 | .copy = NULL, |
| 1633 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
| 1634 | }, |
| 1635 | .surface = { |
| 1636 | .set_reg = r600_set_surface_reg, |
| 1637 | .clear_reg = r600_clear_surface_reg, |
| 1638 | }, |
| 1639 | .hpd = { |
| 1640 | .init = &evergreen_hpd_init, |
| 1641 | .fini = &evergreen_hpd_fini, |
| 1642 | .sense = &evergreen_hpd_sense, |
| 1643 | .set_polarity = &evergreen_hpd_set_polarity, |
| 1644 | }, |
| 1645 | .pm = { |
| 1646 | .misc = &evergreen_pm_misc, |
| 1647 | .prepare = &evergreen_pm_prepare, |
| 1648 | .finish = &evergreen_pm_finish, |
| 1649 | .init_profile = &sumo_pm_init_profile, |
| 1650 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
| 1651 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 1652 | .set_engine_clock = &radeon_atom_set_engine_clock, |
| 1653 | .get_memory_clock = &radeon_atom_get_memory_clock, |
| 1654 | .set_memory_clock = &radeon_atom_set_memory_clock, |
| 1655 | .get_pcie_lanes = NULL, |
| 1656 | .set_pcie_lanes = NULL, |
| 1657 | .set_clock_gating = NULL, |
| 1658 | }, |
| 1659 | .pflip = { |
| 1660 | .pre_page_flip = &evergreen_pre_page_flip, |
| 1661 | .page_flip = &evergreen_page_flip, |
| 1662 | .post_page_flip = &evergreen_post_page_flip, |
| 1663 | }, |
| 1664 | }; |
| 1665 | |
Alex Deucher | abf1dc6 | 2012-07-17 14:02:36 -0400 | [diff] [blame] | 1666 | /** |
| 1667 | * radeon_asic_init - register asic specific callbacks |
| 1668 | * |
| 1669 | * @rdev: radeon device pointer |
| 1670 | * |
| 1671 | * Registers the appropriate asic specific callbacks for each |
| 1672 | * chip family. Also sets other asics specific info like the number |
| 1673 | * of crtcs and the register aperture accessors (all asics). |
| 1674 | * Returns 0 for success. |
| 1675 | */ |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1676 | int radeon_asic_init(struct radeon_device *rdev) |
| 1677 | { |
| 1678 | radeon_register_accessor_init(rdev); |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1679 | |
| 1680 | /* set the number of crtcs */ |
| 1681 | if (rdev->flags & RADEON_SINGLE_CRTC) |
| 1682 | rdev->num_crtc = 1; |
| 1683 | else |
| 1684 | rdev->num_crtc = 2; |
| 1685 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1686 | switch (rdev->family) { |
| 1687 | case CHIP_R100: |
| 1688 | case CHIP_RV100: |
| 1689 | case CHIP_RS100: |
| 1690 | case CHIP_RV200: |
| 1691 | case CHIP_RS200: |
| 1692 | rdev->asic = &r100_asic; |
| 1693 | break; |
| 1694 | case CHIP_R200: |
| 1695 | case CHIP_RV250: |
| 1696 | case CHIP_RS300: |
| 1697 | case CHIP_RV280: |
| 1698 | rdev->asic = &r200_asic; |
| 1699 | break; |
| 1700 | case CHIP_R300: |
| 1701 | case CHIP_R350: |
| 1702 | case CHIP_RV350: |
| 1703 | case CHIP_RV380: |
| 1704 | if (rdev->flags & RADEON_IS_PCIE) |
| 1705 | rdev->asic = &r300_asic_pcie; |
| 1706 | else |
| 1707 | rdev->asic = &r300_asic; |
| 1708 | break; |
| 1709 | case CHIP_R420: |
| 1710 | case CHIP_R423: |
| 1711 | case CHIP_RV410: |
| 1712 | rdev->asic = &r420_asic; |
Alex Deucher | 07bb084 | 2010-06-22 21:58:26 -0400 | [diff] [blame] | 1713 | /* handle macs */ |
| 1714 | if (rdev->bios == NULL) { |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1715 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
| 1716 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; |
| 1717 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; |
| 1718 | rdev->asic->pm.set_memory_clock = NULL; |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 1719 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
Alex Deucher | 07bb084 | 2010-06-22 21:58:26 -0400 | [diff] [blame] | 1720 | } |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1721 | break; |
| 1722 | case CHIP_RS400: |
| 1723 | case CHIP_RS480: |
| 1724 | rdev->asic = &rs400_asic; |
| 1725 | break; |
| 1726 | case CHIP_RS600: |
| 1727 | rdev->asic = &rs600_asic; |
| 1728 | break; |
| 1729 | case CHIP_RS690: |
| 1730 | case CHIP_RS740: |
| 1731 | rdev->asic = &rs690_asic; |
| 1732 | break; |
| 1733 | case CHIP_RV515: |
| 1734 | rdev->asic = &rv515_asic; |
| 1735 | break; |
| 1736 | case CHIP_R520: |
| 1737 | case CHIP_RV530: |
| 1738 | case CHIP_RV560: |
| 1739 | case CHIP_RV570: |
| 1740 | case CHIP_R580: |
| 1741 | rdev->asic = &r520_asic; |
| 1742 | break; |
| 1743 | case CHIP_R600: |
| 1744 | case CHIP_RV610: |
| 1745 | case CHIP_RV630: |
| 1746 | case CHIP_RV620: |
| 1747 | case CHIP_RV635: |
| 1748 | case CHIP_RV670: |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1749 | rdev->asic = &r600_asic; |
| 1750 | break; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1751 | case CHIP_RS780: |
| 1752 | case CHIP_RS880: |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1753 | rdev->asic = &rs780_asic; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1754 | break; |
| 1755 | case CHIP_RV770: |
| 1756 | case CHIP_RV730: |
| 1757 | case CHIP_RV710: |
| 1758 | case CHIP_RV740: |
| 1759 | rdev->asic = &rv770_asic; |
| 1760 | break; |
| 1761 | case CHIP_CEDAR: |
| 1762 | case CHIP_REDWOOD: |
| 1763 | case CHIP_JUNIPER: |
| 1764 | case CHIP_CYPRESS: |
| 1765 | case CHIP_HEMLOCK: |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1766 | /* set num crtcs */ |
| 1767 | if (rdev->family == CHIP_CEDAR) |
| 1768 | rdev->num_crtc = 4; |
| 1769 | else |
| 1770 | rdev->num_crtc = 6; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1771 | rdev->asic = &evergreen_asic; |
| 1772 | break; |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1773 | case CHIP_PALM: |
Alex Deucher | 89da5a3 | 2011-05-31 15:42:47 -0400 | [diff] [blame] | 1774 | case CHIP_SUMO: |
| 1775 | case CHIP_SUMO2: |
Alex Deucher | 958261d | 2010-11-22 17:56:30 -0500 | [diff] [blame] | 1776 | rdev->asic = &sumo_asic; |
| 1777 | break; |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1778 | case CHIP_BARTS: |
| 1779 | case CHIP_TURKS: |
| 1780 | case CHIP_CAICOS: |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1781 | /* set num crtcs */ |
| 1782 | if (rdev->family == CHIP_CAICOS) |
| 1783 | rdev->num_crtc = 4; |
| 1784 | else |
| 1785 | rdev->num_crtc = 6; |
Alex Deucher | a43b766 | 2011-01-06 21:19:33 -0500 | [diff] [blame] | 1786 | rdev->asic = &btc_asic; |
| 1787 | break; |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1788 | case CHIP_CAYMAN: |
| 1789 | rdev->asic = &cayman_asic; |
Alex Deucher | ba7e05e | 2011-06-16 18:14:22 +0000 | [diff] [blame] | 1790 | /* set num crtcs */ |
| 1791 | rdev->num_crtc = 6; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1792 | rdev->vm_manager.funcs = &cayman_vm_funcs; |
Alex Deucher | e348762 | 2011-03-02 20:07:36 -0500 | [diff] [blame] | 1793 | break; |
Alex Deucher | be63fe8 | 2012-03-20 17:18:40 -0400 | [diff] [blame] | 1794 | case CHIP_ARUBA: |
| 1795 | rdev->asic = &trinity_asic; |
| 1796 | /* set num crtcs */ |
| 1797 | rdev->num_crtc = 4; |
| 1798 | rdev->vm_manager.funcs = &cayman_vm_funcs; |
| 1799 | break; |
Alex Deucher | 02779c0 | 2012-03-20 17:18:25 -0400 | [diff] [blame] | 1800 | case CHIP_TAHITI: |
| 1801 | case CHIP_PITCAIRN: |
| 1802 | case CHIP_VERDE: |
| 1803 | rdev->asic = &si_asic; |
| 1804 | /* set num crtcs */ |
| 1805 | rdev->num_crtc = 6; |
| 1806 | rdev->vm_manager.funcs = &si_vm_funcs; |
| 1807 | break; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1808 | default: |
| 1809 | /* FIXME: not supported yet */ |
| 1810 | return -EINVAL; |
| 1811 | } |
| 1812 | |
| 1813 | if (rdev->flags & RADEON_IS_IGP) { |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1814 | rdev->asic->pm.get_memory_clock = NULL; |
| 1815 | rdev->asic->pm.set_memory_clock = NULL; |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1816 | } |
| 1817 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1818 | return 0; |
| 1819 | } |
| 1820 | |