Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * wm5100.c -- WM5100 ALSA SoC Audio driver |
| 3 | * |
Mark Brown | 656baae | 2012-05-23 12:39:07 +0100 | [diff] [blame] | 4 | * Copyright 2011-2 Wolfson Microelectronics plc |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 5 | * |
| 6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/moduleparam.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/pm.h> |
| 18 | #include <linux/gcd.h> |
| 19 | #include <linux/gpio.h> |
| 20 | #include <linux/i2c.h> |
Mark Brown | 62c1c40 | 2012-01-26 17:28:49 +0000 | [diff] [blame] | 21 | #include <linux/pm_runtime.h> |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 22 | #include <linux/regulator/consumer.h> |
| 23 | #include <linux/regulator/fixed.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <sound/core.h> |
| 26 | #include <sound/pcm.h> |
| 27 | #include <sound/pcm_params.h> |
| 28 | #include <sound/soc.h> |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 29 | #include <sound/jack.h> |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 30 | #include <sound/initval.h> |
| 31 | #include <sound/tlv.h> |
| 32 | #include <sound/wm5100.h> |
| 33 | |
| 34 | #include "wm5100.h" |
| 35 | |
| 36 | #define WM5100_NUM_CORE_SUPPLIES 2 |
| 37 | static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = { |
| 38 | "DBVDD1", |
| 39 | "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */ |
| 40 | }; |
| 41 | |
| 42 | #define WM5100_AIFS 3 |
| 43 | #define WM5100_SYNC_SRS 3 |
| 44 | |
| 45 | struct wm5100_fll { |
| 46 | int fref; |
| 47 | int fout; |
| 48 | int src; |
| 49 | struct completion lock; |
| 50 | }; |
| 51 | |
| 52 | /* codec private data */ |
| 53 | struct wm5100_priv { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 54 | struct device *dev; |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 55 | struct regmap *regmap; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 56 | struct snd_soc_codec *codec; |
| 57 | |
| 58 | struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES]; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 59 | |
| 60 | int rev; |
| 61 | |
| 62 | int sysclk; |
| 63 | int asyncclk; |
| 64 | |
| 65 | bool aif_async[WM5100_AIFS]; |
| 66 | bool aif_symmetric[WM5100_AIFS]; |
| 67 | int sr_ref[WM5100_SYNC_SRS]; |
| 68 | |
| 69 | bool out_ena[2]; |
| 70 | |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 71 | struct snd_soc_jack *jack; |
| 72 | bool jack_detecting; |
| 73 | bool jack_mic; |
| 74 | int jack_mode; |
Mark Brown | 2633f73 | 2012-01-26 17:43:09 +0000 | [diff] [blame] | 75 | int jack_flips; |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 76 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 77 | struct wm5100_fll fll[2]; |
| 78 | |
| 79 | struct wm5100_pdata pdata; |
| 80 | |
| 81 | #ifdef CONFIG_GPIOLIB |
| 82 | struct gpio_chip gpio_chip; |
| 83 | #endif |
| 84 | }; |
| 85 | |
| 86 | static int wm5100_sr_code[] = { |
| 87 | 0, |
| 88 | 12000, |
| 89 | 24000, |
| 90 | 48000, |
| 91 | 96000, |
| 92 | 192000, |
| 93 | 384000, |
| 94 | 768000, |
| 95 | 0, |
| 96 | 11025, |
| 97 | 22050, |
| 98 | 44100, |
| 99 | 88200, |
| 100 | 176400, |
| 101 | 352800, |
| 102 | 705600, |
| 103 | 4000, |
| 104 | 8000, |
| 105 | 16000, |
| 106 | 32000, |
| 107 | 64000, |
| 108 | 128000, |
| 109 | 256000, |
| 110 | 512000, |
| 111 | }; |
| 112 | |
| 113 | static int wm5100_sr_regs[WM5100_SYNC_SRS] = { |
| 114 | WM5100_CLOCKING_4, |
| 115 | WM5100_CLOCKING_5, |
| 116 | WM5100_CLOCKING_6, |
| 117 | }; |
| 118 | |
| 119 | static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate) |
| 120 | { |
| 121 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 122 | int sr_code, sr_free, i; |
| 123 | |
| 124 | for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++) |
| 125 | if (wm5100_sr_code[i] == rate) |
| 126 | break; |
| 127 | if (i == ARRAY_SIZE(wm5100_sr_code)) { |
| 128 | dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate); |
| 129 | return -EINVAL; |
| 130 | } |
| 131 | sr_code = i; |
| 132 | |
| 133 | if ((wm5100->sysclk % rate) == 0) { |
| 134 | /* Is this rate already in use? */ |
| 135 | sr_free = -1; |
| 136 | for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) { |
| 137 | if (!wm5100->sr_ref[i] && sr_free == -1) { |
| 138 | sr_free = i; |
| 139 | continue; |
| 140 | } |
| 141 | if ((snd_soc_read(codec, wm5100_sr_regs[i]) & |
| 142 | WM5100_SAMPLE_RATE_1_MASK) == sr_code) |
| 143 | break; |
| 144 | } |
| 145 | |
| 146 | if (i < ARRAY_SIZE(wm5100_sr_regs)) { |
| 147 | wm5100->sr_ref[i]++; |
| 148 | dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n", |
| 149 | rate, i, wm5100->sr_ref[i]); |
| 150 | return i; |
| 151 | } |
| 152 | |
| 153 | if (sr_free == -1) { |
| 154 | dev_err(codec->dev, "All SR slots already in use\n"); |
| 155 | return -EBUSY; |
| 156 | } |
| 157 | |
| 158 | dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n", |
| 159 | sr_free, rate); |
| 160 | wm5100->sr_ref[sr_free]++; |
| 161 | snd_soc_update_bits(codec, wm5100_sr_regs[sr_free], |
| 162 | WM5100_SAMPLE_RATE_1_MASK, |
| 163 | sr_code); |
| 164 | |
| 165 | return sr_free; |
| 166 | |
| 167 | } else { |
| 168 | dev_err(codec->dev, |
| 169 | "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n", |
| 170 | rate, wm5100->sysclk, wm5100->asyncclk); |
| 171 | return -EINVAL; |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | static void wm5100_free_sr(struct snd_soc_codec *codec, int rate) |
| 176 | { |
| 177 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 178 | int i, sr_code; |
| 179 | |
| 180 | for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++) |
| 181 | if (wm5100_sr_code[i] == rate) |
| 182 | break; |
| 183 | if (i == ARRAY_SIZE(wm5100_sr_code)) { |
| 184 | dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate); |
| 185 | return; |
| 186 | } |
| 187 | sr_code = wm5100_sr_code[i]; |
| 188 | |
| 189 | for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) { |
| 190 | if (!wm5100->sr_ref[i]) |
| 191 | continue; |
| 192 | |
| 193 | if ((snd_soc_read(codec, wm5100_sr_regs[i]) & |
| 194 | WM5100_SAMPLE_RATE_1_MASK) == sr_code) |
| 195 | break; |
| 196 | } |
| 197 | if (i < ARRAY_SIZE(wm5100_sr_regs)) { |
| 198 | wm5100->sr_ref[i]--; |
| 199 | dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n", |
| 200 | rate, wm5100->sr_ref[i]); |
| 201 | } else { |
| 202 | dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n", |
| 203 | rate); |
| 204 | } |
| 205 | } |
| 206 | |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 207 | static int wm5100_reset(struct wm5100_priv *wm5100) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 208 | { |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 209 | if (wm5100->pdata.reset) { |
| 210 | gpio_set_value_cansleep(wm5100->pdata.reset, 0); |
| 211 | gpio_set_value_cansleep(wm5100->pdata.reset, 1); |
| 212 | |
| 213 | return 0; |
| 214 | } else { |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 215 | return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 216 | } |
| 217 | } |
| 218 | |
| 219 | static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0); |
| 220 | static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); |
| 221 | static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0); |
| 222 | static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0); |
| 223 | static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); |
| 224 | |
| 225 | static const char *wm5100_mixer_texts[] = { |
| 226 | "None", |
| 227 | "Tone Generator 1", |
| 228 | "Tone Generator 2", |
| 229 | "AEC loopback", |
| 230 | "IN1L", |
| 231 | "IN1R", |
| 232 | "IN2L", |
| 233 | "IN2R", |
| 234 | "IN3L", |
| 235 | "IN3R", |
| 236 | "IN4L", |
| 237 | "IN4R", |
| 238 | "AIF1RX1", |
| 239 | "AIF1RX2", |
| 240 | "AIF1RX3", |
| 241 | "AIF1RX4", |
| 242 | "AIF1RX5", |
| 243 | "AIF1RX6", |
| 244 | "AIF1RX7", |
| 245 | "AIF1RX8", |
| 246 | "AIF2RX1", |
| 247 | "AIF2RX2", |
| 248 | "AIF3RX1", |
| 249 | "AIF3RX2", |
| 250 | "EQ1", |
| 251 | "EQ2", |
| 252 | "EQ3", |
| 253 | "EQ4", |
| 254 | "DRC1L", |
| 255 | "DRC1R", |
| 256 | "LHPF1", |
| 257 | "LHPF2", |
| 258 | "LHPF3", |
| 259 | "LHPF4", |
| 260 | "DSP1.1", |
| 261 | "DSP1.2", |
| 262 | "DSP1.3", |
| 263 | "DSP1.4", |
| 264 | "DSP1.5", |
| 265 | "DSP1.6", |
| 266 | "DSP2.1", |
| 267 | "DSP2.2", |
| 268 | "DSP2.3", |
| 269 | "DSP2.4", |
| 270 | "DSP2.5", |
| 271 | "DSP2.6", |
| 272 | "DSP3.1", |
| 273 | "DSP3.2", |
| 274 | "DSP3.3", |
| 275 | "DSP3.4", |
| 276 | "DSP3.5", |
| 277 | "DSP3.6", |
| 278 | "ASRC1L", |
| 279 | "ASRC1R", |
| 280 | "ASRC2L", |
| 281 | "ASRC2R", |
| 282 | "ISRC1INT1", |
| 283 | "ISRC1INT2", |
| 284 | "ISRC1INT3", |
| 285 | "ISRC1INT4", |
| 286 | "ISRC2INT1", |
| 287 | "ISRC2INT2", |
| 288 | "ISRC2INT3", |
| 289 | "ISRC2INT4", |
| 290 | "ISRC1DEC1", |
| 291 | "ISRC1DEC2", |
| 292 | "ISRC1DEC3", |
| 293 | "ISRC1DEC4", |
| 294 | "ISRC2DEC1", |
| 295 | "ISRC2DEC2", |
| 296 | "ISRC2DEC3", |
| 297 | "ISRC2DEC4", |
| 298 | }; |
| 299 | |
| 300 | static int wm5100_mixer_values[] = { |
| 301 | 0x00, |
| 302 | 0x04, /* Tone */ |
| 303 | 0x05, |
| 304 | 0x08, /* AEC */ |
| 305 | 0x10, /* Input */ |
| 306 | 0x11, |
| 307 | 0x12, |
| 308 | 0x13, |
| 309 | 0x14, |
| 310 | 0x15, |
| 311 | 0x16, |
| 312 | 0x17, |
| 313 | 0x20, /* AIF */ |
| 314 | 0x21, |
| 315 | 0x22, |
| 316 | 0x23, |
| 317 | 0x24, |
| 318 | 0x25, |
| 319 | 0x26, |
| 320 | 0x27, |
| 321 | 0x28, |
| 322 | 0x29, |
| 323 | 0x30, /* AIF3 - check */ |
| 324 | 0x31, |
| 325 | 0x50, /* EQ */ |
| 326 | 0x51, |
| 327 | 0x52, |
| 328 | 0x53, |
| 329 | 0x54, |
| 330 | 0x58, /* DRC */ |
| 331 | 0x59, |
| 332 | 0x60, /* LHPF1 */ |
| 333 | 0x61, /* LHPF2 */ |
| 334 | 0x62, /* LHPF3 */ |
| 335 | 0x63, /* LHPF4 */ |
| 336 | 0x68, /* DSP1 */ |
| 337 | 0x69, |
| 338 | 0x6a, |
| 339 | 0x6b, |
| 340 | 0x6c, |
| 341 | 0x6d, |
| 342 | 0x70, /* DSP2 */ |
| 343 | 0x71, |
| 344 | 0x72, |
| 345 | 0x73, |
| 346 | 0x74, |
| 347 | 0x75, |
| 348 | 0x78, /* DSP3 */ |
| 349 | 0x79, |
| 350 | 0x7a, |
| 351 | 0x7b, |
| 352 | 0x7c, |
| 353 | 0x7d, |
| 354 | 0x90, /* ASRC1 */ |
| 355 | 0x91, |
| 356 | 0x92, /* ASRC2 */ |
| 357 | 0x93, |
| 358 | 0xa0, /* ISRC1DEC1 */ |
| 359 | 0xa1, |
| 360 | 0xa2, |
| 361 | 0xa3, |
| 362 | 0xa4, /* ISRC1INT1 */ |
| 363 | 0xa5, |
| 364 | 0xa6, |
| 365 | 0xa7, |
| 366 | 0xa8, /* ISRC2DEC1 */ |
| 367 | 0xa9, |
| 368 | 0xaa, |
| 369 | 0xab, |
| 370 | 0xac, /* ISRC2INT1 */ |
| 371 | 0xad, |
| 372 | 0xae, |
| 373 | 0xaf, |
| 374 | }; |
| 375 | |
| 376 | #define WM5100_MIXER_CONTROLS(name, base) \ |
| 377 | SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \ |
| 378 | WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \ |
| 379 | SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \ |
| 380 | WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \ |
| 381 | SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \ |
| 382 | WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \ |
| 383 | SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \ |
| 384 | WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv) |
| 385 | |
| 386 | #define WM5100_MUX_ENUM_DECL(name, reg) \ |
| 387 | SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \ |
| 388 | wm5100_mixer_texts, wm5100_mixer_values) |
| 389 | |
| 390 | #define WM5100_MUX_CTL_DECL(name) \ |
| 391 | const struct snd_kcontrol_new name##_mux = \ |
| 392 | SOC_DAPM_VALUE_ENUM("Route", name##_enum) |
| 393 | |
| 394 | #define WM5100_MIXER_ENUMS(name, base_reg) \ |
| 395 | static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \ |
| 396 | static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \ |
| 397 | static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \ |
| 398 | static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \ |
| 399 | static WM5100_MUX_CTL_DECL(name##_in1); \ |
| 400 | static WM5100_MUX_CTL_DECL(name##_in2); \ |
| 401 | static WM5100_MUX_CTL_DECL(name##_in3); \ |
| 402 | static WM5100_MUX_CTL_DECL(name##_in4) |
| 403 | |
| 404 | WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE); |
| 405 | WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE); |
| 406 | WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE); |
| 407 | WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE); |
| 408 | WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE); |
| 409 | WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE); |
| 410 | |
| 411 | WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE); |
| 412 | WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE); |
| 413 | WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE); |
| 414 | WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE); |
| 415 | WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE); |
| 416 | WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE); |
| 417 | |
| 418 | WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE); |
| 419 | WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE); |
| 420 | |
| 421 | WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE); |
| 422 | WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE); |
| 423 | WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE); |
| 424 | WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE); |
| 425 | WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE); |
| 426 | WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE); |
| 427 | WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE); |
| 428 | WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE); |
| 429 | |
| 430 | WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE); |
| 431 | WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE); |
| 432 | |
| 433 | WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE); |
| 434 | WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE); |
| 435 | |
| 436 | WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE); |
| 437 | WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE); |
| 438 | WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE); |
| 439 | WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE); |
| 440 | |
| 441 | WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE); |
| 442 | WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE); |
| 443 | |
| 444 | WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE); |
| 445 | WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE); |
| 446 | WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE); |
| 447 | WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE); |
| 448 | |
| 449 | #define WM5100_MUX(name, ctrl) \ |
| 450 | SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) |
| 451 | |
| 452 | #define WM5100_MIXER_WIDGETS(name, name_str) \ |
| 453 | WM5100_MUX(name_str " Input 1", &name##_in1_mux), \ |
| 454 | WM5100_MUX(name_str " Input 2", &name##_in2_mux), \ |
| 455 | WM5100_MUX(name_str " Input 3", &name##_in3_mux), \ |
| 456 | WM5100_MUX(name_str " Input 4", &name##_in4_mux), \ |
| 457 | SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) |
| 458 | |
| 459 | #define WM5100_MIXER_INPUT_ROUTES(name) \ |
| 460 | { name, "Tone Generator 1", "Tone Generator 1" }, \ |
| 461 | { name, "Tone Generator 2", "Tone Generator 2" }, \ |
| 462 | { name, "IN1L", "IN1L PGA" }, \ |
| 463 | { name, "IN1R", "IN1R PGA" }, \ |
| 464 | { name, "IN2L", "IN2L PGA" }, \ |
| 465 | { name, "IN2R", "IN2R PGA" }, \ |
| 466 | { name, "IN3L", "IN3L PGA" }, \ |
| 467 | { name, "IN3R", "IN3R PGA" }, \ |
| 468 | { name, "IN4L", "IN4L PGA" }, \ |
| 469 | { name, "IN4R", "IN4R PGA" }, \ |
| 470 | { name, "AIF1RX1", "AIF1RX1" }, \ |
| 471 | { name, "AIF1RX2", "AIF1RX2" }, \ |
| 472 | { name, "AIF1RX3", "AIF1RX3" }, \ |
| 473 | { name, "AIF1RX4", "AIF1RX4" }, \ |
| 474 | { name, "AIF1RX5", "AIF1RX5" }, \ |
| 475 | { name, "AIF1RX6", "AIF1RX6" }, \ |
| 476 | { name, "AIF1RX7", "AIF1RX7" }, \ |
| 477 | { name, "AIF1RX8", "AIF1RX8" }, \ |
| 478 | { name, "AIF2RX1", "AIF2RX1" }, \ |
| 479 | { name, "AIF2RX2", "AIF2RX2" }, \ |
| 480 | { name, "AIF3RX1", "AIF3RX1" }, \ |
| 481 | { name, "AIF3RX2", "AIF3RX2" }, \ |
| 482 | { name, "EQ1", "EQ1" }, \ |
| 483 | { name, "EQ2", "EQ2" }, \ |
| 484 | { name, "EQ3", "EQ3" }, \ |
| 485 | { name, "EQ4", "EQ4" }, \ |
| 486 | { name, "DRC1L", "DRC1L" }, \ |
| 487 | { name, "DRC1R", "DRC1R" }, \ |
| 488 | { name, "LHPF1", "LHPF1" }, \ |
| 489 | { name, "LHPF2", "LHPF2" }, \ |
| 490 | { name, "LHPF3", "LHPF3" }, \ |
| 491 | { name, "LHPF4", "LHPF4" } |
| 492 | |
| 493 | #define WM5100_MIXER_ROUTES(widget, name) \ |
| 494 | { widget, NULL, name " Mixer" }, \ |
| 495 | { name " Mixer", NULL, name " Input 1" }, \ |
| 496 | { name " Mixer", NULL, name " Input 2" }, \ |
| 497 | { name " Mixer", NULL, name " Input 3" }, \ |
| 498 | { name " Mixer", NULL, name " Input 4" }, \ |
| 499 | WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \ |
| 500 | WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \ |
| 501 | WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \ |
| 502 | WM5100_MIXER_INPUT_ROUTES(name " Input 4") |
| 503 | |
| 504 | static const char *wm5100_lhpf_mode_text[] = { |
| 505 | "Low-pass", "High-pass" |
| 506 | }; |
| 507 | |
| 508 | static const struct soc_enum wm5100_lhpf1_mode = |
| 509 | SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2, |
| 510 | wm5100_lhpf_mode_text); |
| 511 | |
| 512 | static const struct soc_enum wm5100_lhpf2_mode = |
| 513 | SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2, |
| 514 | wm5100_lhpf_mode_text); |
| 515 | |
| 516 | static const struct soc_enum wm5100_lhpf3_mode = |
| 517 | SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2, |
| 518 | wm5100_lhpf_mode_text); |
| 519 | |
| 520 | static const struct soc_enum wm5100_lhpf4_mode = |
| 521 | SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2, |
| 522 | wm5100_lhpf_mode_text); |
| 523 | |
| 524 | static const struct snd_kcontrol_new wm5100_snd_controls[] = { |
| 525 | SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL, |
| 526 | WM5100_IN1_OSR_SHIFT, 1, 0), |
| 527 | SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL, |
| 528 | WM5100_IN2_OSR_SHIFT, 1, 0), |
| 529 | SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL, |
| 530 | WM5100_IN3_OSR_SHIFT, 1, 0), |
| 531 | SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL, |
| 532 | WM5100_IN4_OSR_SHIFT, 1, 0), |
| 533 | |
| 534 | /* Only applicable for analogue inputs */ |
| 535 | SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL, |
| 536 | WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv), |
| 537 | SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL, |
| 538 | WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv), |
| 539 | SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL, |
| 540 | WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv), |
| 541 | SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL, |
| 542 | WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv), |
| 543 | |
| 544 | SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L, |
| 545 | WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191, |
| 546 | 0, digital_tlv), |
| 547 | SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L, |
| 548 | WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191, |
| 549 | 0, digital_tlv), |
| 550 | SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L, |
| 551 | WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191, |
| 552 | 0, digital_tlv), |
| 553 | SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L, |
| 554 | WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191, |
| 555 | 0, digital_tlv), |
| 556 | |
| 557 | SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L, |
| 558 | WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1), |
| 559 | SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L, |
| 560 | WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1), |
| 561 | SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L, |
| 562 | WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1), |
| 563 | SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L, |
| 564 | WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1), |
| 565 | |
| 566 | SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L, |
| 567 | WM5100_OUT1_OSR_SHIFT, 1, 0), |
| 568 | SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L, |
| 569 | WM5100_OUT2_OSR_SHIFT, 1, 0), |
| 570 | SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L, |
| 571 | WM5100_OUT3_OSR_SHIFT, 1, 0), |
| 572 | SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L, |
| 573 | WM5100_OUT4_OSR_SHIFT, 1, 0), |
| 574 | SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L, |
| 575 | WM5100_OUT5_OSR_SHIFT, 1, 0), |
| 576 | SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L, |
| 577 | WM5100_OUT6_OSR_SHIFT, 1, 0), |
| 578 | |
| 579 | SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L, |
| 580 | WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0, |
| 581 | digital_tlv), |
| 582 | SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L, |
| 583 | WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0, |
| 584 | digital_tlv), |
| 585 | SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L, |
| 586 | WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0, |
| 587 | digital_tlv), |
| 588 | SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L, |
| 589 | WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0, |
| 590 | digital_tlv), |
| 591 | SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L, |
| 592 | WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0, |
| 593 | digital_tlv), |
| 594 | SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L, |
| 595 | WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0, |
| 596 | digital_tlv), |
| 597 | |
| 598 | SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L, |
| 599 | WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1), |
| 600 | SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L, |
| 601 | WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1), |
| 602 | SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L, |
| 603 | WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1), |
| 604 | SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L, |
| 605 | WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1), |
| 606 | SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L, |
| 607 | WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1), |
| 608 | SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L, |
| 609 | WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1), |
| 610 | |
| 611 | /* FIXME: Only valid from -12dB to 0dB (52-64) */ |
| 612 | SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R, |
| 613 | WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv), |
| 614 | SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R, |
| 615 | WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv), |
| 616 | SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R, |
| 617 | WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv), |
| 618 | |
| 619 | SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT, |
| 620 | WM5100_SPK1R_MUTE_SHIFT, 1, 1), |
| 621 | SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT, |
| 622 | WM5100_SPK2R_MUTE_SHIFT, 1, 1), |
| 623 | |
| 624 | SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT, |
| 625 | 24, 0, eq_tlv), |
| 626 | SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT, |
| 627 | 24, 0, eq_tlv), |
| 628 | SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT, |
| 629 | 24, 0, eq_tlv), |
| 630 | SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT, |
| 631 | 24, 0, eq_tlv), |
| 632 | SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT, |
| 633 | 24, 0, eq_tlv), |
| 634 | |
| 635 | SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT, |
| 636 | 24, 0, eq_tlv), |
| 637 | SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT, |
| 638 | 24, 0, eq_tlv), |
| 639 | SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT, |
| 640 | 24, 0, eq_tlv), |
| 641 | SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT, |
| 642 | 24, 0, eq_tlv), |
| 643 | SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT, |
| 644 | 24, 0, eq_tlv), |
| 645 | |
| 646 | SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT, |
| 647 | 24, 0, eq_tlv), |
| 648 | SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT, |
| 649 | 24, 0, eq_tlv), |
| 650 | SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT, |
| 651 | 24, 0, eq_tlv), |
| 652 | SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT, |
| 653 | 24, 0, eq_tlv), |
| 654 | SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT, |
| 655 | 24, 0, eq_tlv), |
| 656 | |
| 657 | SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT, |
| 658 | 24, 0, eq_tlv), |
| 659 | SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT, |
| 660 | 24, 0, eq_tlv), |
| 661 | SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT, |
| 662 | 24, 0, eq_tlv), |
| 663 | SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT, |
| 664 | 24, 0, eq_tlv), |
| 665 | SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT, |
| 666 | 24, 0, eq_tlv), |
| 667 | |
| 668 | SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode), |
| 669 | SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode), |
| 670 | SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode), |
| 671 | SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode), |
| 672 | |
| 673 | WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE), |
| 674 | WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE), |
| 675 | WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE), |
| 676 | WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE), |
| 677 | WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE), |
| 678 | WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE), |
| 679 | |
| 680 | WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE), |
| 681 | WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE), |
| 682 | WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE), |
| 683 | WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE), |
| 684 | WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE), |
| 685 | WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE), |
| 686 | |
| 687 | WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE), |
| 688 | WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE), |
| 689 | |
| 690 | WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE), |
| 691 | WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE), |
| 692 | WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE), |
| 693 | WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE), |
| 694 | WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE), |
| 695 | WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE), |
| 696 | WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE), |
| 697 | WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE), |
| 698 | |
| 699 | WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE), |
| 700 | WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE), |
| 701 | |
| 702 | WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE), |
| 703 | WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE), |
| 704 | |
| 705 | WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE), |
| 706 | WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE), |
| 707 | WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE), |
| 708 | WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE), |
| 709 | |
| 710 | WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE), |
| 711 | WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE), |
Mark Brown | cdaaf30 | 2011-10-10 18:31:44 +0100 | [diff] [blame] | 712 | SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5, |
| 713 | WM5100_DRCL_ENA | WM5100_DRCR_ENA), |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 714 | |
| 715 | WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE), |
| 716 | WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE), |
| 717 | WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE), |
| 718 | WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE), |
| 719 | }; |
| 720 | |
| 721 | static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm, |
| 722 | enum snd_soc_dapm_type event, int subseq) |
| 723 | { |
| 724 | struct snd_soc_codec *codec = container_of(dapm, |
| 725 | struct snd_soc_codec, dapm); |
| 726 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 727 | u16 val, expect, i; |
| 728 | |
| 729 | /* Wait for the outputs to flag themselves as enabled */ |
| 730 | if (wm5100->out_ena[0]) { |
| 731 | expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1); |
| 732 | for (i = 0; i < 200; i++) { |
| 733 | val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1); |
| 734 | if (val == expect) { |
| 735 | wm5100->out_ena[0] = false; |
| 736 | break; |
| 737 | } |
| 738 | } |
| 739 | if (i == 200) { |
| 740 | dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n", |
| 741 | expect); |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | if (wm5100->out_ena[1]) { |
| 746 | expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2); |
| 747 | for (i = 0; i < 200; i++) { |
| 748 | val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2); |
| 749 | if (val == expect) { |
| 750 | wm5100->out_ena[1] = false; |
| 751 | break; |
| 752 | } |
| 753 | } |
| 754 | if (i == 200) { |
| 755 | dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n", |
| 756 | expect); |
| 757 | } |
| 758 | } |
| 759 | } |
| 760 | |
| 761 | static int wm5100_out_ev(struct snd_soc_dapm_widget *w, |
| 762 | struct snd_kcontrol *kcontrol, |
| 763 | int event) |
| 764 | { |
| 765 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec); |
| 766 | |
| 767 | switch (w->reg) { |
| 768 | case WM5100_CHANNEL_ENABLES_1: |
| 769 | wm5100->out_ena[0] = true; |
| 770 | break; |
| 771 | case WM5100_OUTPUT_ENABLES_2: |
| 772 | wm5100->out_ena[0] = true; |
| 773 | break; |
| 774 | default: |
| 775 | break; |
| 776 | } |
| 777 | |
| 778 | return 0; |
| 779 | } |
| 780 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 781 | static void wm5100_log_status3(struct wm5100_priv *wm5100, int val) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 782 | { |
| 783 | if (val & WM5100_SPK_SHUTDOWN_WARN_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 784 | dev_crit(wm5100->dev, "Speaker shutdown warning\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 785 | if (val & WM5100_SPK_SHUTDOWN_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 786 | dev_crit(wm5100->dev, "Speaker shutdown\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 787 | if (val & WM5100_CLKGEN_ERR_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 788 | dev_crit(wm5100->dev, "SYSCLK underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 789 | if (val & WM5100_CLKGEN_ERR_ASYNC_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 790 | dev_crit(wm5100->dev, "ASYNCCLK underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 791 | } |
| 792 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 793 | static void wm5100_log_status4(struct wm5100_priv *wm5100, int val) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 794 | { |
| 795 | if (val & WM5100_AIF3_ERR_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 796 | dev_err(wm5100->dev, "AIF3 configuration error\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 797 | if (val & WM5100_AIF2_ERR_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 798 | dev_err(wm5100->dev, "AIF2 configuration error\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 799 | if (val & WM5100_AIF1_ERR_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 800 | dev_err(wm5100->dev, "AIF1 configuration error\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 801 | if (val & WM5100_CTRLIF_ERR_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 802 | dev_err(wm5100->dev, "Control interface error\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 803 | if (val & WM5100_ISRC2_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 804 | dev_err(wm5100->dev, "ISRC2 underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 805 | if (val & WM5100_ISRC1_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 806 | dev_err(wm5100->dev, "ISRC1 underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 807 | if (val & WM5100_FX_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 808 | dev_err(wm5100->dev, "FX underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 809 | if (val & WM5100_AIF3_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 810 | dev_err(wm5100->dev, "AIF3 underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 811 | if (val & WM5100_AIF2_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 812 | dev_err(wm5100->dev, "AIF2 underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 813 | if (val & WM5100_AIF1_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 814 | dev_err(wm5100->dev, "AIF1 underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 815 | if (val & WM5100_ASRC_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 816 | dev_err(wm5100->dev, "ASRC underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 817 | if (val & WM5100_DAC_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 818 | dev_err(wm5100->dev, "DAC underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 819 | if (val & WM5100_ADC_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 820 | dev_err(wm5100->dev, "ADC underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 821 | if (val & WM5100_MIXER_UNDERCLOCKED_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 822 | dev_err(wm5100->dev, "Mixer underclocked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 823 | } |
| 824 | |
| 825 | static int wm5100_post_ev(struct snd_soc_dapm_widget *w, |
| 826 | struct snd_kcontrol *kcontrol, |
| 827 | int event) |
| 828 | { |
| 829 | struct snd_soc_codec *codec = w->codec; |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 830 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 831 | int ret; |
| 832 | |
| 833 | ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3); |
| 834 | ret &= WM5100_SPK_SHUTDOWN_WARN_STS | |
| 835 | WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS | |
| 836 | WM5100_CLKGEN_ERR_ASYNC_STS; |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 837 | wm5100_log_status3(wm5100, ret); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 838 | |
| 839 | ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4); |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 840 | wm5100_log_status4(wm5100, ret); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 841 | |
| 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = { |
| 846 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0, |
| 847 | NULL, 0), |
| 848 | SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT, |
| 849 | 0, NULL, 0), |
| 850 | |
Mark Brown | 822b4b8 | 2012-09-07 10:54:32 +0800 | [diff] [blame] | 851 | SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), |
| 852 | SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0), |
| 853 | SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0), |
Mark Brown | 1cf7335 | 2012-01-21 22:10:24 +0000 | [diff] [blame] | 854 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 855 | SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0, |
Mark Brown | 1cf7335 | 2012-01-21 22:10:24 +0000 | [diff] [blame] | 856 | NULL, 0), |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 857 | SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0, |
| 858 | NULL, 0), |
| 859 | SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1, |
Mark Brown | 1cf7335 | 2012-01-21 22:10:24 +0000 | [diff] [blame] | 860 | WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0), |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 861 | |
| 862 | SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT, |
| 863 | 0, NULL, 0), |
| 864 | SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT, |
| 865 | 0, NULL, 0), |
| 866 | SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT, |
| 867 | 0, NULL, 0), |
| 868 | |
| 869 | SND_SOC_DAPM_INPUT("IN1L"), |
| 870 | SND_SOC_DAPM_INPUT("IN1R"), |
| 871 | SND_SOC_DAPM_INPUT("IN2L"), |
| 872 | SND_SOC_DAPM_INPUT("IN2R"), |
| 873 | SND_SOC_DAPM_INPUT("IN3L"), |
| 874 | SND_SOC_DAPM_INPUT("IN3R"), |
| 875 | SND_SOC_DAPM_INPUT("IN4L"), |
| 876 | SND_SOC_DAPM_INPUT("IN4R"), |
Mark Brown | dea8e23 | 2011-11-27 16:24:05 +0000 | [diff] [blame] | 877 | SND_SOC_DAPM_SIGGEN("TONE"), |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 878 | |
| 879 | SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0, |
| 880 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 881 | SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0, |
| 882 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 883 | SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0, |
| 884 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 885 | SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0, |
| 886 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 887 | SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0, |
| 888 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 889 | SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0, |
| 890 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 891 | SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0, |
| 892 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 893 | SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0, |
| 894 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 895 | |
| 896 | SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1, |
| 897 | WM5100_TONE1_ENA_SHIFT, 0, NULL, 0), |
| 898 | SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1, |
| 899 | WM5100_TONE2_ENA_SHIFT, 0, NULL, 0), |
| 900 | |
| 901 | SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0, |
| 902 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0), |
| 903 | SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1, |
| 904 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0), |
| 905 | SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2, |
| 906 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0), |
| 907 | SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3, |
| 908 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0), |
| 909 | SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4, |
| 910 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0), |
| 911 | SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5, |
| 912 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0), |
| 913 | SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6, |
| 914 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0), |
| 915 | SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7, |
| 916 | WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0), |
| 917 | |
| 918 | SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0, |
| 919 | WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0), |
| 920 | SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1, |
| 921 | WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0), |
| 922 | |
| 923 | SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0, |
| 924 | WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0), |
| 925 | SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1, |
| 926 | WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0), |
| 927 | |
| 928 | SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0, |
| 929 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0), |
| 930 | SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1, |
| 931 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0), |
| 932 | SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2, |
| 933 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0), |
| 934 | SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3, |
| 935 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0), |
| 936 | SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4, |
| 937 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0), |
| 938 | SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5, |
| 939 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0), |
| 940 | SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6, |
| 941 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0), |
| 942 | SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7, |
| 943 | WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0), |
| 944 | |
| 945 | SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0, |
| 946 | WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0), |
| 947 | SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1, |
| 948 | WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0), |
| 949 | |
| 950 | SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0, |
| 951 | WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0), |
| 952 | SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1, |
| 953 | WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0), |
| 954 | |
| 955 | SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0, |
| 956 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 957 | SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0, |
| 958 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 959 | SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0, |
| 960 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 961 | SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0, |
| 962 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 963 | SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0, |
| 964 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 965 | SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0, |
| 966 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 967 | SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0, |
| 968 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 969 | SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0, |
| 970 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 971 | SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0, |
| 972 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 973 | SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0, |
| 974 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 975 | SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0, |
| 976 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 977 | SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0, |
| 978 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 979 | SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0, |
| 980 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 981 | SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0, |
| 982 | NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU), |
| 983 | |
| 984 | SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0), |
| 985 | SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0), |
| 986 | SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0), |
| 987 | SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0), |
| 988 | |
| 989 | SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0, |
| 990 | NULL, 0), |
| 991 | SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0, |
| 992 | NULL, 0), |
| 993 | |
| 994 | SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0, |
| 995 | NULL, 0), |
| 996 | SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0, |
| 997 | NULL, 0), |
| 998 | SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0, |
| 999 | NULL, 0), |
| 1000 | SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0, |
| 1001 | NULL, 0), |
| 1002 | |
| 1003 | WM5100_MIXER_WIDGETS(EQ1, "EQ1"), |
| 1004 | WM5100_MIXER_WIDGETS(EQ2, "EQ2"), |
| 1005 | WM5100_MIXER_WIDGETS(EQ3, "EQ3"), |
| 1006 | WM5100_MIXER_WIDGETS(EQ4, "EQ4"), |
| 1007 | |
| 1008 | WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"), |
| 1009 | WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"), |
| 1010 | |
| 1011 | WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"), |
| 1012 | WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"), |
| 1013 | WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"), |
| 1014 | WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"), |
| 1015 | |
| 1016 | WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), |
| 1017 | WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), |
| 1018 | WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), |
| 1019 | WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), |
| 1020 | WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), |
| 1021 | WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), |
| 1022 | WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"), |
| 1023 | WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"), |
| 1024 | |
| 1025 | WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), |
| 1026 | WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), |
| 1027 | |
| 1028 | WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), |
| 1029 | WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), |
| 1030 | |
| 1031 | WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"), |
| 1032 | WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"), |
| 1033 | WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"), |
| 1034 | WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"), |
| 1035 | WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"), |
| 1036 | WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"), |
| 1037 | |
| 1038 | WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"), |
| 1039 | WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"), |
| 1040 | WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"), |
| 1041 | WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"), |
| 1042 | WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"), |
| 1043 | WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"), |
| 1044 | |
| 1045 | WM5100_MIXER_WIDGETS(PWM1, "PWM1"), |
| 1046 | WM5100_MIXER_WIDGETS(PWM2, "PWM2"), |
| 1047 | |
| 1048 | SND_SOC_DAPM_OUTPUT("HPOUT1L"), |
| 1049 | SND_SOC_DAPM_OUTPUT("HPOUT1R"), |
| 1050 | SND_SOC_DAPM_OUTPUT("HPOUT2L"), |
| 1051 | SND_SOC_DAPM_OUTPUT("HPOUT2R"), |
| 1052 | SND_SOC_DAPM_OUTPUT("HPOUT3L"), |
| 1053 | SND_SOC_DAPM_OUTPUT("HPOUT3R"), |
| 1054 | SND_SOC_DAPM_OUTPUT("SPKOUTL"), |
| 1055 | SND_SOC_DAPM_OUTPUT("SPKOUTR"), |
| 1056 | SND_SOC_DAPM_OUTPUT("SPKDAT1"), |
| 1057 | SND_SOC_DAPM_OUTPUT("SPKDAT2"), |
| 1058 | SND_SOC_DAPM_OUTPUT("PWM1"), |
| 1059 | SND_SOC_DAPM_OUTPUT("PWM2"), |
| 1060 | }; |
| 1061 | |
| 1062 | /* We register a _POST event if we don't have IRQ support so we can |
| 1063 | * look at the error status from the CODEC - if we've got the IRQ |
| 1064 | * hooked up then we will get prompted to look by an interrupt. |
| 1065 | */ |
| 1066 | static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = { |
| 1067 | SND_SOC_DAPM_POST("Post", wm5100_post_ev), |
| 1068 | }; |
| 1069 | |
| 1070 | static const struct snd_soc_dapm_route wm5100_dapm_routes[] = { |
Mark Brown | 1cf7335 | 2012-01-21 22:10:24 +0000 | [diff] [blame] | 1071 | { "CP1", NULL, "CPVDD" }, |
| 1072 | { "CP2 Active", NULL, "CPVDD" }, |
| 1073 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1074 | { "IN1L", NULL, "SYSCLK" }, |
| 1075 | { "IN1R", NULL, "SYSCLK" }, |
| 1076 | { "IN2L", NULL, "SYSCLK" }, |
| 1077 | { "IN2R", NULL, "SYSCLK" }, |
| 1078 | { "IN3L", NULL, "SYSCLK" }, |
| 1079 | { "IN3R", NULL, "SYSCLK" }, |
| 1080 | { "IN4L", NULL, "SYSCLK" }, |
| 1081 | { "IN4R", NULL, "SYSCLK" }, |
| 1082 | |
| 1083 | { "OUT1L", NULL, "SYSCLK" }, |
| 1084 | { "OUT1R", NULL, "SYSCLK" }, |
| 1085 | { "OUT2L", NULL, "SYSCLK" }, |
| 1086 | { "OUT2R", NULL, "SYSCLK" }, |
| 1087 | { "OUT3L", NULL, "SYSCLK" }, |
| 1088 | { "OUT3R", NULL, "SYSCLK" }, |
| 1089 | { "OUT4L", NULL, "SYSCLK" }, |
| 1090 | { "OUT4R", NULL, "SYSCLK" }, |
| 1091 | { "OUT5L", NULL, "SYSCLK" }, |
| 1092 | { "OUT5R", NULL, "SYSCLK" }, |
| 1093 | { "OUT6L", NULL, "SYSCLK" }, |
| 1094 | { "OUT6R", NULL, "SYSCLK" }, |
| 1095 | |
| 1096 | { "AIF1RX1", NULL, "SYSCLK" }, |
| 1097 | { "AIF1RX2", NULL, "SYSCLK" }, |
| 1098 | { "AIF1RX3", NULL, "SYSCLK" }, |
| 1099 | { "AIF1RX4", NULL, "SYSCLK" }, |
| 1100 | { "AIF1RX5", NULL, "SYSCLK" }, |
| 1101 | { "AIF1RX6", NULL, "SYSCLK" }, |
| 1102 | { "AIF1RX7", NULL, "SYSCLK" }, |
| 1103 | { "AIF1RX8", NULL, "SYSCLK" }, |
| 1104 | |
| 1105 | { "AIF2RX1", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1106 | { "AIF2RX1", NULL, "DBVDD2" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1107 | { "AIF2RX2", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1108 | { "AIF2RX2", NULL, "DBVDD2" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1109 | |
| 1110 | { "AIF3RX1", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1111 | { "AIF3RX1", NULL, "DBVDD3" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1112 | { "AIF3RX2", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1113 | { "AIF3RX2", NULL, "DBVDD3" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1114 | |
| 1115 | { "AIF1TX1", NULL, "SYSCLK" }, |
| 1116 | { "AIF1TX2", NULL, "SYSCLK" }, |
| 1117 | { "AIF1TX3", NULL, "SYSCLK" }, |
| 1118 | { "AIF1TX4", NULL, "SYSCLK" }, |
| 1119 | { "AIF1TX5", NULL, "SYSCLK" }, |
| 1120 | { "AIF1TX6", NULL, "SYSCLK" }, |
| 1121 | { "AIF1TX7", NULL, "SYSCLK" }, |
| 1122 | { "AIF1TX8", NULL, "SYSCLK" }, |
| 1123 | |
| 1124 | { "AIF2TX1", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1125 | { "AIF2TX1", NULL, "DBVDD2" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1126 | { "AIF2TX2", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1127 | { "AIF2TX2", NULL, "DBVDD2" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1128 | |
| 1129 | { "AIF3TX1", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1130 | { "AIF3TX1", NULL, "DBVDD3" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1131 | { "AIF3TX2", NULL, "SYSCLK" }, |
Mark Brown | 7aefb08 | 2011-09-21 17:59:02 +0100 | [diff] [blame] | 1132 | { "AIF3TX2", NULL, "DBVDD3" }, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1133 | |
| 1134 | { "MICBIAS1", NULL, "CP2" }, |
| 1135 | { "MICBIAS2", NULL, "CP2" }, |
| 1136 | { "MICBIAS3", NULL, "CP2" }, |
| 1137 | |
| 1138 | { "IN1L PGA", NULL, "CP2" }, |
| 1139 | { "IN1R PGA", NULL, "CP2" }, |
| 1140 | { "IN2L PGA", NULL, "CP2" }, |
| 1141 | { "IN2R PGA", NULL, "CP2" }, |
| 1142 | { "IN3L PGA", NULL, "CP2" }, |
| 1143 | { "IN3R PGA", NULL, "CP2" }, |
| 1144 | { "IN4L PGA", NULL, "CP2" }, |
| 1145 | { "IN4R PGA", NULL, "CP2" }, |
| 1146 | |
| 1147 | { "IN1L PGA", NULL, "CP2 Active" }, |
| 1148 | { "IN1R PGA", NULL, "CP2 Active" }, |
| 1149 | { "IN2L PGA", NULL, "CP2 Active" }, |
| 1150 | { "IN2R PGA", NULL, "CP2 Active" }, |
| 1151 | { "IN3L PGA", NULL, "CP2 Active" }, |
| 1152 | { "IN3R PGA", NULL, "CP2 Active" }, |
| 1153 | { "IN4L PGA", NULL, "CP2 Active" }, |
| 1154 | { "IN4R PGA", NULL, "CP2 Active" }, |
| 1155 | |
| 1156 | { "OUT1L", NULL, "CP1" }, |
| 1157 | { "OUT1R", NULL, "CP1" }, |
| 1158 | { "OUT2L", NULL, "CP1" }, |
| 1159 | { "OUT2R", NULL, "CP1" }, |
| 1160 | { "OUT3L", NULL, "CP1" }, |
| 1161 | { "OUT3R", NULL, "CP1" }, |
| 1162 | |
| 1163 | { "Tone Generator 1", NULL, "TONE" }, |
| 1164 | { "Tone Generator 2", NULL, "TONE" }, |
| 1165 | |
| 1166 | { "IN1L PGA", NULL, "IN1L" }, |
| 1167 | { "IN1R PGA", NULL, "IN1R" }, |
| 1168 | { "IN2L PGA", NULL, "IN2L" }, |
| 1169 | { "IN2R PGA", NULL, "IN2R" }, |
| 1170 | { "IN3L PGA", NULL, "IN3L" }, |
| 1171 | { "IN3R PGA", NULL, "IN3R" }, |
| 1172 | { "IN4L PGA", NULL, "IN4L" }, |
| 1173 | { "IN4R PGA", NULL, "IN4R" }, |
| 1174 | |
| 1175 | WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"), |
| 1176 | WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"), |
| 1177 | WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"), |
| 1178 | WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"), |
| 1179 | WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"), |
| 1180 | WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"), |
| 1181 | |
| 1182 | WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"), |
| 1183 | WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"), |
| 1184 | WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"), |
| 1185 | WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"), |
| 1186 | WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"), |
| 1187 | WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"), |
| 1188 | |
| 1189 | WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"), |
| 1190 | WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"), |
| 1191 | |
| 1192 | WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), |
| 1193 | WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), |
| 1194 | WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), |
| 1195 | WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), |
| 1196 | WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), |
| 1197 | WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), |
| 1198 | WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"), |
| 1199 | WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"), |
| 1200 | |
| 1201 | WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), |
| 1202 | WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), |
| 1203 | |
| 1204 | WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), |
| 1205 | WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), |
| 1206 | |
| 1207 | WM5100_MIXER_ROUTES("EQ1", "EQ1"), |
| 1208 | WM5100_MIXER_ROUTES("EQ2", "EQ2"), |
| 1209 | WM5100_MIXER_ROUTES("EQ3", "EQ3"), |
| 1210 | WM5100_MIXER_ROUTES("EQ4", "EQ4"), |
| 1211 | |
| 1212 | WM5100_MIXER_ROUTES("DRC1L", "DRC1L"), |
| 1213 | WM5100_MIXER_ROUTES("DRC1R", "DRC1R"), |
| 1214 | |
| 1215 | WM5100_MIXER_ROUTES("LHPF1", "LHPF1"), |
| 1216 | WM5100_MIXER_ROUTES("LHPF2", "LHPF2"), |
| 1217 | WM5100_MIXER_ROUTES("LHPF3", "LHPF3"), |
| 1218 | WM5100_MIXER_ROUTES("LHPF4", "LHPF4"), |
| 1219 | |
| 1220 | { "HPOUT1L", NULL, "OUT1L" }, |
| 1221 | { "HPOUT1R", NULL, "OUT1R" }, |
| 1222 | { "HPOUT2L", NULL, "OUT2L" }, |
| 1223 | { "HPOUT2R", NULL, "OUT2R" }, |
| 1224 | { "HPOUT3L", NULL, "OUT3L" }, |
| 1225 | { "HPOUT3R", NULL, "OUT3R" }, |
| 1226 | { "SPKOUTL", NULL, "OUT4L" }, |
| 1227 | { "SPKOUTR", NULL, "OUT4R" }, |
| 1228 | { "SPKDAT1", NULL, "OUT5L" }, |
| 1229 | { "SPKDAT1", NULL, "OUT5R" }, |
| 1230 | { "SPKDAT2", NULL, "OUT6L" }, |
| 1231 | { "SPKDAT2", NULL, "OUT6R" }, |
| 1232 | { "PWM1", NULL, "PWM1 Driver" }, |
| 1233 | { "PWM2", NULL, "PWM2 Driver" }, |
| 1234 | }; |
| 1235 | |
Andi Kleen | c7fd5bc | 2012-10-04 17:12:13 -0700 | [diff] [blame] | 1236 | static const __devinitconst struct reg_default wm5100_reva_patches[] = { |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1237 | { WM5100_AUDIO_IF_1_10, 0 }, |
| 1238 | { WM5100_AUDIO_IF_1_11, 1 }, |
| 1239 | { WM5100_AUDIO_IF_1_12, 2 }, |
| 1240 | { WM5100_AUDIO_IF_1_13, 3 }, |
| 1241 | { WM5100_AUDIO_IF_1_14, 4 }, |
| 1242 | { WM5100_AUDIO_IF_1_15, 5 }, |
| 1243 | { WM5100_AUDIO_IF_1_16, 6 }, |
| 1244 | { WM5100_AUDIO_IF_1_17, 7 }, |
| 1245 | |
| 1246 | { WM5100_AUDIO_IF_1_18, 0 }, |
| 1247 | { WM5100_AUDIO_IF_1_19, 1 }, |
| 1248 | { WM5100_AUDIO_IF_1_20, 2 }, |
| 1249 | { WM5100_AUDIO_IF_1_21, 3 }, |
| 1250 | { WM5100_AUDIO_IF_1_22, 4 }, |
| 1251 | { WM5100_AUDIO_IF_1_23, 5 }, |
| 1252 | { WM5100_AUDIO_IF_1_24, 6 }, |
| 1253 | { WM5100_AUDIO_IF_1_25, 7 }, |
| 1254 | |
| 1255 | { WM5100_AUDIO_IF_2_10, 0 }, |
| 1256 | { WM5100_AUDIO_IF_2_11, 1 }, |
| 1257 | |
| 1258 | { WM5100_AUDIO_IF_2_18, 0 }, |
| 1259 | { WM5100_AUDIO_IF_2_19, 1 }, |
| 1260 | |
| 1261 | { WM5100_AUDIO_IF_3_10, 0 }, |
| 1262 | { WM5100_AUDIO_IF_3_11, 1 }, |
| 1263 | |
| 1264 | { WM5100_AUDIO_IF_3_18, 0 }, |
| 1265 | { WM5100_AUDIO_IF_3_19, 1 }, |
| 1266 | }; |
| 1267 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1268 | static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 1269 | { |
| 1270 | struct snd_soc_codec *codec = dai->codec; |
| 1271 | int lrclk, bclk, mask, base; |
| 1272 | |
Mark Brown | 9b52312 | 2012-05-01 20:03:52 +0100 | [diff] [blame] | 1273 | base = dai->driver->base; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1274 | |
| 1275 | lrclk = 0; |
| 1276 | bclk = 0; |
| 1277 | |
| 1278 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1279 | case SND_SOC_DAIFMT_DSP_A: |
| 1280 | mask = 0; |
| 1281 | break; |
| 1282 | case SND_SOC_DAIFMT_DSP_B: |
| 1283 | mask = 1; |
| 1284 | break; |
| 1285 | case SND_SOC_DAIFMT_I2S: |
| 1286 | mask = 2; |
| 1287 | break; |
| 1288 | case SND_SOC_DAIFMT_LEFT_J: |
| 1289 | mask = 3; |
| 1290 | break; |
| 1291 | default: |
| 1292 | dev_err(codec->dev, "Unsupported DAI format %d\n", |
| 1293 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); |
| 1294 | return -EINVAL; |
| 1295 | } |
| 1296 | |
| 1297 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1298 | case SND_SOC_DAIFMT_CBS_CFS: |
| 1299 | break; |
| 1300 | case SND_SOC_DAIFMT_CBS_CFM: |
| 1301 | lrclk |= WM5100_AIF1TX_LRCLK_MSTR; |
| 1302 | break; |
| 1303 | case SND_SOC_DAIFMT_CBM_CFS: |
| 1304 | bclk |= WM5100_AIF1_BCLK_MSTR; |
| 1305 | break; |
| 1306 | case SND_SOC_DAIFMT_CBM_CFM: |
| 1307 | lrclk |= WM5100_AIF1TX_LRCLK_MSTR; |
| 1308 | bclk |= WM5100_AIF1_BCLK_MSTR; |
| 1309 | break; |
| 1310 | default: |
| 1311 | dev_err(codec->dev, "Unsupported master mode %d\n", |
| 1312 | fmt & SND_SOC_DAIFMT_MASTER_MASK); |
| 1313 | return -EINVAL; |
| 1314 | } |
| 1315 | |
| 1316 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1317 | case SND_SOC_DAIFMT_NB_NF: |
| 1318 | break; |
| 1319 | case SND_SOC_DAIFMT_IB_IF: |
| 1320 | bclk |= WM5100_AIF1_BCLK_INV; |
| 1321 | lrclk |= WM5100_AIF1TX_LRCLK_INV; |
| 1322 | break; |
| 1323 | case SND_SOC_DAIFMT_IB_NF: |
| 1324 | bclk |= WM5100_AIF1_BCLK_INV; |
| 1325 | break; |
| 1326 | case SND_SOC_DAIFMT_NB_IF: |
| 1327 | lrclk |= WM5100_AIF1TX_LRCLK_INV; |
| 1328 | break; |
| 1329 | default: |
| 1330 | return -EINVAL; |
| 1331 | } |
| 1332 | |
| 1333 | snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR | |
| 1334 | WM5100_AIF1_BCLK_INV, bclk); |
| 1335 | snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR | |
| 1336 | WM5100_AIF1TX_LRCLK_INV, lrclk); |
| 1337 | snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR | |
| 1338 | WM5100_AIF1TX_LRCLK_INV, lrclk); |
| 1339 | snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask); |
| 1340 | |
| 1341 | return 0; |
| 1342 | } |
| 1343 | |
| 1344 | #define WM5100_NUM_BCLK_RATES 19 |
| 1345 | |
| 1346 | static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = { |
| 1347 | 32000, |
| 1348 | 48000, |
| 1349 | 64000, |
| 1350 | 96000, |
| 1351 | 128000, |
| 1352 | 192000, |
Mark Brown | d73ec75 | 2011-09-22 17:48:01 +0100 | [diff] [blame] | 1353 | 256000, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1354 | 384000, |
| 1355 | 512000, |
| 1356 | 768000, |
| 1357 | 1024000, |
| 1358 | 1536000, |
| 1359 | 2048000, |
| 1360 | 3072000, |
| 1361 | 4096000, |
| 1362 | 6144000, |
| 1363 | 8192000, |
| 1364 | 12288000, |
| 1365 | 24576000, |
| 1366 | }; |
| 1367 | |
| 1368 | static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = { |
| 1369 | 29400, |
| 1370 | 44100, |
| 1371 | 58800, |
| 1372 | 88200, |
| 1373 | 117600, |
| 1374 | 176400, |
| 1375 | 235200, |
| 1376 | 352800, |
| 1377 | 470400, |
| 1378 | 705600, |
| 1379 | 940800, |
| 1380 | 1411200, |
| 1381 | 1881600, |
| 1382 | 2882400, |
| 1383 | 3763200, |
| 1384 | 5644800, |
| 1385 | 7526400, |
| 1386 | 11289600, |
| 1387 | 22579600, |
| 1388 | }; |
| 1389 | |
| 1390 | static int wm5100_hw_params(struct snd_pcm_substream *substream, |
| 1391 | struct snd_pcm_hw_params *params, |
| 1392 | struct snd_soc_dai *dai) |
| 1393 | { |
| 1394 | struct snd_soc_codec *codec = dai->codec; |
| 1395 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 1396 | bool async = wm5100->aif_async[dai->id]; |
| 1397 | int i, base, bclk, aif_rate, lrclk, wl, fl, sr; |
| 1398 | int *bclk_rates; |
| 1399 | |
Mark Brown | 9b52312 | 2012-05-01 20:03:52 +0100 | [diff] [blame] | 1400 | base = dai->driver->base; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1401 | |
| 1402 | /* Data sizes if not using TDM */ |
| 1403 | wl = snd_pcm_format_width(params_format(params)); |
| 1404 | if (wl < 0) |
| 1405 | return wl; |
| 1406 | fl = snd_soc_params_to_frame_size(params); |
| 1407 | if (fl < 0) |
| 1408 | return fl; |
| 1409 | |
| 1410 | dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n", |
| 1411 | wl, fl); |
| 1412 | |
| 1413 | /* Target BCLK rate */ |
| 1414 | bclk = snd_soc_params_to_bclk(params); |
| 1415 | if (bclk < 0) |
| 1416 | return bclk; |
| 1417 | |
| 1418 | /* Root for BCLK depends on SYS/ASYNCCLK */ |
| 1419 | if (!async) { |
| 1420 | aif_rate = wm5100->sysclk; |
| 1421 | sr = wm5100_alloc_sr(codec, params_rate(params)); |
| 1422 | if (sr < 0) |
| 1423 | return sr; |
| 1424 | } else { |
| 1425 | /* If we're in ASYNCCLK set the ASYNC sample rate */ |
| 1426 | aif_rate = wm5100->asyncclk; |
| 1427 | sr = 3; |
| 1428 | |
| 1429 | for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++) |
| 1430 | if (params_rate(params) == wm5100_sr_code[i]) |
| 1431 | break; |
| 1432 | if (i == ARRAY_SIZE(wm5100_sr_code)) { |
| 1433 | dev_err(codec->dev, "Invalid rate %dHzn", |
| 1434 | params_rate(params)); |
| 1435 | return -EINVAL; |
| 1436 | } |
| 1437 | |
| 1438 | /* TODO: We should really check for symmetry */ |
| 1439 | snd_soc_update_bits(codec, WM5100_CLOCKING_8, |
| 1440 | WM5100_ASYNC_SAMPLE_RATE_MASK, i); |
| 1441 | } |
| 1442 | |
| 1443 | if (!aif_rate) { |
| 1444 | dev_err(codec->dev, "%s has no rate set\n", |
| 1445 | async ? "ASYNCCLK" : "SYSCLK"); |
| 1446 | return -EINVAL; |
| 1447 | } |
| 1448 | |
| 1449 | dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n", |
| 1450 | bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK"); |
| 1451 | |
| 1452 | if (aif_rate % 4000) |
| 1453 | bclk_rates = wm5100_bclk_rates_cd; |
| 1454 | else |
| 1455 | bclk_rates = wm5100_bclk_rates_dat; |
| 1456 | |
| 1457 | for (i = 0; i < WM5100_NUM_BCLK_RATES; i++) |
| 1458 | if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0)) |
| 1459 | break; |
| 1460 | if (i == WM5100_NUM_BCLK_RATES) { |
| 1461 | dev_err(codec->dev, |
| 1462 | "No valid BCLK for %dHz found from %dHz %s\n", |
| 1463 | bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK"); |
| 1464 | return -EINVAL; |
| 1465 | } |
| 1466 | |
| 1467 | bclk = i; |
| 1468 | dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]); |
| 1469 | snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk); |
| 1470 | |
| 1471 | lrclk = bclk_rates[bclk] / params_rate(params); |
| 1472 | dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk); |
| 1473 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || |
| 1474 | wm5100->aif_symmetric[dai->id]) |
| 1475 | snd_soc_update_bits(codec, base + 7, |
| 1476 | WM5100_AIF1RX_BCPF_MASK, lrclk); |
| 1477 | else |
| 1478 | snd_soc_update_bits(codec, base + 6, |
| 1479 | WM5100_AIF1TX_BCPF_MASK, lrclk); |
| 1480 | |
| 1481 | i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl; |
| 1482 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 1483 | snd_soc_update_bits(codec, base + 9, |
| 1484 | WM5100_AIF1RX_WL_MASK | |
| 1485 | WM5100_AIF1RX_SLOT_LEN_MASK, i); |
| 1486 | else |
| 1487 | snd_soc_update_bits(codec, base + 8, |
| 1488 | WM5100_AIF1TX_WL_MASK | |
| 1489 | WM5100_AIF1TX_SLOT_LEN_MASK, i); |
| 1490 | |
| 1491 | snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr); |
| 1492 | |
| 1493 | return 0; |
| 1494 | } |
| 1495 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 1496 | static const struct snd_soc_dai_ops wm5100_dai_ops = { |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1497 | .set_fmt = wm5100_set_fmt, |
| 1498 | .hw_params = wm5100_hw_params, |
| 1499 | }; |
| 1500 | |
| 1501 | static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id, |
| 1502 | int source, unsigned int freq, int dir) |
| 1503 | { |
| 1504 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 1505 | int *rate_store; |
| 1506 | int fval, audio_rate, ret, reg; |
| 1507 | |
| 1508 | switch (clk_id) { |
| 1509 | case WM5100_CLK_SYSCLK: |
| 1510 | reg = WM5100_CLOCKING_3; |
| 1511 | rate_store = &wm5100->sysclk; |
| 1512 | break; |
| 1513 | case WM5100_CLK_ASYNCCLK: |
| 1514 | reg = WM5100_CLOCKING_7; |
| 1515 | rate_store = &wm5100->asyncclk; |
| 1516 | break; |
| 1517 | case WM5100_CLK_32KHZ: |
| 1518 | /* The 32kHz clock is slightly different to the others */ |
| 1519 | switch (source) { |
| 1520 | case WM5100_CLKSRC_MCLK1: |
| 1521 | case WM5100_CLKSRC_MCLK2: |
| 1522 | case WM5100_CLKSRC_SYSCLK: |
| 1523 | snd_soc_update_bits(codec, WM5100_CLOCKING_1, |
| 1524 | WM5100_CLK_32K_SRC_MASK, |
| 1525 | source); |
| 1526 | break; |
| 1527 | default: |
| 1528 | return -EINVAL; |
| 1529 | } |
| 1530 | return 0; |
| 1531 | |
| 1532 | case WM5100_CLK_AIF1: |
| 1533 | case WM5100_CLK_AIF2: |
| 1534 | case WM5100_CLK_AIF3: |
| 1535 | /* Not real clocks, record which clock domain they're in */ |
| 1536 | switch (source) { |
| 1537 | case WM5100_CLKSRC_SYSCLK: |
| 1538 | wm5100->aif_async[clk_id - 1] = false; |
| 1539 | break; |
| 1540 | case WM5100_CLKSRC_ASYNCCLK: |
| 1541 | wm5100->aif_async[clk_id - 1] = true; |
| 1542 | break; |
| 1543 | default: |
| 1544 | dev_err(codec->dev, "Invalid source %d\n", source); |
| 1545 | return -EINVAL; |
| 1546 | } |
| 1547 | return 0; |
| 1548 | |
| 1549 | case WM5100_CLK_OPCLK: |
| 1550 | switch (freq) { |
| 1551 | case 5644800: |
| 1552 | case 6144000: |
| 1553 | snd_soc_update_bits(codec, WM5100_MISC_GPIO_1, |
| 1554 | WM5100_OPCLK_SEL_MASK, 0); |
| 1555 | break; |
| 1556 | case 11289600: |
| 1557 | case 12288000: |
| 1558 | snd_soc_update_bits(codec, WM5100_MISC_GPIO_1, |
| 1559 | WM5100_OPCLK_SEL_MASK, 0); |
| 1560 | break; |
| 1561 | case 22579200: |
| 1562 | case 24576000: |
| 1563 | snd_soc_update_bits(codec, WM5100_MISC_GPIO_1, |
| 1564 | WM5100_OPCLK_SEL_MASK, 0); |
| 1565 | break; |
| 1566 | default: |
| 1567 | dev_err(codec->dev, "Unsupported OPCLK %dHz\n", |
| 1568 | freq); |
| 1569 | return -EINVAL; |
| 1570 | } |
| 1571 | return 0; |
| 1572 | |
| 1573 | default: |
| 1574 | dev_err(codec->dev, "Unknown clock %d\n", clk_id); |
| 1575 | return -EINVAL; |
| 1576 | } |
| 1577 | |
| 1578 | switch (source) { |
| 1579 | case WM5100_CLKSRC_SYSCLK: |
| 1580 | case WM5100_CLKSRC_ASYNCCLK: |
| 1581 | dev_err(codec->dev, "Invalid source %d\n", source); |
| 1582 | return -EINVAL; |
| 1583 | } |
| 1584 | |
| 1585 | switch (freq) { |
| 1586 | case 5644800: |
| 1587 | case 6144000: |
| 1588 | fval = 0; |
| 1589 | break; |
| 1590 | case 11289600: |
| 1591 | case 12288000: |
| 1592 | fval = 1; |
| 1593 | break; |
| 1594 | case 22579200: |
Mark Brown | 11c2b5f | 2011-10-03 21:07:06 +0100 | [diff] [blame] | 1595 | case 24576000: |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1596 | fval = 2; |
| 1597 | break; |
| 1598 | default: |
| 1599 | dev_err(codec->dev, "Invalid clock rate: %d\n", freq); |
| 1600 | return -EINVAL; |
| 1601 | } |
| 1602 | |
| 1603 | switch (freq) { |
| 1604 | case 5644800: |
| 1605 | case 11289600: |
| 1606 | case 22579200: |
| 1607 | audio_rate = 44100; |
| 1608 | break; |
| 1609 | |
| 1610 | case 6144000: |
| 1611 | case 12288000: |
Mark Brown | 11c2b5f | 2011-10-03 21:07:06 +0100 | [diff] [blame] | 1612 | case 24576000: |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1613 | audio_rate = 48000; |
| 1614 | break; |
| 1615 | |
| 1616 | default: |
| 1617 | BUG(); |
| 1618 | audio_rate = 0; |
| 1619 | break; |
| 1620 | } |
| 1621 | |
| 1622 | /* TODO: Check if MCLKs are in use and enable/disable pulls to |
| 1623 | * match. |
| 1624 | */ |
| 1625 | |
| 1626 | snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK | |
| 1627 | WM5100_SYSCLK_SRC_MASK, |
| 1628 | fval << WM5100_SYSCLK_FREQ_SHIFT | source); |
| 1629 | |
| 1630 | /* If this is SYSCLK then configure the clock rate for the |
| 1631 | * internal audio functions to the natural sample rate for |
| 1632 | * this clock rate. |
| 1633 | */ |
| 1634 | if (clk_id == WM5100_CLK_SYSCLK) { |
| 1635 | dev_dbg(codec->dev, "Setting primary audio rate to %dHz", |
| 1636 | audio_rate); |
| 1637 | if (0 && *rate_store) |
| 1638 | wm5100_free_sr(codec, audio_rate); |
| 1639 | ret = wm5100_alloc_sr(codec, audio_rate); |
| 1640 | if (ret != 0) |
| 1641 | dev_warn(codec->dev, "Primary audio slot is %d\n", |
| 1642 | ret); |
| 1643 | } |
| 1644 | |
| 1645 | *rate_store = freq; |
| 1646 | |
| 1647 | return 0; |
| 1648 | } |
| 1649 | |
| 1650 | struct _fll_div { |
| 1651 | u16 fll_fratio; |
| 1652 | u16 fll_outdiv; |
| 1653 | u16 fll_refclk_div; |
| 1654 | u16 n; |
| 1655 | u16 theta; |
| 1656 | u16 lambda; |
| 1657 | }; |
| 1658 | |
| 1659 | static struct { |
| 1660 | unsigned int min; |
| 1661 | unsigned int max; |
| 1662 | u16 fll_fratio; |
| 1663 | int ratio; |
| 1664 | } fll_fratios[] = { |
| 1665 | { 0, 64000, 4, 16 }, |
| 1666 | { 64000, 128000, 3, 8 }, |
| 1667 | { 128000, 256000, 2, 4 }, |
| 1668 | { 256000, 1000000, 1, 2 }, |
| 1669 | { 1000000, 13500000, 0, 1 }, |
| 1670 | }; |
| 1671 | |
| 1672 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, |
| 1673 | unsigned int Fout) |
| 1674 | { |
| 1675 | unsigned int target; |
| 1676 | unsigned int div; |
| 1677 | unsigned int fratio, gcd_fll; |
| 1678 | int i; |
| 1679 | |
| 1680 | /* Fref must be <=13.5MHz */ |
| 1681 | div = 1; |
| 1682 | fll_div->fll_refclk_div = 0; |
| 1683 | while ((Fref / div) > 13500000) { |
| 1684 | div *= 2; |
| 1685 | fll_div->fll_refclk_div++; |
| 1686 | |
| 1687 | if (div > 8) { |
| 1688 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", |
| 1689 | Fref); |
| 1690 | return -EINVAL; |
| 1691 | } |
| 1692 | } |
| 1693 | |
| 1694 | pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); |
| 1695 | |
| 1696 | /* Apply the division for our remaining calculations */ |
| 1697 | Fref /= div; |
| 1698 | |
| 1699 | /* Fvco should be 90-100MHz; don't check the upper bound */ |
| 1700 | div = 2; |
| 1701 | while (Fout * div < 90000000) { |
| 1702 | div++; |
| 1703 | if (div > 64) { |
| 1704 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", |
| 1705 | Fout); |
| 1706 | return -EINVAL; |
| 1707 | } |
| 1708 | } |
| 1709 | target = Fout * div; |
| 1710 | fll_div->fll_outdiv = div - 1; |
| 1711 | |
| 1712 | pr_debug("FLL Fvco=%dHz\n", target); |
| 1713 | |
| 1714 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ |
| 1715 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
| 1716 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { |
| 1717 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; |
| 1718 | fratio = fll_fratios[i].ratio; |
| 1719 | break; |
| 1720 | } |
| 1721 | } |
| 1722 | if (i == ARRAY_SIZE(fll_fratios)) { |
| 1723 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); |
| 1724 | return -EINVAL; |
| 1725 | } |
| 1726 | |
| 1727 | fll_div->n = target / (fratio * Fref); |
| 1728 | |
| 1729 | if (target % Fref == 0) { |
| 1730 | fll_div->theta = 0; |
| 1731 | fll_div->lambda = 0; |
| 1732 | } else { |
| 1733 | gcd_fll = gcd(target, fratio * Fref); |
| 1734 | |
| 1735 | fll_div->theta = (target - (fll_div->n * fratio * Fref)) |
| 1736 | / gcd_fll; |
| 1737 | fll_div->lambda = (fratio * Fref) / gcd_fll; |
| 1738 | } |
| 1739 | |
| 1740 | pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", |
| 1741 | fll_div->n, fll_div->theta, fll_div->lambda); |
| 1742 | pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", |
| 1743 | fll_div->fll_fratio, fratio, fll_div->fll_outdiv, |
| 1744 | fll_div->fll_refclk_div); |
| 1745 | |
| 1746 | return 0; |
| 1747 | } |
| 1748 | |
| 1749 | static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source, |
| 1750 | unsigned int Fref, unsigned int Fout) |
| 1751 | { |
| 1752 | struct i2c_client *i2c = to_i2c_client(codec->dev); |
| 1753 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 1754 | struct _fll_div factors; |
| 1755 | struct wm5100_fll *fll; |
| 1756 | int ret, base, lock, i, timeout; |
| 1757 | |
| 1758 | switch (fll_id) { |
| 1759 | case WM5100_FLL1: |
| 1760 | fll = &wm5100->fll[0]; |
| 1761 | base = WM5100_FLL1_CONTROL_1 - 1; |
| 1762 | lock = WM5100_FLL1_LOCK_STS; |
| 1763 | break; |
| 1764 | case WM5100_FLL2: |
| 1765 | fll = &wm5100->fll[1]; |
| 1766 | base = WM5100_FLL2_CONTROL_2 - 1; |
| 1767 | lock = WM5100_FLL2_LOCK_STS; |
| 1768 | break; |
| 1769 | default: |
| 1770 | dev_err(codec->dev, "Unknown FLL %d\n",fll_id); |
| 1771 | return -EINVAL; |
| 1772 | } |
| 1773 | |
| 1774 | if (!Fout) { |
| 1775 | dev_dbg(codec->dev, "FLL%d disabled", fll_id); |
Mark Brown | 62c1c40 | 2012-01-26 17:28:49 +0000 | [diff] [blame] | 1776 | if (fll->fout) |
| 1777 | pm_runtime_put(codec->dev); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1778 | fll->fout = 0; |
| 1779 | snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0); |
| 1780 | return 0; |
| 1781 | } |
| 1782 | |
| 1783 | switch (source) { |
| 1784 | case WM5100_FLL_SRC_MCLK1: |
| 1785 | case WM5100_FLL_SRC_MCLK2: |
| 1786 | case WM5100_FLL_SRC_FLL1: |
| 1787 | case WM5100_FLL_SRC_FLL2: |
| 1788 | case WM5100_FLL_SRC_AIF1BCLK: |
| 1789 | case WM5100_FLL_SRC_AIF2BCLK: |
| 1790 | case WM5100_FLL_SRC_AIF3BCLK: |
| 1791 | break; |
| 1792 | default: |
| 1793 | dev_err(codec->dev, "Invalid FLL source %d\n", source); |
| 1794 | return -EINVAL; |
| 1795 | } |
| 1796 | |
| 1797 | ret = fll_factors(&factors, Fref, Fout); |
| 1798 | if (ret < 0) |
| 1799 | return ret; |
| 1800 | |
| 1801 | /* Disable the FLL while we reconfigure */ |
| 1802 | snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0); |
| 1803 | |
| 1804 | snd_soc_update_bits(codec, base + 2, |
| 1805 | WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK, |
| 1806 | (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) | |
| 1807 | factors.fll_fratio); |
| 1808 | snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK, |
| 1809 | factors.theta); |
| 1810 | snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n); |
| 1811 | snd_soc_update_bits(codec, base + 6, |
| 1812 | WM5100_FLL1_REFCLK_DIV_MASK | |
| 1813 | WM5100_FLL1_REFCLK_SRC_MASK, |
| 1814 | (factors.fll_refclk_div |
| 1815 | << WM5100_FLL1_REFCLK_DIV_SHIFT) | source); |
| 1816 | snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK, |
| 1817 | factors.lambda); |
| 1818 | |
| 1819 | /* Clear any pending completions */ |
| 1820 | try_wait_for_completion(&fll->lock); |
| 1821 | |
Mark Brown | 62c1c40 | 2012-01-26 17:28:49 +0000 | [diff] [blame] | 1822 | pm_runtime_get_sync(codec->dev); |
| 1823 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1824 | snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA); |
| 1825 | |
| 1826 | if (i2c->irq) |
| 1827 | timeout = 2; |
| 1828 | else |
| 1829 | timeout = 50; |
| 1830 | |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 1831 | snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA, |
| 1832 | WM5100_SYSCLK_ENA); |
| 1833 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1834 | /* Poll for the lock; will use interrupt when we can test */ |
| 1835 | for (i = 0; i < timeout; i++) { |
| 1836 | if (i2c->irq) { |
| 1837 | ret = wait_for_completion_timeout(&fll->lock, |
| 1838 | msecs_to_jiffies(25)); |
| 1839 | if (ret > 0) |
| 1840 | break; |
| 1841 | } else { |
| 1842 | msleep(1); |
| 1843 | } |
| 1844 | |
| 1845 | ret = snd_soc_read(codec, |
| 1846 | WM5100_INTERRUPT_RAW_STATUS_3); |
| 1847 | if (ret < 0) { |
| 1848 | dev_err(codec->dev, |
| 1849 | "Failed to read FLL status: %d\n", |
| 1850 | ret); |
| 1851 | continue; |
| 1852 | } |
| 1853 | if (ret & lock) |
| 1854 | break; |
| 1855 | } |
| 1856 | if (i == timeout) { |
| 1857 | dev_err(codec->dev, "FLL%d lock timed out\n", fll_id); |
Mark Brown | 62c1c40 | 2012-01-26 17:28:49 +0000 | [diff] [blame] | 1858 | pm_runtime_put(codec->dev); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1859 | return -ETIMEDOUT; |
| 1860 | } |
| 1861 | |
| 1862 | fll->src = source; |
| 1863 | fll->fref = Fref; |
| 1864 | fll->fout = Fout; |
| 1865 | |
| 1866 | dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id, |
| 1867 | Fref, Fout); |
| 1868 | |
| 1869 | return 0; |
| 1870 | } |
| 1871 | |
| 1872 | /* Actually go much higher */ |
| 1873 | #define WM5100_RATES SNDRV_PCM_RATE_8000_192000 |
| 1874 | |
| 1875 | #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
| 1876 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 1877 | |
| 1878 | static struct snd_soc_dai_driver wm5100_dai[] = { |
| 1879 | { |
| 1880 | .name = "wm5100-aif1", |
Mark Brown | 9b52312 | 2012-05-01 20:03:52 +0100 | [diff] [blame] | 1881 | .base = WM5100_AUDIO_IF_1_1 - 1, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1882 | .playback = { |
| 1883 | .stream_name = "AIF1 Playback", |
| 1884 | .channels_min = 2, |
| 1885 | .channels_max = 2, |
| 1886 | .rates = WM5100_RATES, |
| 1887 | .formats = WM5100_FORMATS, |
| 1888 | }, |
| 1889 | .capture = { |
| 1890 | .stream_name = "AIF1 Capture", |
| 1891 | .channels_min = 2, |
| 1892 | .channels_max = 2, |
| 1893 | .rates = WM5100_RATES, |
| 1894 | .formats = WM5100_FORMATS, |
| 1895 | }, |
| 1896 | .ops = &wm5100_dai_ops, |
| 1897 | }, |
| 1898 | { |
| 1899 | .name = "wm5100-aif2", |
| 1900 | .id = 1, |
Mark Brown | 9b52312 | 2012-05-01 20:03:52 +0100 | [diff] [blame] | 1901 | .base = WM5100_AUDIO_IF_2_1 - 1, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1902 | .playback = { |
| 1903 | .stream_name = "AIF2 Playback", |
| 1904 | .channels_min = 2, |
| 1905 | .channels_max = 2, |
| 1906 | .rates = WM5100_RATES, |
| 1907 | .formats = WM5100_FORMATS, |
| 1908 | }, |
| 1909 | .capture = { |
| 1910 | .stream_name = "AIF2 Capture", |
| 1911 | .channels_min = 2, |
| 1912 | .channels_max = 2, |
| 1913 | .rates = WM5100_RATES, |
| 1914 | .formats = WM5100_FORMATS, |
| 1915 | }, |
| 1916 | .ops = &wm5100_dai_ops, |
| 1917 | }, |
| 1918 | { |
| 1919 | .name = "wm5100-aif3", |
| 1920 | .id = 2, |
Mark Brown | 9b52312 | 2012-05-01 20:03:52 +0100 | [diff] [blame] | 1921 | .base = WM5100_AUDIO_IF_3_1 - 1, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 1922 | .playback = { |
| 1923 | .stream_name = "AIF3 Playback", |
| 1924 | .channels_min = 2, |
| 1925 | .channels_max = 2, |
| 1926 | .rates = WM5100_RATES, |
| 1927 | .formats = WM5100_FORMATS, |
| 1928 | }, |
| 1929 | .capture = { |
| 1930 | .stream_name = "AIF3 Capture", |
| 1931 | .channels_min = 2, |
| 1932 | .channels_max = 2, |
| 1933 | .rates = WM5100_RATES, |
| 1934 | .formats = WM5100_FORMATS, |
| 1935 | }, |
| 1936 | .ops = &wm5100_dai_ops, |
| 1937 | }, |
| 1938 | }; |
| 1939 | |
| 1940 | static int wm5100_dig_vu[] = { |
| 1941 | WM5100_ADC_DIGITAL_VOLUME_1L, |
| 1942 | WM5100_ADC_DIGITAL_VOLUME_1R, |
| 1943 | WM5100_ADC_DIGITAL_VOLUME_2L, |
| 1944 | WM5100_ADC_DIGITAL_VOLUME_2R, |
| 1945 | WM5100_ADC_DIGITAL_VOLUME_3L, |
| 1946 | WM5100_ADC_DIGITAL_VOLUME_3R, |
| 1947 | WM5100_ADC_DIGITAL_VOLUME_4L, |
| 1948 | WM5100_ADC_DIGITAL_VOLUME_4R, |
| 1949 | |
| 1950 | WM5100_DAC_DIGITAL_VOLUME_1L, |
| 1951 | WM5100_DAC_DIGITAL_VOLUME_1R, |
| 1952 | WM5100_DAC_DIGITAL_VOLUME_2L, |
| 1953 | WM5100_DAC_DIGITAL_VOLUME_2R, |
| 1954 | WM5100_DAC_DIGITAL_VOLUME_3L, |
| 1955 | WM5100_DAC_DIGITAL_VOLUME_3R, |
| 1956 | WM5100_DAC_DIGITAL_VOLUME_4L, |
| 1957 | WM5100_DAC_DIGITAL_VOLUME_4R, |
| 1958 | WM5100_DAC_DIGITAL_VOLUME_5L, |
| 1959 | WM5100_DAC_DIGITAL_VOLUME_5R, |
| 1960 | WM5100_DAC_DIGITAL_VOLUME_6L, |
| 1961 | WM5100_DAC_DIGITAL_VOLUME_6R, |
| 1962 | }; |
| 1963 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 1964 | static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode) |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 1965 | { |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 1966 | struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode]; |
| 1967 | |
| 1968 | BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes)); |
| 1969 | |
| 1970 | gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol); |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 1971 | regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1, |
| 1972 | WM5100_ACCDET_BIAS_SRC_MASK | |
| 1973 | WM5100_ACCDET_SRC, |
| 1974 | (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) | |
| 1975 | mode->micd_src << WM5100_ACCDET_SRC_SHIFT); |
| 1976 | regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL, |
| 1977 | WM5100_HPCOM_SRC, |
| 1978 | mode->micd_src << WM5100_HPCOM_SRC_SHIFT); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 1979 | |
| 1980 | wm5100->jack_mode = the_mode; |
| 1981 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 1982 | dev_dbg(wm5100->dev, "Set microphone polarity to %d\n", |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 1983 | wm5100->jack_mode); |
| 1984 | } |
| 1985 | |
Mark Brown | 2633f73 | 2012-01-26 17:43:09 +0000 | [diff] [blame] | 1986 | static void wm5100_report_headphone(struct wm5100_priv *wm5100) |
| 1987 | { |
| 1988 | dev_dbg(wm5100->dev, "Headphone detected\n"); |
| 1989 | wm5100->jack_detecting = false; |
| 1990 | snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE, |
| 1991 | SND_JACK_HEADPHONE); |
| 1992 | |
| 1993 | /* Increase the detection rate a bit for responsiveness. */ |
| 1994 | regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1, |
| 1995 | WM5100_ACCDET_RATE_MASK, |
| 1996 | 7 << WM5100_ACCDET_RATE_SHIFT); |
| 1997 | } |
| 1998 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 1999 | static void wm5100_micd_irq(struct wm5100_priv *wm5100) |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2000 | { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2001 | unsigned int val; |
| 2002 | int ret; |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2003 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2004 | ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val); |
| 2005 | if (ret != 0) { |
| 2006 | dev_err(wm5100->dev, "Failed to read micropone status: %d\n", |
| 2007 | ret); |
| 2008 | return; |
| 2009 | } |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2010 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2011 | dev_dbg(wm5100->dev, "Microphone event: %x\n", val); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2012 | |
| 2013 | if (!(val & WM5100_ACCDET_VALID)) { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2014 | dev_warn(wm5100->dev, "Microphone detection state invalid\n"); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2015 | return; |
| 2016 | } |
| 2017 | |
| 2018 | /* No accessory, reset everything and report removal */ |
| 2019 | if (!(val & WM5100_ACCDET_STS)) { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2020 | dev_dbg(wm5100->dev, "Jack removal detected\n"); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2021 | wm5100->jack_mic = false; |
| 2022 | wm5100->jack_detecting = true; |
Mark Brown | 2633f73 | 2012-01-26 17:43:09 +0000 | [diff] [blame] | 2023 | wm5100->jack_flips = 0; |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2024 | snd_soc_jack_report(wm5100->jack, 0, |
| 2025 | SND_JACK_LINEOUT | SND_JACK_HEADSET | |
| 2026 | SND_JACK_BTN_0); |
| 2027 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2028 | regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1, |
| 2029 | WM5100_ACCDET_RATE_MASK, |
| 2030 | WM5100_ACCDET_RATE_MASK); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2031 | return; |
| 2032 | } |
| 2033 | |
| 2034 | /* If the measurement is very high we've got a microphone, |
| 2035 | * either we just detected one or if we already reported then |
| 2036 | * we've got a button release event. |
| 2037 | */ |
| 2038 | if (val & 0x400) { |
| 2039 | if (wm5100->jack_detecting) { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2040 | dev_dbg(wm5100->dev, "Microphone detected\n"); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2041 | wm5100->jack_mic = true; |
Mark Brown | 9fb8352 | 2012-01-25 15:19:20 +0000 | [diff] [blame] | 2042 | wm5100->jack_detecting = false; |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2043 | snd_soc_jack_report(wm5100->jack, |
| 2044 | SND_JACK_HEADSET, |
| 2045 | SND_JACK_HEADSET | SND_JACK_BTN_0); |
| 2046 | |
| 2047 | /* Increase poll rate to give better responsiveness |
| 2048 | * for buttons */ |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2049 | regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1, |
| 2050 | WM5100_ACCDET_RATE_MASK, |
| 2051 | 5 << WM5100_ACCDET_RATE_SHIFT); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2052 | } else { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2053 | dev_dbg(wm5100->dev, "Mic button up\n"); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2054 | snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0); |
| 2055 | } |
| 2056 | |
| 2057 | return; |
| 2058 | } |
| 2059 | |
| 2060 | /* If we detected a lower impedence during initial startup |
| 2061 | * then we probably have the wrong polarity, flip it. Don't |
| 2062 | * do this for the lowest impedences to speed up detection of |
Mark Brown | 2633f73 | 2012-01-26 17:43:09 +0000 | [diff] [blame] | 2063 | * plain headphones and give up if neither polarity looks |
| 2064 | * sensible. |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2065 | */ |
| 2066 | if (wm5100->jack_detecting && (val & 0x3f8)) { |
Mark Brown | 2633f73 | 2012-01-26 17:43:09 +0000 | [diff] [blame] | 2067 | wm5100->jack_flips++; |
| 2068 | |
| 2069 | if (wm5100->jack_flips > 1) |
| 2070 | wm5100_report_headphone(wm5100); |
| 2071 | else |
| 2072 | wm5100_set_detect_mode(wm5100, !wm5100->jack_mode); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2073 | |
| 2074 | return; |
| 2075 | } |
| 2076 | |
| 2077 | /* Don't distinguish between buttons, just report any low |
| 2078 | * impedence as BTN_0. |
| 2079 | */ |
| 2080 | if (val & 0x3fc) { |
| 2081 | if (wm5100->jack_mic) { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2082 | dev_dbg(wm5100->dev, "Mic button detected\n"); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2083 | snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0, |
| 2084 | SND_JACK_BTN_0); |
| 2085 | } else if (wm5100->jack_detecting) { |
Mark Brown | 2633f73 | 2012-01-26 17:43:09 +0000 | [diff] [blame] | 2086 | wm5100_report_headphone(wm5100); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2087 | } |
| 2088 | } |
| 2089 | } |
| 2090 | |
| 2091 | int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) |
| 2092 | { |
| 2093 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 2094 | |
| 2095 | if (jack) { |
| 2096 | wm5100->jack = jack; |
| 2097 | wm5100->jack_detecting = true; |
Mark Brown | 2633f73 | 2012-01-26 17:43:09 +0000 | [diff] [blame] | 2098 | wm5100->jack_flips = 0; |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2099 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2100 | wm5100_set_detect_mode(wm5100, 0); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2101 | |
| 2102 | /* Slowest detection rate, gives debounce for initial |
| 2103 | * detection */ |
| 2104 | snd_soc_update_bits(codec, WM5100_MIC_DETECT_1, |
| 2105 | WM5100_ACCDET_BIAS_STARTTIME_MASK | |
| 2106 | WM5100_ACCDET_RATE_MASK, |
| 2107 | (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) | |
| 2108 | WM5100_ACCDET_RATE_MASK); |
| 2109 | |
| 2110 | /* We need the charge pump to power MICBIAS */ |
| 2111 | snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2"); |
| 2112 | snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); |
| 2113 | snd_soc_dapm_sync(&codec->dapm); |
| 2114 | |
| 2115 | /* We start off just enabling microphone detection - even a |
| 2116 | * plain headphone will trigger detection. |
| 2117 | */ |
| 2118 | snd_soc_update_bits(codec, WM5100_MIC_DETECT_1, |
| 2119 | WM5100_ACCDET_ENA, WM5100_ACCDET_ENA); |
| 2120 | |
| 2121 | snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK, |
| 2122 | WM5100_IM_ACCDET_EINT, 0); |
| 2123 | } else { |
| 2124 | snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK, |
| 2125 | WM5100_IM_HPDET_EINT | |
| 2126 | WM5100_IM_ACCDET_EINT, |
| 2127 | WM5100_IM_HPDET_EINT | |
| 2128 | WM5100_IM_ACCDET_EINT); |
| 2129 | snd_soc_update_bits(codec, WM5100_MIC_DETECT_1, |
| 2130 | WM5100_ACCDET_ENA, 0); |
| 2131 | wm5100->jack = NULL; |
| 2132 | } |
| 2133 | |
| 2134 | return 0; |
| 2135 | } |
| 2136 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2137 | static irqreturn_t wm5100_irq(int irq, void *data) |
| 2138 | { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2139 | struct wm5100_priv *wm5100 = data; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2140 | irqreturn_t status = IRQ_NONE; |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2141 | unsigned int irq_val, mask_val; |
| 2142 | int ret; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2143 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2144 | ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val); |
| 2145 | if (ret < 0) { |
| 2146 | dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n", |
| 2147 | ret); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2148 | irq_val = 0; |
| 2149 | } |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2150 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2151 | ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK, |
| 2152 | &mask_val); |
| 2153 | if (ret < 0) { |
| 2154 | dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n", |
| 2155 | ret); |
| 2156 | mask_val = 0xffff; |
| 2157 | } |
| 2158 | |
| 2159 | irq_val &= ~mask_val; |
| 2160 | |
| 2161 | regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2162 | |
| 2163 | if (irq_val) |
| 2164 | status = IRQ_HANDLED; |
| 2165 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2166 | wm5100_log_status3(wm5100, irq_val); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2167 | |
| 2168 | if (irq_val & WM5100_FLL1_LOCK_EINT) { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2169 | dev_dbg(wm5100->dev, "FLL1 locked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2170 | complete(&wm5100->fll[0].lock); |
| 2171 | } |
| 2172 | if (irq_val & WM5100_FLL2_LOCK_EINT) { |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2173 | dev_dbg(wm5100->dev, "FLL2 locked\n"); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2174 | complete(&wm5100->fll[1].lock); |
| 2175 | } |
| 2176 | |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2177 | if (irq_val & WM5100_ACCDET_EINT) |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2178 | wm5100_micd_irq(wm5100); |
Mark Brown | ba896ed | 2011-09-27 17:39:50 +0100 | [diff] [blame] | 2179 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2180 | ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val); |
| 2181 | if (ret < 0) { |
| 2182 | dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n", |
| 2183 | ret); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2184 | irq_val = 0; |
| 2185 | } |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2186 | |
| 2187 | ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK, |
| 2188 | &mask_val); |
| 2189 | if (ret < 0) { |
| 2190 | dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n", |
| 2191 | ret); |
| 2192 | mask_val = 0xffff; |
| 2193 | } |
| 2194 | |
| 2195 | irq_val &= ~mask_val; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2196 | |
| 2197 | if (irq_val) |
| 2198 | status = IRQ_HANDLED; |
| 2199 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2200 | regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2201 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2202 | wm5100_log_status4(wm5100, irq_val); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2203 | |
| 2204 | return status; |
| 2205 | } |
| 2206 | |
| 2207 | static irqreturn_t wm5100_edge_irq(int irq, void *data) |
| 2208 | { |
| 2209 | irqreturn_t ret = IRQ_NONE; |
| 2210 | irqreturn_t val; |
| 2211 | |
| 2212 | do { |
| 2213 | val = wm5100_irq(irq, data); |
| 2214 | if (val != IRQ_NONE) |
| 2215 | ret = val; |
| 2216 | } while (val != IRQ_NONE); |
| 2217 | |
| 2218 | return ret; |
| 2219 | } |
| 2220 | |
| 2221 | #ifdef CONFIG_GPIOLIB |
| 2222 | static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip) |
| 2223 | { |
| 2224 | return container_of(chip, struct wm5100_priv, gpio_chip); |
| 2225 | } |
| 2226 | |
| 2227 | static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 2228 | { |
| 2229 | struct wm5100_priv *wm5100 = gpio_to_wm5100(chip); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2230 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2231 | regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, |
| 2232 | WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2233 | } |
| 2234 | |
| 2235 | static int wm5100_gpio_direction_out(struct gpio_chip *chip, |
| 2236 | unsigned offset, int value) |
| 2237 | { |
| 2238 | struct wm5100_priv *wm5100 = gpio_to_wm5100(chip); |
Mark Brown | 64964e8 | 2011-10-31 19:02:13 +0000 | [diff] [blame] | 2239 | int val, ret; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2240 | |
| 2241 | val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT); |
| 2242 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2243 | ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, |
| 2244 | WM5100_GP1_FN_MASK | WM5100_GP1_DIR | |
| 2245 | WM5100_GP1_LVL, val); |
Mark Brown | 64964e8 | 2011-10-31 19:02:13 +0000 | [diff] [blame] | 2246 | if (ret < 0) |
| 2247 | return ret; |
| 2248 | else |
| 2249 | return 0; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2250 | } |
| 2251 | |
| 2252 | static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 2253 | { |
| 2254 | struct wm5100_priv *wm5100 = gpio_to_wm5100(chip); |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2255 | unsigned int reg; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2256 | int ret; |
| 2257 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2258 | ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, ®); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2259 | if (ret < 0) |
| 2260 | return ret; |
| 2261 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2262 | return (reg & WM5100_GP1_LVL) != 0; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2263 | } |
| 2264 | |
| 2265 | static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset) |
| 2266 | { |
| 2267 | struct wm5100_priv *wm5100 = gpio_to_wm5100(chip); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2268 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2269 | return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, |
| 2270 | WM5100_GP1_FN_MASK | WM5100_GP1_DIR, |
| 2271 | (1 << WM5100_GP1_FN_SHIFT) | |
| 2272 | (1 << WM5100_GP1_DIR_SHIFT)); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2273 | } |
| 2274 | |
| 2275 | static struct gpio_chip wm5100_template_chip = { |
| 2276 | .label = "wm5100", |
| 2277 | .owner = THIS_MODULE, |
| 2278 | .direction_output = wm5100_gpio_direction_out, |
| 2279 | .set = wm5100_gpio_set, |
| 2280 | .direction_input = wm5100_gpio_direction_in, |
| 2281 | .get = wm5100_gpio_get, |
| 2282 | .can_sleep = 1, |
| 2283 | }; |
| 2284 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2285 | static void wm5100_init_gpio(struct i2c_client *i2c) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2286 | { |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2287 | struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2288 | int ret; |
| 2289 | |
| 2290 | wm5100->gpio_chip = wm5100_template_chip; |
| 2291 | wm5100->gpio_chip.ngpio = 6; |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2292 | wm5100->gpio_chip.dev = &i2c->dev; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2293 | |
| 2294 | if (wm5100->pdata.gpio_base) |
| 2295 | wm5100->gpio_chip.base = wm5100->pdata.gpio_base; |
| 2296 | else |
| 2297 | wm5100->gpio_chip.base = -1; |
| 2298 | |
| 2299 | ret = gpiochip_add(&wm5100->gpio_chip); |
| 2300 | if (ret != 0) |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2301 | dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2302 | } |
| 2303 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2304 | static void wm5100_free_gpio(struct i2c_client *i2c) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2305 | { |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2306 | struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2307 | int ret; |
| 2308 | |
| 2309 | ret = gpiochip_remove(&wm5100->gpio_chip); |
| 2310 | if (ret != 0) |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2311 | dev_err(&i2c->dev, "Failed to remove GPIOs: %d\n", ret); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2312 | } |
| 2313 | #else |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2314 | static void wm5100_init_gpio(struct i2c_client *i2c) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2315 | { |
| 2316 | } |
| 2317 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2318 | static void wm5100_free_gpio(struct i2c_client *i2c) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2319 | { |
| 2320 | } |
| 2321 | #endif |
| 2322 | |
| 2323 | static int wm5100_probe(struct snd_soc_codec *codec) |
| 2324 | { |
| 2325 | struct i2c_client *i2c = to_i2c_client(codec->dev); |
| 2326 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2327 | int ret, i; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2328 | |
| 2329 | wm5100->codec = codec; |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2330 | codec->control_data = wm5100->regmap; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2331 | |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2332 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2333 | if (ret != 0) { |
| 2334 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
| 2335 | return ret; |
| 2336 | } |
| 2337 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2338 | for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++) |
| 2339 | snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU, |
| 2340 | WM5100_OUT_VU); |
| 2341 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2342 | /* Don't debounce interrupts to support use of SYSCLK only */ |
| 2343 | snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0); |
| 2344 | snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0); |
| 2345 | |
| 2346 | /* TODO: check if we're symmetric */ |
| 2347 | |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2348 | if (i2c->irq) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2349 | snd_soc_dapm_new_controls(&codec->dapm, |
| 2350 | wm5100_dapm_widgets_noirq, |
| 2351 | ARRAY_SIZE(wm5100_dapm_widgets_noirq)); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2352 | |
| 2353 | if (wm5100->pdata.hp_pol) { |
| 2354 | ret = gpio_request_one(wm5100->pdata.hp_pol, |
| 2355 | GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL"); |
| 2356 | if (ret < 0) { |
| 2357 | dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n", |
| 2358 | wm5100->pdata.hp_pol, ret); |
| 2359 | goto err_gpio; |
| 2360 | } |
| 2361 | } |
| 2362 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2363 | return 0; |
| 2364 | |
| 2365 | err_gpio: |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2366 | |
| 2367 | return ret; |
| 2368 | } |
| 2369 | |
| 2370 | static int wm5100_remove(struct snd_soc_codec *codec) |
| 2371 | { |
| 2372 | struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec); |
| 2373 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2374 | if (wm5100->pdata.hp_pol) { |
| 2375 | gpio_free(wm5100->pdata.hp_pol); |
| 2376 | } |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2377 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2378 | return 0; |
| 2379 | } |
| 2380 | |
| 2381 | static struct snd_soc_codec_driver soc_codec_dev_wm5100 = { |
| 2382 | .probe = wm5100_probe, |
| 2383 | .remove = wm5100_remove, |
| 2384 | |
| 2385 | .set_sysclk = wm5100_set_sysclk, |
| 2386 | .set_pll = wm5100_set_fll, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2387 | .idle_bias_off = 1, |
| 2388 | |
| 2389 | .seq_notifier = wm5100_seq_notifier, |
| 2390 | .controls = wm5100_snd_controls, |
| 2391 | .num_controls = ARRAY_SIZE(wm5100_snd_controls), |
| 2392 | .dapm_widgets = wm5100_dapm_widgets, |
| 2393 | .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets), |
| 2394 | .dapm_routes = wm5100_dapm_routes, |
| 2395 | .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes), |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2396 | }; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2397 | |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2398 | static const struct regmap_config wm5100_regmap = { |
| 2399 | .reg_bits = 16, |
| 2400 | .val_bits = 16, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2401 | |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2402 | .max_register = WM5100_MAX_REGISTER, |
| 2403 | .reg_defaults = wm5100_reg_defaults, |
| 2404 | .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults), |
| 2405 | .volatile_reg = wm5100_volatile_register, |
| 2406 | .readable_reg = wm5100_readable_register, |
| 2407 | .cache_type = REGCACHE_RBTREE, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2408 | }; |
| 2409 | |
Mark Brown | a188fcb | 2012-01-25 17:57:16 +0000 | [diff] [blame] | 2410 | static const unsigned int wm5100_mic_ctrl_reg[] = { |
| 2411 | WM5100_IN1L_CONTROL, |
| 2412 | WM5100_IN2L_CONTROL, |
| 2413 | WM5100_IN3L_CONTROL, |
| 2414 | WM5100_IN4L_CONTROL, |
| 2415 | }; |
| 2416 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2417 | static __devinit int wm5100_i2c_probe(struct i2c_client *i2c, |
| 2418 | const struct i2c_device_id *id) |
| 2419 | { |
| 2420 | struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev); |
| 2421 | struct wm5100_priv *wm5100; |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2422 | unsigned int reg; |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2423 | int ret, i, irq_flags; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2424 | |
Mark Brown | a81b82c | 2011-11-24 18:28:51 +0000 | [diff] [blame] | 2425 | wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv), |
| 2426 | GFP_KERNEL); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2427 | if (wm5100 == NULL) |
| 2428 | return -ENOMEM; |
| 2429 | |
Mark Brown | 46c1a877 | 2012-01-18 14:53:08 +0000 | [diff] [blame] | 2430 | wm5100->dev = &i2c->dev; |
| 2431 | |
Mark Brown | 77caaba | 2012-01-30 20:01:53 +0000 | [diff] [blame] | 2432 | wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap); |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2433 | if (IS_ERR(wm5100->regmap)) { |
| 2434 | ret = PTR_ERR(wm5100->regmap); |
| 2435 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", |
| 2436 | ret); |
Mark Brown | a81b82c | 2011-11-24 18:28:51 +0000 | [diff] [blame] | 2437 | goto err; |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2438 | } |
| 2439 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2440 | for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++) |
| 2441 | init_completion(&wm5100->fll[i].lock); |
| 2442 | |
| 2443 | if (pdata) |
| 2444 | wm5100->pdata = *pdata; |
| 2445 | |
| 2446 | i2c_set_clientdata(i2c, wm5100); |
| 2447 | |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2448 | for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++) |
| 2449 | wm5100->core_supplies[i].supply = wm5100_core_supply_names[i]; |
| 2450 | |
Mark Brown | 17e3e57 | 2012-01-23 15:00:17 +0000 | [diff] [blame] | 2451 | ret = devm_regulator_bulk_get(&i2c->dev, |
| 2452 | ARRAY_SIZE(wm5100->core_supplies), |
| 2453 | wm5100->core_supplies); |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2454 | if (ret != 0) { |
| 2455 | dev_err(&i2c->dev, "Failed to request core supplies: %d\n", |
| 2456 | ret); |
Mark Brown | 77caaba | 2012-01-30 20:01:53 +0000 | [diff] [blame] | 2457 | goto err; |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2458 | } |
| 2459 | |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2460 | ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies), |
| 2461 | wm5100->core_supplies); |
| 2462 | if (ret != 0) { |
| 2463 | dev_err(&i2c->dev, "Failed to enable core supplies: %d\n", |
| 2464 | ret); |
Mark Brown | 77caaba | 2012-01-30 20:01:53 +0000 | [diff] [blame] | 2465 | goto err; |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2466 | } |
| 2467 | |
| 2468 | if (wm5100->pdata.ldo_ena) { |
| 2469 | ret = gpio_request_one(wm5100->pdata.ldo_ena, |
| 2470 | GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA"); |
| 2471 | if (ret < 0) { |
| 2472 | dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n", |
| 2473 | wm5100->pdata.ldo_ena, ret); |
| 2474 | goto err_enable; |
| 2475 | } |
| 2476 | msleep(2); |
| 2477 | } |
| 2478 | |
| 2479 | if (wm5100->pdata.reset) { |
| 2480 | ret = gpio_request_one(wm5100->pdata.reset, |
| 2481 | GPIOF_OUT_INIT_HIGH, "WM5100 /RESET"); |
| 2482 | if (ret < 0) { |
| 2483 | dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n", |
| 2484 | wm5100->pdata.reset, ret); |
| 2485 | goto err_ldo; |
| 2486 | } |
| 2487 | } |
| 2488 | |
| 2489 | ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, ®); |
| 2490 | if (ret < 0) { |
Mark Brown | 0132615 | 2012-01-17 19:27:04 +0000 | [diff] [blame] | 2491 | dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2492 | goto err_reset; |
| 2493 | } |
| 2494 | switch (reg) { |
| 2495 | case 0x8997: |
| 2496 | case 0x5100: |
| 2497 | break; |
| 2498 | |
| 2499 | default: |
| 2500 | dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg); |
| 2501 | ret = -EINVAL; |
| 2502 | goto err_reset; |
| 2503 | } |
| 2504 | |
| 2505 | ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, ®); |
| 2506 | if (ret < 0) { |
| 2507 | dev_err(&i2c->dev, "Failed to read revision register\n"); |
| 2508 | goto err_reset; |
| 2509 | } |
| 2510 | wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK; |
| 2511 | |
| 2512 | dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A'); |
| 2513 | |
| 2514 | ret = wm5100_reset(wm5100); |
| 2515 | if (ret < 0) { |
| 2516 | dev_err(&i2c->dev, "Failed to issue reset\n"); |
| 2517 | goto err_reset; |
| 2518 | } |
| 2519 | |
Mark Brown | 15b52f1 | 2012-01-21 12:14:53 +0000 | [diff] [blame] | 2520 | switch (wm5100->rev) { |
| 2521 | case 0: |
| 2522 | ret = regmap_register_patch(wm5100->regmap, |
| 2523 | wm5100_reva_patches, |
| 2524 | ARRAY_SIZE(wm5100_reva_patches)); |
| 2525 | if (ret != 0) { |
| 2526 | dev_err(&i2c->dev, "Failed to register patches: %d\n", |
| 2527 | ret); |
| 2528 | goto err_reset; |
| 2529 | } |
| 2530 | break; |
| 2531 | default: |
| 2532 | break; |
| 2533 | } |
| 2534 | |
| 2535 | |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2536 | wm5100_init_gpio(i2c); |
| 2537 | |
Mark Brown | d9b5e9c | 2011-11-10 16:14:04 +0000 | [diff] [blame] | 2538 | for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) { |
| 2539 | if (!wm5100->pdata.gpio_defaults[i]) |
| 2540 | continue; |
| 2541 | |
| 2542 | regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i, |
| 2543 | wm5100->pdata.gpio_defaults[i]); |
| 2544 | } |
| 2545 | |
| 2546 | for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) { |
Mark Brown | a188fcb | 2012-01-25 17:57:16 +0000 | [diff] [blame] | 2547 | regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i], |
Mark Brown | d9b5e9c | 2011-11-10 16:14:04 +0000 | [diff] [blame] | 2548 | WM5100_IN1_MODE_MASK | |
| 2549 | WM5100_IN1_DMIC_SUP_MASK, |
| 2550 | (wm5100->pdata.in_mode[i] << |
| 2551 | WM5100_IN1_MODE_SHIFT) | |
| 2552 | (wm5100->pdata.dmic_sup[i] << |
| 2553 | WM5100_IN1_DMIC_SUP_SHIFT)); |
| 2554 | } |
| 2555 | |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2556 | if (i2c->irq) { |
| 2557 | if (wm5100->pdata.irq_flags) |
| 2558 | irq_flags = wm5100->pdata.irq_flags; |
| 2559 | else |
| 2560 | irq_flags = IRQF_TRIGGER_LOW; |
| 2561 | |
| 2562 | irq_flags |= IRQF_ONESHOT; |
| 2563 | |
| 2564 | if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) |
| 2565 | ret = request_threaded_irq(i2c->irq, NULL, |
| 2566 | wm5100_edge_irq, irq_flags, |
| 2567 | "wm5100", wm5100); |
| 2568 | else |
| 2569 | ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq, |
| 2570 | irq_flags, "wm5100", |
| 2571 | wm5100); |
| 2572 | |
| 2573 | if (ret != 0) { |
| 2574 | dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n", |
| 2575 | i2c->irq, ret); |
| 2576 | } else { |
| 2577 | /* Enable default interrupts */ |
| 2578 | regmap_update_bits(wm5100->regmap, |
| 2579 | WM5100_INTERRUPT_STATUS_3_MASK, |
| 2580 | WM5100_IM_SPK_SHUTDOWN_WARN_EINT | |
| 2581 | WM5100_IM_SPK_SHUTDOWN_EINT | |
| 2582 | WM5100_IM_ASRC2_LOCK_EINT | |
| 2583 | WM5100_IM_ASRC1_LOCK_EINT | |
| 2584 | WM5100_IM_FLL2_LOCK_EINT | |
| 2585 | WM5100_IM_FLL1_LOCK_EINT | |
| 2586 | WM5100_CLKGEN_ERR_EINT | |
| 2587 | WM5100_CLKGEN_ERR_ASYNC_EINT, 0); |
| 2588 | |
| 2589 | regmap_update_bits(wm5100->regmap, |
| 2590 | WM5100_INTERRUPT_STATUS_4_MASK, |
| 2591 | WM5100_AIF3_ERR_EINT | |
| 2592 | WM5100_AIF2_ERR_EINT | |
| 2593 | WM5100_AIF1_ERR_EINT | |
| 2594 | WM5100_CTRLIF_ERR_EINT | |
| 2595 | WM5100_ISRC2_UNDERCLOCKED_EINT | |
| 2596 | WM5100_ISRC1_UNDERCLOCKED_EINT | |
| 2597 | WM5100_FX_UNDERCLOCKED_EINT | |
| 2598 | WM5100_AIF3_UNDERCLOCKED_EINT | |
| 2599 | WM5100_AIF2_UNDERCLOCKED_EINT | |
| 2600 | WM5100_AIF1_UNDERCLOCKED_EINT | |
| 2601 | WM5100_ASRC_UNDERCLOCKED_EINT | |
| 2602 | WM5100_DAC_UNDERCLOCKED_EINT | |
| 2603 | WM5100_ADC_UNDERCLOCKED_EINT | |
| 2604 | WM5100_MIXER_UNDERCLOCKED_EINT, 0); |
| 2605 | } |
| 2606 | } |
| 2607 | |
Mark Brown | 62c1c40 | 2012-01-26 17:28:49 +0000 | [diff] [blame] | 2608 | pm_runtime_set_active(&i2c->dev); |
| 2609 | pm_runtime_enable(&i2c->dev); |
| 2610 | pm_request_idle(&i2c->dev); |
| 2611 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2612 | ret = snd_soc_register_codec(&i2c->dev, |
| 2613 | &soc_codec_dev_wm5100, wm5100_dai, |
| 2614 | ARRAY_SIZE(wm5100_dai)); |
| 2615 | if (ret < 0) { |
| 2616 | dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret); |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2617 | goto err_reset; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2618 | } |
| 2619 | |
| 2620 | return ret; |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2621 | |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2622 | err_reset: |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2623 | if (i2c->irq) |
| 2624 | free_irq(i2c->irq, wm5100); |
Mark Brown | 9db16e4 | 2011-11-09 17:27:28 +0000 | [diff] [blame] | 2625 | wm5100_free_gpio(i2c); |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2626 | if (wm5100->pdata.reset) { |
Mark Brown | 2688738 | 2012-01-17 19:18:27 +0000 | [diff] [blame] | 2627 | gpio_set_value_cansleep(wm5100->pdata.reset, 0); |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2628 | gpio_free(wm5100->pdata.reset); |
| 2629 | } |
| 2630 | err_ldo: |
| 2631 | if (wm5100->pdata.ldo_ena) { |
| 2632 | gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0); |
| 2633 | gpio_free(wm5100->pdata.ldo_ena); |
| 2634 | } |
| 2635 | err_enable: |
| 2636 | regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies), |
| 2637 | wm5100->core_supplies); |
Mark Brown | a81b82c | 2011-11-24 18:28:51 +0000 | [diff] [blame] | 2638 | err: |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2639 | return ret; |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2640 | } |
| 2641 | |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2642 | static __devexit int wm5100_i2c_remove(struct i2c_client *i2c) |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2643 | { |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2644 | struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c); |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2645 | |
Mark Brown | 09452f2 | 2012-01-18 15:05:46 +0000 | [diff] [blame] | 2646 | snd_soc_unregister_codec(&i2c->dev); |
| 2647 | if (i2c->irq) |
| 2648 | free_irq(i2c->irq, wm5100); |
| 2649 | wm5100_free_gpio(i2c); |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2650 | if (wm5100->pdata.reset) { |
Mark Brown | 2688738 | 2012-01-17 19:18:27 +0000 | [diff] [blame] | 2651 | gpio_set_value_cansleep(wm5100->pdata.reset, 0); |
Mark Brown | 588ac5e | 2011-11-09 16:12:04 +0000 | [diff] [blame] | 2652 | gpio_free(wm5100->pdata.reset); |
| 2653 | } |
| 2654 | if (wm5100->pdata.ldo_ena) { |
| 2655 | gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0); |
| 2656 | gpio_free(wm5100->pdata.ldo_ena); |
| 2657 | } |
Mark Brown | bd132ec | 2011-10-23 11:10:45 +0100 | [diff] [blame] | 2658 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2659 | return 0; |
| 2660 | } |
| 2661 | |
Mark Brown | 62c1c40 | 2012-01-26 17:28:49 +0000 | [diff] [blame] | 2662 | #ifdef CONFIG_PM_RUNTIME |
| 2663 | static int wm5100_runtime_suspend(struct device *dev) |
| 2664 | { |
| 2665 | struct wm5100_priv *wm5100 = dev_get_drvdata(dev); |
| 2666 | |
| 2667 | regcache_cache_only(wm5100->regmap, true); |
| 2668 | regcache_mark_dirty(wm5100->regmap); |
| 2669 | if (wm5100->pdata.ldo_ena) |
| 2670 | gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0); |
| 2671 | regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies), |
| 2672 | wm5100->core_supplies); |
| 2673 | |
| 2674 | return 0; |
| 2675 | } |
| 2676 | |
| 2677 | static int wm5100_runtime_resume(struct device *dev) |
| 2678 | { |
| 2679 | struct wm5100_priv *wm5100 = dev_get_drvdata(dev); |
| 2680 | int ret; |
| 2681 | |
| 2682 | ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies), |
| 2683 | wm5100->core_supplies); |
| 2684 | if (ret != 0) { |
| 2685 | dev_err(dev, "Failed to enable supplies: %d\n", |
| 2686 | ret); |
| 2687 | return ret; |
| 2688 | } |
| 2689 | |
| 2690 | if (wm5100->pdata.ldo_ena) { |
| 2691 | gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1); |
| 2692 | msleep(2); |
| 2693 | } |
| 2694 | |
| 2695 | regcache_cache_only(wm5100->regmap, false); |
| 2696 | regcache_sync(wm5100->regmap); |
| 2697 | |
| 2698 | return 0; |
| 2699 | } |
| 2700 | #endif |
| 2701 | |
| 2702 | static struct dev_pm_ops wm5100_pm = { |
| 2703 | SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume, |
| 2704 | NULL) |
| 2705 | }; |
| 2706 | |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2707 | static const struct i2c_device_id wm5100_i2c_id[] = { |
| 2708 | { "wm5100", 0 }, |
| 2709 | { } |
| 2710 | }; |
| 2711 | MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id); |
| 2712 | |
| 2713 | static struct i2c_driver wm5100_i2c_driver = { |
| 2714 | .driver = { |
| 2715 | .name = "wm5100", |
| 2716 | .owner = THIS_MODULE, |
Mark Brown | 62c1c40 | 2012-01-26 17:28:49 +0000 | [diff] [blame] | 2717 | .pm = &wm5100_pm, |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2718 | }, |
| 2719 | .probe = wm5100_i2c_probe, |
| 2720 | .remove = __devexit_p(wm5100_i2c_remove), |
| 2721 | .id_table = wm5100_i2c_id, |
| 2722 | }; |
| 2723 | |
Mark Brown | d564407 | 2012-05-12 13:00:29 +0100 | [diff] [blame] | 2724 | module_i2c_driver(wm5100_i2c_driver); |
Mark Brown | 6d4baf0 | 2011-09-20 15:44:21 +0100 | [diff] [blame] | 2725 | |
| 2726 | MODULE_DESCRIPTION("ASoC WM5100 driver"); |
| 2727 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); |
| 2728 | MODULE_LICENSE("GPL"); |