Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * wm8400.c -- WM8400 ALSA Soc Audio driver |
| 3 | * |
Mark Brown | 656baae | 2012-05-23 12:39:07 +0100 | [diff] [blame] | 4 | * Copyright 2008-11 Wolfson Microelectronics PLC. |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 5 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/moduleparam.h> |
| 16 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 17 | #include <linux/slab.h> |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 18 | #include <linux/init.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/pm.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/regulator/consumer.h> |
| 23 | #include <linux/mfd/wm8400-audio.h> |
| 24 | #include <linux/mfd/wm8400-private.h> |
Andres Salomon | dab1547 | 2011-02-17 19:07:27 -0800 | [diff] [blame] | 25 | #include <linux/mfd/core.h> |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 26 | #include <sound/core.h> |
| 27 | #include <sound/pcm.h> |
| 28 | #include <sound/pcm_params.h> |
| 29 | #include <sound/soc.h> |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 30 | #include <sound/initval.h> |
| 31 | #include <sound/tlv.h> |
| 32 | |
| 33 | #include "wm8400.h" |
| 34 | |
| 35 | /* Fake register for internal state */ |
| 36 | #define WM8400_INTDRIVBITS (WM8400_REGISTER_COUNT + 1) |
| 37 | #define WM8400_INMIXL_PWR 0 |
| 38 | #define WM8400_AINLMUX_PWR 1 |
| 39 | #define WM8400_INMIXR_PWR 2 |
| 40 | #define WM8400_AINRMUX_PWR 3 |
| 41 | |
| 42 | static struct regulator_bulk_data power[] = { |
| 43 | { |
| 44 | .supply = "I2S1VDD", |
| 45 | }, |
| 46 | { |
| 47 | .supply = "I2S2VDD", |
| 48 | }, |
| 49 | { |
| 50 | .supply = "DCVDD", |
| 51 | }, |
| 52 | { |
Mark Brown | 24a5102 | 2009-03-18 15:19:48 +0000 | [diff] [blame] | 53 | .supply = "AVDD", |
| 54 | }, |
| 55 | { |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 56 | .supply = "FLLVDD", |
| 57 | }, |
| 58 | { |
| 59 | .supply = "HPVDD", |
| 60 | }, |
| 61 | { |
| 62 | .supply = "SPKVDD", |
| 63 | }, |
| 64 | }; |
| 65 | |
| 66 | /* codec private data */ |
| 67 | struct wm8400_priv { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 68 | struct snd_soc_codec *codec; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 69 | struct wm8400 *wm8400; |
| 70 | u16 fake_register; |
| 71 | unsigned int sysclk; |
| 72 | unsigned int pcmclk; |
| 73 | struct work_struct work; |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 74 | int fll_in, fll_out; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | static inline unsigned int wm8400_read(struct snd_soc_codec *codec, |
| 78 | unsigned int reg) |
| 79 | { |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 80 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 81 | |
| 82 | if (reg == WM8400_INTDRIVBITS) |
| 83 | return wm8400->fake_register; |
| 84 | else |
| 85 | return wm8400_reg_read(wm8400->wm8400, reg); |
| 86 | } |
| 87 | |
| 88 | /* |
| 89 | * write to the wm8400 register space |
| 90 | */ |
| 91 | static int wm8400_write(struct snd_soc_codec *codec, unsigned int reg, |
| 92 | unsigned int value) |
| 93 | { |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 94 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 95 | |
| 96 | if (reg == WM8400_INTDRIVBITS) { |
| 97 | wm8400->fake_register = value; |
| 98 | return 0; |
| 99 | } else |
| 100 | return wm8400_set_bits(wm8400->wm8400, reg, 0xffff, value); |
| 101 | } |
| 102 | |
| 103 | static void wm8400_codec_reset(struct snd_soc_codec *codec) |
| 104 | { |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 105 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 106 | |
| 107 | wm8400_reset_codec_reg_cache(wm8400->wm8400); |
| 108 | } |
| 109 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 110 | static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 111 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 112 | static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 113 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 114 | static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 115 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 116 | static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 117 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 118 | static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 119 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 120 | static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 121 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 122 | static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 123 | |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 124 | static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 125 | |
| 126 | static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, |
| 127 | struct snd_ctl_elem_value *ucontrol) |
| 128 | { |
| 129 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
| 130 | struct soc_mixer_control *mc = |
| 131 | (struct soc_mixer_control *)kcontrol->private_value; |
| 132 | int reg = mc->reg; |
| 133 | int ret; |
| 134 | u16 val; |
| 135 | |
| 136 | ret = snd_soc_put_volsw(kcontrol, ucontrol); |
| 137 | if (ret < 0) |
| 138 | return ret; |
| 139 | |
| 140 | /* now hit the volume update bits (always bit 8) */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 141 | val = snd_soc_read(codec, reg); |
| 142 | return snd_soc_write(codec, reg, val | 0x0100); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ |
| 146 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ |
| 147 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ |
| 148 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ |
| 149 | .tlv.p = (tlv_array), \ |
| 150 | .info = snd_soc_info_volsw, \ |
| 151 | .get = snd_soc_get_volsw, .put = wm8400_outpga_put_volsw_vu, \ |
| 152 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } |
| 153 | |
| 154 | |
| 155 | static const char *wm8400_digital_sidetone[] = |
| 156 | {"None", "Left ADC", "Right ADC", "Reserved"}; |
| 157 | |
| 158 | static const struct soc_enum wm8400_left_digital_sidetone_enum = |
| 159 | SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE, |
| 160 | WM8400_ADC_TO_DACL_SHIFT, 2, wm8400_digital_sidetone); |
| 161 | |
| 162 | static const struct soc_enum wm8400_right_digital_sidetone_enum = |
| 163 | SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE, |
| 164 | WM8400_ADC_TO_DACR_SHIFT, 2, wm8400_digital_sidetone); |
| 165 | |
| 166 | static const char *wm8400_adcmode[] = |
| 167 | {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; |
| 168 | |
| 169 | static const struct soc_enum wm8400_right_adcmode_enum = |
| 170 | SOC_ENUM_SINGLE(WM8400_ADC_CTRL, WM8400_ADC_HPF_CUT_SHIFT, 3, wm8400_adcmode); |
| 171 | |
| 172 | static const struct snd_kcontrol_new wm8400_snd_controls[] = { |
| 173 | /* INMIXL */ |
| 174 | SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT, |
| 175 | 1, 0), |
| 176 | SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT, |
| 177 | 1, 0), |
| 178 | /* INMIXR */ |
| 179 | SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT, |
| 180 | 1, 0), |
| 181 | SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT, |
| 182 | 1, 0), |
| 183 | |
| 184 | /* LOMIX */ |
| 185 | SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3, |
| 186 | WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv), |
| 187 | SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, |
| 188 | WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv), |
| 189 | SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, |
| 190 | WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv), |
| 191 | SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5, |
| 192 | WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv), |
| 193 | SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5, |
| 194 | WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), |
| 195 | SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5, |
| 196 | WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), |
| 197 | |
| 198 | /* ROMIX */ |
| 199 | SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4, |
| 200 | WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv), |
| 201 | SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, |
| 202 | WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv), |
| 203 | SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, |
| 204 | WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv), |
| 205 | SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6, |
| 206 | WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv), |
| 207 | SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6, |
| 208 | WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv), |
| 209 | SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6, |
| 210 | WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv), |
| 211 | |
| 212 | /* LOUT */ |
| 213 | WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME, |
| 214 | WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv), |
| 215 | SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0), |
| 216 | |
| 217 | /* ROUT */ |
| 218 | WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME, |
| 219 | WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv), |
| 220 | SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0), |
| 221 | |
| 222 | /* LOPGA */ |
| 223 | WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME, |
| 224 | WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv), |
| 225 | SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME, |
| 226 | WM8400_LOPGAZC_SHIFT, 1, 0), |
| 227 | |
| 228 | /* ROPGA */ |
| 229 | WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME, |
| 230 | WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv), |
| 231 | SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME, |
| 232 | WM8400_ROPGAZC_SHIFT, 1, 0), |
| 233 | |
| 234 | SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, |
| 235 | WM8400_LONMUTE_SHIFT, 1, 0), |
| 236 | SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, |
| 237 | WM8400_LOPMUTE_SHIFT, 1, 0), |
| 238 | SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, |
| 239 | WM8400_LOATTN_SHIFT, 1, 0), |
| 240 | SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, |
| 241 | WM8400_RONMUTE_SHIFT, 1, 0), |
| 242 | SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, |
| 243 | WM8400_ROPMUTE_SHIFT, 1, 0), |
| 244 | SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, |
| 245 | WM8400_ROATTN_SHIFT, 1, 0), |
| 246 | |
| 247 | SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME, |
| 248 | WM8400_OUT3MUTE_SHIFT, 1, 0), |
| 249 | SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME, |
| 250 | WM8400_OUT3ATTN_SHIFT, 1, 0), |
| 251 | |
| 252 | SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME, |
| 253 | WM8400_OUT4MUTE_SHIFT, 1, 0), |
| 254 | SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME, |
| 255 | WM8400_OUT4ATTN_SHIFT, 1, 0), |
| 256 | |
| 257 | SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1, |
| 258 | WM8400_CDMODE_SHIFT, 1, 0), |
| 259 | |
| 260 | SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME, |
| 261 | WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0), |
| 262 | SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3, |
| 263 | WM8400_DCGAIN_SHIFT, 6, 0), |
| 264 | SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3, |
| 265 | WM8400_ACGAIN_SHIFT, 6, 0), |
| 266 | |
| 267 | WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", |
| 268 | WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT, |
| 269 | 127, 0, out_dac_tlv), |
| 270 | |
| 271 | WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", |
| 272 | WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT, |
| 273 | 127, 0, out_dac_tlv), |
| 274 | |
| 275 | SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum), |
| 276 | SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum), |
| 277 | |
| 278 | SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, |
| 279 | WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), |
| 280 | SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, |
| 281 | WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), |
| 282 | |
| 283 | SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL, |
| 284 | WM8400_ADC_HPF_ENA_SHIFT, 1, 0), |
| 285 | |
| 286 | SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum), |
| 287 | |
| 288 | WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", |
| 289 | WM8400_LEFT_ADC_DIGITAL_VOLUME, |
| 290 | WM8400_ADCL_VOL_SHIFT, |
| 291 | WM8400_ADCL_VOL_MASK, |
| 292 | 0, |
| 293 | in_adc_tlv), |
| 294 | |
| 295 | WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", |
| 296 | WM8400_RIGHT_ADC_DIGITAL_VOLUME, |
| 297 | WM8400_ADCR_VOL_SHIFT, |
| 298 | WM8400_ADCR_VOL_MASK, |
| 299 | 0, |
| 300 | in_adc_tlv), |
| 301 | |
| 302 | WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume", |
| 303 | WM8400_LEFT_LINE_INPUT_1_2_VOLUME, |
| 304 | WM8400_LIN12VOL_SHIFT, |
| 305 | WM8400_LIN12VOL_MASK, |
| 306 | 0, |
| 307 | in_pga_tlv), |
| 308 | |
| 309 | SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, |
| 310 | WM8400_LI12ZC_SHIFT, 1, 0), |
| 311 | |
| 312 | SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, |
| 313 | WM8400_LI12MUTE_SHIFT, 1, 0), |
| 314 | |
| 315 | WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume", |
| 316 | WM8400_LEFT_LINE_INPUT_3_4_VOLUME, |
| 317 | WM8400_LIN34VOL_SHIFT, |
| 318 | WM8400_LIN34VOL_MASK, |
| 319 | 0, |
| 320 | in_pga_tlv), |
| 321 | |
| 322 | SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, |
| 323 | WM8400_LI34ZC_SHIFT, 1, 0), |
| 324 | |
| 325 | SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, |
| 326 | WM8400_LI34MUTE_SHIFT, 1, 0), |
| 327 | |
| 328 | WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume", |
| 329 | WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, |
| 330 | WM8400_RIN12VOL_SHIFT, |
| 331 | WM8400_RIN12VOL_MASK, |
| 332 | 0, |
| 333 | in_pga_tlv), |
| 334 | |
| 335 | SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, |
| 336 | WM8400_RI12ZC_SHIFT, 1, 0), |
| 337 | |
| 338 | SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, |
| 339 | WM8400_RI12MUTE_SHIFT, 1, 0), |
| 340 | |
| 341 | WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume", |
| 342 | WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, |
| 343 | WM8400_RIN34VOL_SHIFT, |
| 344 | WM8400_RIN34VOL_MASK, |
| 345 | 0, |
| 346 | in_pga_tlv), |
| 347 | |
| 348 | SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, |
| 349 | WM8400_RI34ZC_SHIFT, 1, 0), |
| 350 | |
| 351 | SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, |
| 352 | WM8400_RI34MUTE_SHIFT, 1, 0), |
| 353 | |
| 354 | }; |
| 355 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 356 | /* |
| 357 | * _DAPM_ Controls |
| 358 | */ |
| 359 | |
| 360 | static int inmixer_event (struct snd_soc_dapm_widget *w, |
| 361 | struct snd_kcontrol *kcontrol, int event) |
| 362 | { |
| 363 | u16 reg, fakepower; |
| 364 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 365 | reg = snd_soc_read(w->codec, WM8400_POWER_MANAGEMENT_2); |
| 366 | fakepower = snd_soc_read(w->codec, WM8400_INTDRIVBITS); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 367 | |
| 368 | if (fakepower & ((1 << WM8400_INMIXL_PWR) | |
| 369 | (1 << WM8400_AINLMUX_PWR))) { |
| 370 | reg |= WM8400_AINL_ENA; |
| 371 | } else { |
| 372 | reg &= ~WM8400_AINL_ENA; |
| 373 | } |
| 374 | |
| 375 | if (fakepower & ((1 << WM8400_INMIXR_PWR) | |
| 376 | (1 << WM8400_AINRMUX_PWR))) { |
| 377 | reg |= WM8400_AINR_ENA; |
| 378 | } else { |
Axel Lin | 1a8e8d2 | 2011-10-14 13:56:49 +0800 | [diff] [blame] | 379 | reg &= ~WM8400_AINR_ENA; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 380 | } |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 381 | snd_soc_write(w->codec, WM8400_POWER_MANAGEMENT_2, reg); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 382 | |
| 383 | return 0; |
| 384 | } |
| 385 | |
| 386 | static int outmixer_event (struct snd_soc_dapm_widget *w, |
| 387 | struct snd_kcontrol * kcontrol, int event) |
| 388 | { |
| 389 | struct soc_mixer_control *mc = |
| 390 | (struct soc_mixer_control *)kcontrol->private_value; |
| 391 | u32 reg_shift = mc->shift; |
| 392 | int ret = 0; |
| 393 | u16 reg; |
| 394 | |
| 395 | switch (reg_shift) { |
| 396 | case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) : |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 397 | reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER1); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 398 | if (reg & WM8400_LDLO) { |
| 399 | printk(KERN_WARNING |
| 400 | "Cannot set as Output Mixer 1 LDLO Set\n"); |
| 401 | ret = -1; |
| 402 | } |
| 403 | break; |
| 404 | case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8): |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 405 | reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER2); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 406 | if (reg & WM8400_RDRO) { |
| 407 | printk(KERN_WARNING |
| 408 | "Cannot set as Output Mixer 2 RDRO Set\n"); |
| 409 | ret = -1; |
| 410 | } |
| 411 | break; |
| 412 | case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8): |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 413 | reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 414 | if (reg & WM8400_LDSPK) { |
| 415 | printk(KERN_WARNING |
| 416 | "Cannot set as Speaker Mixer LDSPK Set\n"); |
| 417 | ret = -1; |
| 418 | } |
| 419 | break; |
| 420 | case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8): |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 421 | reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 422 | if (reg & WM8400_RDSPK) { |
| 423 | printk(KERN_WARNING |
| 424 | "Cannot set as Speaker Mixer RDSPK Set\n"); |
| 425 | ret = -1; |
| 426 | } |
| 427 | break; |
| 428 | } |
| 429 | |
| 430 | return ret; |
| 431 | } |
| 432 | |
| 433 | /* INMIX dB values */ |
| 434 | static const unsigned int in_mix_tlv[] = { |
| 435 | TLV_DB_RANGE_HEAD(1), |
Mark Brown | 3351e9f | 2010-05-25 10:48:31 -0700 | [diff] [blame] | 436 | 0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0), |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 437 | }; |
| 438 | |
| 439 | /* Left In PGA Connections */ |
| 440 | static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = { |
| 441 | SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0), |
| 442 | SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0), |
| 443 | }; |
| 444 | |
| 445 | static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = { |
| 446 | SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0), |
| 447 | SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0), |
| 448 | }; |
| 449 | |
| 450 | /* Right In PGA Connections */ |
| 451 | static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = { |
| 452 | SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0), |
| 453 | SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0), |
| 454 | }; |
| 455 | |
| 456 | static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = { |
| 457 | SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0), |
| 458 | SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0), |
| 459 | }; |
| 460 | |
| 461 | /* INMIXL */ |
| 462 | static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = { |
| 463 | SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3, |
| 464 | WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv), |
| 465 | SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT, |
| 466 | 7, 0, in_mix_tlv), |
| 467 | SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, |
| 468 | 1, 0), |
| 469 | SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, |
| 470 | 1, 0), |
| 471 | }; |
| 472 | |
| 473 | /* INMIXR */ |
| 474 | static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = { |
| 475 | SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4, |
| 476 | WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv), |
| 477 | SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT, |
| 478 | 7, 0, in_mix_tlv), |
| 479 | SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, |
| 480 | 1, 0), |
| 481 | SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, |
| 482 | 1, 0), |
| 483 | }; |
| 484 | |
| 485 | /* AINLMUX */ |
| 486 | static const char *wm8400_ainlmux[] = |
| 487 | {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; |
| 488 | |
| 489 | static const struct soc_enum wm8400_ainlmux_enum = |
| 490 | SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINLMODE_SHIFT, |
| 491 | ARRAY_SIZE(wm8400_ainlmux), wm8400_ainlmux); |
| 492 | |
| 493 | static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls = |
| 494 | SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum); |
| 495 | |
| 496 | /* DIFFINL */ |
| 497 | |
| 498 | /* AINRMUX */ |
| 499 | static const char *wm8400_ainrmux[] = |
| 500 | {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; |
| 501 | |
| 502 | static const struct soc_enum wm8400_ainrmux_enum = |
| 503 | SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINRMODE_SHIFT, |
| 504 | ARRAY_SIZE(wm8400_ainrmux), wm8400_ainrmux); |
| 505 | |
| 506 | static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls = |
| 507 | SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum); |
| 508 | |
| 509 | /* RXVOICE */ |
| 510 | static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = { |
| 511 | SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT, |
| 512 | WM8400_LR4BVOL_MASK, 0, in_mix_tlv), |
| 513 | SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT, |
| 514 | WM8400_RL4BVOL_MASK, 0, in_mix_tlv), |
| 515 | }; |
| 516 | |
| 517 | /* LOMIX */ |
| 518 | static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = { |
| 519 | SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1, |
| 520 | WM8400_LRBLO_SHIFT, 1, 0), |
| 521 | SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1, |
| 522 | WM8400_LLBLO_SHIFT, 1, 0), |
| 523 | SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, |
| 524 | WM8400_LRI3LO_SHIFT, 1, 0), |
| 525 | SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, |
| 526 | WM8400_LLI3LO_SHIFT, 1, 0), |
| 527 | SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, |
| 528 | WM8400_LR12LO_SHIFT, 1, 0), |
| 529 | SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, |
| 530 | WM8400_LL12LO_SHIFT, 1, 0), |
| 531 | SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1, |
| 532 | WM8400_LDLO_SHIFT, 1, 0), |
| 533 | }; |
| 534 | |
| 535 | /* ROMIX */ |
| 536 | static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = { |
| 537 | SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2, |
| 538 | WM8400_RLBRO_SHIFT, 1, 0), |
| 539 | SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2, |
| 540 | WM8400_RRBRO_SHIFT, 1, 0), |
| 541 | SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, |
| 542 | WM8400_RLI3RO_SHIFT, 1, 0), |
| 543 | SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, |
| 544 | WM8400_RRI3RO_SHIFT, 1, 0), |
| 545 | SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, |
| 546 | WM8400_RL12RO_SHIFT, 1, 0), |
| 547 | SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, |
| 548 | WM8400_RR12RO_SHIFT, 1, 0), |
| 549 | SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2, |
| 550 | WM8400_RDRO_SHIFT, 1, 0), |
| 551 | }; |
| 552 | |
| 553 | /* LONMIX */ |
| 554 | static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = { |
| 555 | SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, |
| 556 | WM8400_LLOPGALON_SHIFT, 1, 0), |
| 557 | SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1, |
| 558 | WM8400_LROPGALON_SHIFT, 1, 0), |
| 559 | SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1, |
| 560 | WM8400_LOPLON_SHIFT, 1, 0), |
| 561 | }; |
| 562 | |
| 563 | /* LOPMIX */ |
| 564 | static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = { |
| 565 | SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1, |
| 566 | WM8400_LR12LOP_SHIFT, 1, 0), |
| 567 | SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1, |
| 568 | WM8400_LL12LOP_SHIFT, 1, 0), |
| 569 | SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, |
| 570 | WM8400_LLOPGALOP_SHIFT, 1, 0), |
| 571 | }; |
| 572 | |
| 573 | /* RONMIX */ |
| 574 | static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = { |
| 575 | SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, |
| 576 | WM8400_RROPGARON_SHIFT, 1, 0), |
| 577 | SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2, |
| 578 | WM8400_RLOPGARON_SHIFT, 1, 0), |
| 579 | SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2, |
| 580 | WM8400_ROPRON_SHIFT, 1, 0), |
| 581 | }; |
| 582 | |
| 583 | /* ROPMIX */ |
| 584 | static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = { |
| 585 | SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2, |
| 586 | WM8400_RL12ROP_SHIFT, 1, 0), |
| 587 | SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2, |
| 588 | WM8400_RR12ROP_SHIFT, 1, 0), |
| 589 | SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, |
| 590 | WM8400_RROPGAROP_SHIFT, 1, 0), |
| 591 | }; |
| 592 | |
| 593 | /* OUT3MIX */ |
| 594 | static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = { |
| 595 | SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, |
| 596 | WM8400_LI4O3_SHIFT, 1, 0), |
| 597 | SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER, |
| 598 | WM8400_LPGAO3_SHIFT, 1, 0), |
| 599 | }; |
| 600 | |
| 601 | /* OUT4MIX */ |
| 602 | static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = { |
| 603 | SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER, |
| 604 | WM8400_RPGAO4_SHIFT, 1, 0), |
| 605 | SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, |
| 606 | WM8400_RI4O4_SHIFT, 1, 0), |
| 607 | }; |
| 608 | |
| 609 | /* SPKMIX */ |
| 610 | static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = { |
| 611 | SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER, |
| 612 | WM8400_LI2SPK_SHIFT, 1, 0), |
| 613 | SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER, |
| 614 | WM8400_LB2SPK_SHIFT, 1, 0), |
| 615 | SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER, |
| 616 | WM8400_LOPGASPK_SHIFT, 1, 0), |
| 617 | SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER, |
| 618 | WM8400_LDSPK_SHIFT, 1, 0), |
| 619 | SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER, |
| 620 | WM8400_RDSPK_SHIFT, 1, 0), |
| 621 | SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER, |
| 622 | WM8400_ROPGASPK_SHIFT, 1, 0), |
| 623 | SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER, |
| 624 | WM8400_RL12ROP_SHIFT, 1, 0), |
| 625 | SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER, |
| 626 | WM8400_RI2SPK_SHIFT, 1, 0), |
| 627 | }; |
| 628 | |
| 629 | static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = { |
| 630 | /* Input Side */ |
| 631 | /* Input Lines */ |
| 632 | SND_SOC_DAPM_INPUT("LIN1"), |
| 633 | SND_SOC_DAPM_INPUT("LIN2"), |
| 634 | SND_SOC_DAPM_INPUT("LIN3"), |
| 635 | SND_SOC_DAPM_INPUT("LIN4/RXN"), |
| 636 | SND_SOC_DAPM_INPUT("RIN3"), |
| 637 | SND_SOC_DAPM_INPUT("RIN4/RXP"), |
| 638 | SND_SOC_DAPM_INPUT("RIN1"), |
| 639 | SND_SOC_DAPM_INPUT("RIN2"), |
| 640 | SND_SOC_DAPM_INPUT("Internal ADC Source"), |
| 641 | |
| 642 | /* DACs */ |
| 643 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2, |
| 644 | WM8400_ADCL_ENA_SHIFT, 0), |
| 645 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2, |
| 646 | WM8400_ADCR_ENA_SHIFT, 0), |
| 647 | |
| 648 | /* Input PGAs */ |
| 649 | SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2, |
| 650 | WM8400_LIN12_ENA_SHIFT, |
| 651 | 0, &wm8400_dapm_lin12_pga_controls[0], |
| 652 | ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)), |
| 653 | SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2, |
| 654 | WM8400_LIN34_ENA_SHIFT, |
| 655 | 0, &wm8400_dapm_lin34_pga_controls[0], |
| 656 | ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)), |
| 657 | SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2, |
| 658 | WM8400_RIN12_ENA_SHIFT, |
| 659 | 0, &wm8400_dapm_rin12_pga_controls[0], |
| 660 | ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)), |
| 661 | SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2, |
| 662 | WM8400_RIN34_ENA_SHIFT, |
| 663 | 0, &wm8400_dapm_rin34_pga_controls[0], |
| 664 | ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)), |
| 665 | |
| 666 | /* INMIXL */ |
| 667 | SND_SOC_DAPM_MIXER_E("INMIXL", WM8400_INTDRIVBITS, WM8400_INMIXL_PWR, 0, |
| 668 | &wm8400_dapm_inmixl_controls[0], |
| 669 | ARRAY_SIZE(wm8400_dapm_inmixl_controls), |
| 670 | inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 671 | |
| 672 | /* AINLMUX */ |
| 673 | SND_SOC_DAPM_MUX_E("AILNMUX", WM8400_INTDRIVBITS, WM8400_AINLMUX_PWR, 0, |
| 674 | &wm8400_dapm_ainlmux_controls, inmixer_event, |
| 675 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 676 | |
| 677 | /* INMIXR */ |
| 678 | SND_SOC_DAPM_MIXER_E("INMIXR", WM8400_INTDRIVBITS, WM8400_INMIXR_PWR, 0, |
| 679 | &wm8400_dapm_inmixr_controls[0], |
| 680 | ARRAY_SIZE(wm8400_dapm_inmixr_controls), |
| 681 | inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 682 | |
| 683 | /* AINRMUX */ |
| 684 | SND_SOC_DAPM_MUX_E("AIRNMUX", WM8400_INTDRIVBITS, WM8400_AINRMUX_PWR, 0, |
| 685 | &wm8400_dapm_ainrmux_controls, inmixer_event, |
| 686 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 687 | |
| 688 | /* Output Side */ |
| 689 | /* DACs */ |
| 690 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3, |
| 691 | WM8400_DACL_ENA_SHIFT, 0), |
| 692 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3, |
| 693 | WM8400_DACR_ENA_SHIFT, 0), |
| 694 | |
| 695 | /* LOMIX */ |
| 696 | SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3, |
| 697 | WM8400_LOMIX_ENA_SHIFT, |
| 698 | 0, &wm8400_dapm_lomix_controls[0], |
| 699 | ARRAY_SIZE(wm8400_dapm_lomix_controls), |
| 700 | outmixer_event, SND_SOC_DAPM_PRE_REG), |
| 701 | |
| 702 | /* LONMIX */ |
| 703 | SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT, |
| 704 | 0, &wm8400_dapm_lonmix_controls[0], |
| 705 | ARRAY_SIZE(wm8400_dapm_lonmix_controls)), |
| 706 | |
| 707 | /* LOPMIX */ |
| 708 | SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT, |
| 709 | 0, &wm8400_dapm_lopmix_controls[0], |
| 710 | ARRAY_SIZE(wm8400_dapm_lopmix_controls)), |
| 711 | |
| 712 | /* OUT3MIX */ |
| 713 | SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT, |
| 714 | 0, &wm8400_dapm_out3mix_controls[0], |
| 715 | ARRAY_SIZE(wm8400_dapm_out3mix_controls)), |
| 716 | |
| 717 | /* SPKMIX */ |
| 718 | SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT, |
| 719 | 0, &wm8400_dapm_spkmix_controls[0], |
| 720 | ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event, |
| 721 | SND_SOC_DAPM_PRE_REG), |
| 722 | |
| 723 | /* OUT4MIX */ |
| 724 | SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT, |
| 725 | 0, &wm8400_dapm_out4mix_controls[0], |
| 726 | ARRAY_SIZE(wm8400_dapm_out4mix_controls)), |
| 727 | |
| 728 | /* ROPMIX */ |
| 729 | SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT, |
| 730 | 0, &wm8400_dapm_ropmix_controls[0], |
| 731 | ARRAY_SIZE(wm8400_dapm_ropmix_controls)), |
| 732 | |
| 733 | /* RONMIX */ |
| 734 | SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT, |
| 735 | 0, &wm8400_dapm_ronmix_controls[0], |
| 736 | ARRAY_SIZE(wm8400_dapm_ronmix_controls)), |
| 737 | |
| 738 | /* ROMIX */ |
| 739 | SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3, |
| 740 | WM8400_ROMIX_ENA_SHIFT, |
| 741 | 0, &wm8400_dapm_romix_controls[0], |
| 742 | ARRAY_SIZE(wm8400_dapm_romix_controls), |
| 743 | outmixer_event, SND_SOC_DAPM_PRE_REG), |
| 744 | |
| 745 | /* LOUT PGA */ |
| 746 | SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT, |
| 747 | 0, NULL, 0), |
| 748 | |
| 749 | /* ROUT PGA */ |
| 750 | SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT, |
| 751 | 0, NULL, 0), |
| 752 | |
| 753 | /* LOPGA */ |
| 754 | SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0, |
| 755 | NULL, 0), |
| 756 | |
| 757 | /* ROPGA */ |
| 758 | SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0, |
| 759 | NULL, 0), |
| 760 | |
| 761 | /* MICBIAS */ |
Mark Brown | 3ff51c8 | 2011-10-27 09:44:59 +0200 | [diff] [blame] | 762 | SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1, |
| 763 | WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0), |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 764 | |
| 765 | SND_SOC_DAPM_OUTPUT("LON"), |
| 766 | SND_SOC_DAPM_OUTPUT("LOP"), |
| 767 | SND_SOC_DAPM_OUTPUT("OUT3"), |
| 768 | SND_SOC_DAPM_OUTPUT("LOUT"), |
| 769 | SND_SOC_DAPM_OUTPUT("SPKN"), |
| 770 | SND_SOC_DAPM_OUTPUT("SPKP"), |
| 771 | SND_SOC_DAPM_OUTPUT("ROUT"), |
| 772 | SND_SOC_DAPM_OUTPUT("OUT4"), |
| 773 | SND_SOC_DAPM_OUTPUT("ROP"), |
| 774 | SND_SOC_DAPM_OUTPUT("RON"), |
| 775 | |
| 776 | SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), |
| 777 | }; |
| 778 | |
Mark Brown | b4505ab | 2011-12-03 11:34:34 +0000 | [diff] [blame] | 779 | static const struct snd_soc_dapm_route wm8400_dapm_routes[] = { |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 780 | /* Make DACs turn on when playing even if not mixed into any outputs */ |
| 781 | {"Internal DAC Sink", NULL, "Left DAC"}, |
| 782 | {"Internal DAC Sink", NULL, "Right DAC"}, |
| 783 | |
| 784 | /* Make ADCs turn on when recording |
| 785 | * even if not mixed from any inputs */ |
| 786 | {"Left ADC", NULL, "Internal ADC Source"}, |
| 787 | {"Right ADC", NULL, "Internal ADC Source"}, |
| 788 | |
| 789 | /* Input Side */ |
| 790 | /* LIN12 PGA */ |
| 791 | {"LIN12 PGA", "LIN1 Switch", "LIN1"}, |
| 792 | {"LIN12 PGA", "LIN2 Switch", "LIN2"}, |
| 793 | /* LIN34 PGA */ |
| 794 | {"LIN34 PGA", "LIN3 Switch", "LIN3"}, |
| 795 | {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, |
| 796 | /* INMIXL */ |
| 797 | {"INMIXL", "Record Left Volume", "LOMIX"}, |
| 798 | {"INMIXL", "LIN2 Volume", "LIN2"}, |
| 799 | {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, |
| 800 | {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, |
| 801 | /* AILNMUX */ |
| 802 | {"AILNMUX", "INMIXL Mix", "INMIXL"}, |
| 803 | {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"}, |
| 804 | {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"}, |
| 805 | {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"}, |
| 806 | {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"}, |
| 807 | /* ADC */ |
| 808 | {"Left ADC", NULL, "AILNMUX"}, |
| 809 | |
| 810 | /* RIN12 PGA */ |
| 811 | {"RIN12 PGA", "RIN1 Switch", "RIN1"}, |
| 812 | {"RIN12 PGA", "RIN2 Switch", "RIN2"}, |
| 813 | /* RIN34 PGA */ |
| 814 | {"RIN34 PGA", "RIN3 Switch", "RIN3"}, |
| 815 | {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, |
| 816 | /* INMIXL */ |
| 817 | {"INMIXR", "Record Right Volume", "ROMIX"}, |
| 818 | {"INMIXR", "RIN2 Volume", "RIN2"}, |
| 819 | {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, |
| 820 | {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, |
| 821 | /* AIRNMUX */ |
| 822 | {"AIRNMUX", "INMIXR Mix", "INMIXR"}, |
| 823 | {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"}, |
| 824 | {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"}, |
| 825 | {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"}, |
| 826 | {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"}, |
| 827 | /* ADC */ |
| 828 | {"Right ADC", NULL, "AIRNMUX"}, |
| 829 | |
| 830 | /* LOMIX */ |
| 831 | {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, |
| 832 | {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, |
| 833 | {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, |
| 834 | {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, |
| 835 | {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"}, |
| 836 | {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"}, |
| 837 | {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, |
| 838 | |
| 839 | /* ROMIX */ |
| 840 | {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, |
| 841 | {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, |
| 842 | {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, |
| 843 | {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, |
| 844 | {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"}, |
| 845 | {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"}, |
| 846 | {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, |
| 847 | |
| 848 | /* SPKMIX */ |
| 849 | {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, |
| 850 | {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, |
| 851 | {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"}, |
| 852 | {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"}, |
| 853 | {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, |
| 854 | {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, |
| 855 | {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, |
| 856 | {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, |
| 857 | |
| 858 | /* LONMIX */ |
| 859 | {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, |
| 860 | {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, |
| 861 | {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, |
| 862 | |
| 863 | /* LOPMIX */ |
| 864 | {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, |
| 865 | {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, |
| 866 | {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, |
| 867 | |
| 868 | /* OUT3MIX */ |
| 869 | {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, |
| 870 | {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, |
| 871 | |
| 872 | /* OUT4MIX */ |
| 873 | {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, |
| 874 | {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, |
| 875 | |
| 876 | /* RONMIX */ |
| 877 | {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, |
| 878 | {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, |
| 879 | {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, |
| 880 | |
| 881 | /* ROPMIX */ |
| 882 | {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, |
| 883 | {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, |
| 884 | {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, |
| 885 | |
| 886 | /* Out Mixer PGAs */ |
| 887 | {"LOPGA", NULL, "LOMIX"}, |
| 888 | {"ROPGA", NULL, "ROMIX"}, |
| 889 | |
| 890 | {"LOUT PGA", NULL, "LOMIX"}, |
| 891 | {"ROUT PGA", NULL, "ROMIX"}, |
| 892 | |
| 893 | /* Output Pins */ |
| 894 | {"LON", NULL, "LONMIX"}, |
| 895 | {"LOP", NULL, "LOPMIX"}, |
| 896 | {"OUT3", NULL, "OUT3MIX"}, |
| 897 | {"LOUT", NULL, "LOUT PGA"}, |
| 898 | {"SPKN", NULL, "SPKMIX"}, |
| 899 | {"ROUT", NULL, "ROUT PGA"}, |
| 900 | {"OUT4", NULL, "OUT4MIX"}, |
| 901 | {"ROP", NULL, "ROPMIX"}, |
| 902 | {"RON", NULL, "RONMIX"}, |
| 903 | }; |
| 904 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 905 | /* |
| 906 | * Clock after FLL and dividers |
| 907 | */ |
| 908 | static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
| 909 | int clk_id, unsigned int freq, int dir) |
| 910 | { |
| 911 | struct snd_soc_codec *codec = codec_dai->codec; |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 912 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 913 | |
| 914 | wm8400->sysclk = freq; |
| 915 | return 0; |
| 916 | } |
| 917 | |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 918 | struct fll_factors { |
| 919 | u16 n; |
| 920 | u16 k; |
| 921 | u16 outdiv; |
| 922 | u16 fratio; |
| 923 | u16 freq_ref; |
| 924 | }; |
| 925 | |
| 926 | #define FIXED_FLL_SIZE ((1 << 16) * 10) |
| 927 | |
| 928 | static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors, |
| 929 | unsigned int Fref, unsigned int Fout) |
| 930 | { |
| 931 | u64 Kpart; |
| 932 | unsigned int K, Nmod, target; |
| 933 | |
| 934 | factors->outdiv = 2; |
| 935 | while (Fout * factors->outdiv < 90000000 || |
| 936 | Fout * factors->outdiv > 100000000) { |
| 937 | factors->outdiv *= 2; |
| 938 | if (factors->outdiv > 32) { |
| 939 | dev_err(wm8400->wm8400->dev, |
Roel Kluin | 449bd54 | 2009-05-27 17:08:39 -0700 | [diff] [blame] | 940 | "Unsupported FLL output frequency %uHz\n", |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 941 | Fout); |
| 942 | return -EINVAL; |
| 943 | } |
| 944 | } |
| 945 | target = Fout * factors->outdiv; |
| 946 | factors->outdiv = factors->outdiv >> 2; |
| 947 | |
| 948 | if (Fref < 48000) |
| 949 | factors->freq_ref = 1; |
| 950 | else |
| 951 | factors->freq_ref = 0; |
| 952 | |
| 953 | if (Fref < 1000000) |
| 954 | factors->fratio = 9; |
| 955 | else |
| 956 | factors->fratio = 0; |
| 957 | |
| 958 | /* Ensure we have a fractional part */ |
| 959 | do { |
| 960 | if (Fref < 1000000) |
| 961 | factors->fratio--; |
| 962 | else |
| 963 | factors->fratio++; |
| 964 | |
| 965 | if (factors->fratio < 1 || factors->fratio > 8) { |
| 966 | dev_err(wm8400->wm8400->dev, |
| 967 | "Unable to calculate FRATIO\n"); |
| 968 | return -EINVAL; |
| 969 | } |
| 970 | |
| 971 | factors->n = target / (Fref * factors->fratio); |
| 972 | Nmod = target % (Fref * factors->fratio); |
| 973 | } while (Nmod == 0); |
| 974 | |
| 975 | /* Calculate fractional part - scale up so we can round. */ |
| 976 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; |
| 977 | |
| 978 | do_div(Kpart, (Fref * factors->fratio)); |
| 979 | |
| 980 | K = Kpart & 0xFFFFFFFF; |
| 981 | |
| 982 | if ((K % 10) >= 5) |
| 983 | K += 5; |
| 984 | |
| 985 | /* Move down to proper range now rounding is done */ |
| 986 | factors->k = K / 10; |
| 987 | |
| 988 | dev_dbg(wm8400->wm8400->dev, |
Roel Kluin | 449bd54 | 2009-05-27 17:08:39 -0700 | [diff] [blame] | 989 | "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n", |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 990 | Fref, Fout, |
| 991 | factors->n, factors->k, factors->fratio, factors->outdiv); |
| 992 | |
| 993 | return 0; |
| 994 | } |
| 995 | |
| 996 | static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
Mark Brown | 8548803 | 2009-09-05 18:52:16 +0100 | [diff] [blame] | 997 | int source, unsigned int freq_in, |
| 998 | unsigned int freq_out) |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 999 | { |
| 1000 | struct snd_soc_codec *codec = codec_dai->codec; |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 1001 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1002 | struct fll_factors factors; |
| 1003 | int ret; |
| 1004 | u16 reg; |
| 1005 | |
| 1006 | if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out) |
| 1007 | return 0; |
| 1008 | |
Mark Brown | 8aa2df5 | 2009-07-17 21:53:49 +0100 | [diff] [blame] | 1009 | if (freq_out) { |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1010 | ret = fll_factors(wm8400, &factors, freq_in, freq_out); |
| 1011 | if (ret != 0) |
| 1012 | return ret; |
Mark Brown | 8aa2df5 | 2009-07-17 21:53:49 +0100 | [diff] [blame] | 1013 | } else { |
| 1014 | /* Bodge GCC 4.4.0 uninitialised variable warning - it |
| 1015 | * doesn't seem capable of working out that we exit if |
| 1016 | * freq_out is 0 before any of the uses. */ |
| 1017 | memset(&factors, 0, sizeof(factors)); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1018 | } |
| 1019 | |
| 1020 | wm8400->fll_out = freq_out; |
| 1021 | wm8400->fll_in = freq_in; |
| 1022 | |
| 1023 | /* We *must* disable the FLL before any changes */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1024 | reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1025 | reg &= ~WM8400_FLL_ENA; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1026 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1027 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1028 | reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1029 | reg &= ~WM8400_FLL_OSC_ENA; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1030 | snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1031 | |
Mark Brown | 8aa2df5 | 2009-07-17 21:53:49 +0100 | [diff] [blame] | 1032 | if (!freq_out) |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1033 | return 0; |
| 1034 | |
| 1035 | reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK); |
| 1036 | reg |= WM8400_FLL_FRAC | factors.fratio; |
| 1037 | reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1038 | snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1039 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1040 | snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k); |
| 1041 | snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1042 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1043 | reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4); |
Axel Lin | 1d533de | 2011-10-22 22:48:27 +0800 | [diff] [blame] | 1044 | reg &= ~WM8400_FLL_OUTDIV_MASK; |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1045 | reg |= factors.outdiv; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1046 | snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg); |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1047 | |
| 1048 | return 0; |
| 1049 | } |
| 1050 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1051 | /* |
| 1052 | * Sets ADC and Voice DAC format. |
| 1053 | */ |
| 1054 | static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai, |
| 1055 | unsigned int fmt) |
| 1056 | { |
| 1057 | struct snd_soc_codec *codec = codec_dai->codec; |
| 1058 | u16 audio1, audio3; |
| 1059 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1060 | audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1); |
| 1061 | audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1062 | |
| 1063 | /* set master/slave audio interface */ |
| 1064 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1065 | case SND_SOC_DAIFMT_CBS_CFS: |
| 1066 | audio3 &= ~WM8400_AIF_MSTR1; |
| 1067 | break; |
| 1068 | case SND_SOC_DAIFMT_CBM_CFM: |
| 1069 | audio3 |= WM8400_AIF_MSTR1; |
| 1070 | break; |
| 1071 | default: |
| 1072 | return -EINVAL; |
| 1073 | } |
| 1074 | |
| 1075 | audio1 &= ~WM8400_AIF_FMT_MASK; |
| 1076 | |
| 1077 | /* interface format */ |
| 1078 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1079 | case SND_SOC_DAIFMT_I2S: |
| 1080 | audio1 |= WM8400_AIF_FMT_I2S; |
| 1081 | audio1 &= ~WM8400_AIF_LRCLK_INV; |
| 1082 | break; |
| 1083 | case SND_SOC_DAIFMT_RIGHT_J: |
| 1084 | audio1 |= WM8400_AIF_FMT_RIGHTJ; |
| 1085 | audio1 &= ~WM8400_AIF_LRCLK_INV; |
| 1086 | break; |
| 1087 | case SND_SOC_DAIFMT_LEFT_J: |
| 1088 | audio1 |= WM8400_AIF_FMT_LEFTJ; |
| 1089 | audio1 &= ~WM8400_AIF_LRCLK_INV; |
| 1090 | break; |
| 1091 | case SND_SOC_DAIFMT_DSP_A: |
| 1092 | audio1 |= WM8400_AIF_FMT_DSP; |
| 1093 | audio1 &= ~WM8400_AIF_LRCLK_INV; |
| 1094 | break; |
| 1095 | case SND_SOC_DAIFMT_DSP_B: |
| 1096 | audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV; |
| 1097 | break; |
| 1098 | default: |
| 1099 | return -EINVAL; |
| 1100 | } |
| 1101 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1102 | snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); |
| 1103 | snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1104 | return 0; |
| 1105 | } |
| 1106 | |
| 1107 | static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
| 1108 | int div_id, int div) |
| 1109 | { |
| 1110 | struct snd_soc_codec *codec = codec_dai->codec; |
| 1111 | u16 reg; |
| 1112 | |
| 1113 | switch (div_id) { |
| 1114 | case WM8400_MCLK_DIV: |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1115 | reg = snd_soc_read(codec, WM8400_CLOCKING_2) & |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1116 | ~WM8400_MCLK_DIV_MASK; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1117 | snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1118 | break; |
| 1119 | case WM8400_DACCLK_DIV: |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1120 | reg = snd_soc_read(codec, WM8400_CLOCKING_2) & |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1121 | ~WM8400_DAC_CLKDIV_MASK; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1122 | snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1123 | break; |
| 1124 | case WM8400_ADCCLK_DIV: |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1125 | reg = snd_soc_read(codec, WM8400_CLOCKING_2) & |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1126 | ~WM8400_ADC_CLKDIV_MASK; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1127 | snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1128 | break; |
| 1129 | case WM8400_BCLK_DIV: |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1130 | reg = snd_soc_read(codec, WM8400_CLOCKING_1) & |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1131 | ~WM8400_BCLK_DIV_MASK; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1132 | snd_soc_write(codec, WM8400_CLOCKING_1, reg | div); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1133 | break; |
| 1134 | default: |
| 1135 | return -EINVAL; |
| 1136 | } |
| 1137 | |
| 1138 | return 0; |
| 1139 | } |
| 1140 | |
| 1141 | /* |
| 1142 | * Set PCM DAI bit size and sample rate. |
| 1143 | */ |
| 1144 | static int wm8400_hw_params(struct snd_pcm_substream *substream, |
| 1145 | struct snd_pcm_hw_params *params, |
| 1146 | struct snd_soc_dai *dai) |
| 1147 | { |
Mark Brown | e6968a1 | 2012-04-04 15:58:16 +0100 | [diff] [blame] | 1148 | struct snd_soc_codec *codec = dai->codec; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1149 | u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1150 | |
| 1151 | audio1 &= ~WM8400_AIF_WL_MASK; |
| 1152 | /* bit size */ |
| 1153 | switch (params_format(params)) { |
| 1154 | case SNDRV_PCM_FORMAT_S16_LE: |
| 1155 | break; |
| 1156 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 1157 | audio1 |= WM8400_AIF_WL_20BITS; |
| 1158 | break; |
| 1159 | case SNDRV_PCM_FORMAT_S24_LE: |
| 1160 | audio1 |= WM8400_AIF_WL_24BITS; |
| 1161 | break; |
| 1162 | case SNDRV_PCM_FORMAT_S32_LE: |
| 1163 | audio1 |= WM8400_AIF_WL_32BITS; |
| 1164 | break; |
| 1165 | } |
| 1166 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1167 | snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1168 | return 0; |
| 1169 | } |
| 1170 | |
| 1171 | static int wm8400_mute(struct snd_soc_dai *dai, int mute) |
| 1172 | { |
| 1173 | struct snd_soc_codec *codec = dai->codec; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1174 | u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1175 | |
| 1176 | if (mute) |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1177 | snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1178 | else |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1179 | snd_soc_write(codec, WM8400_DAC_CTRL, val); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1180 | |
| 1181 | return 0; |
| 1182 | } |
| 1183 | |
| 1184 | /* TODO: set bias for best performance at standby */ |
| 1185 | static int wm8400_set_bias_level(struct snd_soc_codec *codec, |
| 1186 | enum snd_soc_bias_level level) |
| 1187 | { |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 1188 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1189 | u16 val; |
| 1190 | int ret; |
| 1191 | |
| 1192 | switch (level) { |
| 1193 | case SND_SOC_BIAS_ON: |
| 1194 | break; |
| 1195 | |
| 1196 | case SND_SOC_BIAS_PREPARE: |
| 1197 | /* VMID=2*50k */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1198 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1199 | ~WM8400_VMID_MODE_MASK; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1200 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1201 | break; |
| 1202 | |
| 1203 | case SND_SOC_BIAS_STANDBY: |
Liam Girdwood | ce6120c | 2010-11-05 15:53:46 +0200 | [diff] [blame] | 1204 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1205 | ret = regulator_bulk_enable(ARRAY_SIZE(power), |
| 1206 | &power[0]); |
| 1207 | if (ret != 0) { |
| 1208 | dev_err(wm8400->wm8400->dev, |
| 1209 | "Failed to enable regulators: %d\n", |
| 1210 | ret); |
| 1211 | return ret; |
| 1212 | } |
| 1213 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1214 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1215 | WM8400_CODEC_ENA | WM8400_SYSCLK_ENA); |
| 1216 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1217 | /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1218 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1219 | WM8400_BUFDCOPEN | WM8400_POBCTRL); |
| 1220 | |
Mark Brown | e3598f6 | 2009-03-18 15:19:10 +0000 | [diff] [blame] | 1221 | msleep(50); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1222 | |
| 1223 | /* Enable VREF & VMID at 2x50k */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1224 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1225 | val |= 0x2 | WM8400_VREF_ENA; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1226 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1227 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1228 | /* Enable BUFIOEN */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1229 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1230 | WM8400_BUFDCOPEN | WM8400_POBCTRL | |
| 1231 | WM8400_BUFIOEN); |
| 1232 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1233 | /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1234 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1235 | } |
| 1236 | |
| 1237 | /* VMID=2*300k */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1238 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1239 | ~WM8400_VMID_MODE_MASK; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1240 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1241 | break; |
| 1242 | |
| 1243 | case SND_SOC_BIAS_OFF: |
| 1244 | /* Enable POBCTRL and SOFT_ST */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1245 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1246 | WM8400_POBCTRL | WM8400_BUFIOEN); |
| 1247 | |
| 1248 | /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1249 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1250 | WM8400_BUFDCOPEN | WM8400_POBCTRL | |
| 1251 | WM8400_BUFIOEN); |
| 1252 | |
| 1253 | /* mute DAC */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1254 | val = snd_soc_read(codec, WM8400_DAC_CTRL); |
| 1255 | snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1256 | |
| 1257 | /* Enable any disabled outputs */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1258 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1259 | val |= WM8400_SPK_ENA | WM8400_OUT3_ENA | |
| 1260 | WM8400_OUT4_ENA | WM8400_LOUT_ENA | |
| 1261 | WM8400_ROUT_ENA; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1262 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1263 | |
| 1264 | /* Disable VMID */ |
| 1265 | val &= ~WM8400_VMID_MODE_MASK; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1266 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1267 | |
| 1268 | msleep(300); |
| 1269 | |
| 1270 | /* Enable all output discharge bits */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1271 | snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1272 | WM8400_DIS_RLINE | WM8400_DIS_OUT3 | |
| 1273 | WM8400_DIS_OUT4 | WM8400_DIS_LOUT | |
| 1274 | WM8400_DIS_ROUT); |
| 1275 | |
| 1276 | /* Disable VREF */ |
| 1277 | val &= ~WM8400_VREF_ENA; |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1278 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1279 | |
| 1280 | /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1281 | snd_soc_write(codec, WM8400_ANTIPOP2, 0x0); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1282 | |
| 1283 | ret = regulator_bulk_disable(ARRAY_SIZE(power), |
| 1284 | &power[0]); |
| 1285 | if (ret != 0) |
| 1286 | return ret; |
| 1287 | |
| 1288 | break; |
| 1289 | } |
| 1290 | |
Liam Girdwood | ce6120c | 2010-11-05 15:53:46 +0200 | [diff] [blame] | 1291 | codec->dapm.bias_level = level; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1292 | return 0; |
| 1293 | } |
| 1294 | |
| 1295 | #define WM8400_RATES SNDRV_PCM_RATE_8000_96000 |
| 1296 | |
| 1297 | #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
| 1298 | SNDRV_PCM_FMTBIT_S24_LE) |
| 1299 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 1300 | static const struct snd_soc_dai_ops wm8400_dai_ops = { |
Mark Brown | 65ec1cd | 2009-03-11 16:51:31 +0000 | [diff] [blame] | 1301 | .hw_params = wm8400_hw_params, |
| 1302 | .digital_mute = wm8400_mute, |
| 1303 | .set_fmt = wm8400_set_dai_fmt, |
| 1304 | .set_clkdiv = wm8400_set_dai_clkdiv, |
| 1305 | .set_sysclk = wm8400_set_dai_sysclk, |
Mark Brown | e8523b6 | 2009-03-18 18:28:01 +0000 | [diff] [blame] | 1306 | .set_pll = wm8400_set_dai_pll, |
Mark Brown | 65ec1cd | 2009-03-11 16:51:31 +0000 | [diff] [blame] | 1307 | }; |
| 1308 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1309 | /* |
| 1310 | * The WM8400 supports 2 different and mutually exclusive DAI |
| 1311 | * configurations. |
| 1312 | * |
| 1313 | * 1. ADC/DAC on Primary Interface |
| 1314 | * 2. ADC on Primary Interface/DAC on secondary |
| 1315 | */ |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1316 | static struct snd_soc_dai_driver wm8400_dai = { |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1317 | /* ADC/DAC on primary */ |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1318 | .name = "wm8400-hifi", |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1319 | .playback = { |
| 1320 | .stream_name = "Playback", |
| 1321 | .channels_min = 1, |
| 1322 | .channels_max = 2, |
| 1323 | .rates = WM8400_RATES, |
| 1324 | .formats = WM8400_FORMATS, |
| 1325 | }, |
| 1326 | .capture = { |
| 1327 | .stream_name = "Capture", |
| 1328 | .channels_min = 1, |
| 1329 | .channels_max = 2, |
| 1330 | .rates = WM8400_RATES, |
| 1331 | .formats = WM8400_FORMATS, |
| 1332 | }, |
Mark Brown | 65ec1cd | 2009-03-11 16:51:31 +0000 | [diff] [blame] | 1333 | .ops = &wm8400_dai_ops, |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1334 | }; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1335 | |
Lars-Peter Clausen | 84b315e | 2011-12-02 10:18:28 +0100 | [diff] [blame] | 1336 | static int wm8400_suspend(struct snd_soc_codec *codec) |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1337 | { |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1338 | wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF); |
| 1339 | |
| 1340 | return 0; |
| 1341 | } |
| 1342 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1343 | static int wm8400_resume(struct snd_soc_codec *codec) |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1344 | { |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1345 | wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1346 | |
| 1347 | return 0; |
| 1348 | } |
| 1349 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1350 | static void wm8400_probe_deferred(struct work_struct *work) |
| 1351 | { |
| 1352 | struct wm8400_priv *priv = container_of(work, struct wm8400_priv, |
| 1353 | work); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1354 | struct snd_soc_codec *codec = priv->codec; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1355 | |
| 1356 | /* charge output caps */ |
| 1357 | wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1358 | } |
| 1359 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1360 | static int wm8400_codec_probe(struct snd_soc_codec *codec) |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1361 | { |
Samuel Ortiz | e45be4b | 2011-05-11 10:44:36 +0200 | [diff] [blame] | 1362 | struct wm8400 *wm8400 = dev_get_platdata(codec->dev); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1363 | struct wm8400_priv *priv; |
| 1364 | int ret; |
| 1365 | u16 reg; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1366 | |
Mark Brown | b903c0e | 2011-12-03 11:41:27 +0000 | [diff] [blame] | 1367 | priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv), |
| 1368 | GFP_KERNEL); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1369 | if (priv == NULL) |
| 1370 | return -ENOMEM; |
| 1371 | |
Mark Brown | b2c812e | 2010-04-14 15:35:19 +0900 | [diff] [blame] | 1372 | snd_soc_codec_set_drvdata(codec, priv); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1373 | codec->control_data = priv->wm8400 = wm8400; |
| 1374 | priv->codec = codec; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1375 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1376 | ret = regulator_bulk_get(wm8400->dev, |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1377 | ARRAY_SIZE(power), &power[0]); |
| 1378 | if (ret != 0) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1379 | dev_err(codec->dev, "Failed to get regulators: %d\n", ret); |
Mark Brown | b903c0e | 2011-12-03 11:41:27 +0000 | [diff] [blame] | 1380 | return ret; |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1381 | } |
| 1382 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1383 | INIT_WORK(&priv->work, wm8400_probe_deferred); |
| 1384 | |
| 1385 | wm8400_codec_reset(codec); |
| 1386 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1387 | reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
| 1388 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1389 | |
| 1390 | /* Latch volume update bits */ |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1391 | reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME); |
| 1392 | snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME, |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1393 | reg & WM8400_IPVU); |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1394 | reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME); |
| 1395 | snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1396 | reg & WM8400_IPVU); |
| 1397 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1398 | snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); |
| 1399 | snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1400 | |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1401 | if (!schedule_work(&priv->work)) { |
| 1402 | ret = -EINVAL; |
| 1403 | goto err_regulator; |
| 1404 | } |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1405 | return 0; |
| 1406 | |
| 1407 | err_regulator: |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1408 | regulator_bulk_free(ARRAY_SIZE(power), power); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1409 | return ret; |
| 1410 | } |
| 1411 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1412 | static int wm8400_codec_remove(struct snd_soc_codec *codec) |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1413 | { |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1414 | u16 reg; |
| 1415 | |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1416 | reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
| 1417 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1418 | reg & (~WM8400_CODEC_ENA)); |
| 1419 | |
| 1420 | regulator_bulk_free(ARRAY_SIZE(power), power); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1421 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1422 | return 0; |
| 1423 | } |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1424 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1425 | static struct snd_soc_codec_driver soc_codec_dev_wm8400 = { |
| 1426 | .probe = wm8400_codec_probe, |
| 1427 | .remove = wm8400_codec_remove, |
| 1428 | .suspend = wm8400_suspend, |
| 1429 | .resume = wm8400_resume, |
Mark Brown | 5fa87d3 | 2012-04-05 22:05:18 +0100 | [diff] [blame] | 1430 | .read = snd_soc_read, |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1431 | .write = wm8400_write, |
| 1432 | .set_bias_level = wm8400_set_bias_level, |
Mark Brown | b4505ab | 2011-12-03 11:34:34 +0000 | [diff] [blame] | 1433 | |
| 1434 | .controls = wm8400_snd_controls, |
| 1435 | .num_controls = ARRAY_SIZE(wm8400_snd_controls), |
| 1436 | .dapm_widgets = wm8400_dapm_widgets, |
| 1437 | .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets), |
| 1438 | .dapm_routes = wm8400_dapm_routes, |
| 1439 | .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes), |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1440 | }; |
| 1441 | |
| 1442 | static int __devinit wm8400_probe(struct platform_device *pdev) |
| 1443 | { |
| 1444 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400, |
| 1445 | &wm8400_dai, 1); |
| 1446 | } |
| 1447 | |
| 1448 | static int __devexit wm8400_remove(struct platform_device *pdev) |
| 1449 | { |
| 1450 | snd_soc_unregister_codec(&pdev->dev); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1451 | return 0; |
| 1452 | } |
| 1453 | |
| 1454 | static struct platform_driver wm8400_codec_driver = { |
| 1455 | .driver = { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1456 | .name = "wm8400-codec", |
| 1457 | .owner = THIS_MODULE, |
| 1458 | }, |
| 1459 | .probe = wm8400_probe, |
| 1460 | .remove = __devexit_p(wm8400_remove), |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1461 | }; |
| 1462 | |
Mark Brown | 5bbcc3c | 2011-11-23 22:52:08 +0000 | [diff] [blame] | 1463 | module_platform_driver(wm8400_codec_driver); |
Mark Brown | aaf1e17 | 2009-03-10 10:55:15 +0000 | [diff] [blame] | 1464 | |
| 1465 | MODULE_DESCRIPTION("ASoC WM8400 driver"); |
| 1466 | MODULE_AUTHOR("Mark Brown"); |
| 1467 | MODULE_LICENSE("GPL"); |
| 1468 | MODULE_ALIAS("platform:wm8400-codec"); |