Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 1 | /* |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 2 | * arch/arm/mach-orion5x/pci.c |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 3 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 4 | * PCI and PCIe functions for Marvell Orion System On Chip |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 5 | * |
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 7 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 10 | * warranty of any kind, whether express or implied. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/pci.h> |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 15 | #include <linux/mbus.h> |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 16 | #include <asm/mach/pci.h> |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 17 | #include <asm/plat-orion/pcie.h> |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 18 | #include "common.h" |
| 19 | |
| 20 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 21 | * Orion has one PCIe controller and one PCI controller. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 22 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 23 | * Note1: The local PCIe bus number is '0'. The local PCI bus number |
| 24 | * follows the scanned PCIe bridged busses, if any. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 25 | * |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 26 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 27 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on |
| 28 | * device bus, Orion registers, etc. However this code only enable the |
| 29 | * access to DDR banks. |
| 30 | ****************************************************************************/ |
| 31 | |
| 32 | |
| 33 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 34 | * PCIe controller |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 35 | ****************************************************************************/ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 36 | #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 37 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 38 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 39 | { |
| 40 | *dev = orion_pcie_dev_id(PCIE_BASE); |
| 41 | *rev = orion_pcie_rev(PCIE_BASE); |
| 42 | } |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 43 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 44 | static int pcie_valid_config(int bus, int dev) |
| 45 | { |
| 46 | /* |
| 47 | * Don't go out when trying to access -- |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 48 | * 1. nonexisting device on local bus |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 49 | * 2. where there's no device connected (no link) |
| 50 | */ |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 51 | if (bus == 0 && dev == 0) |
| 52 | return 1; |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 53 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 54 | if (!orion_pcie_link_up(PCIE_BASE)) |
| 55 | return 0; |
| 56 | |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 57 | if (bus == 0 && dev != 1) |
| 58 | return 0; |
| 59 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 60 | return 1; |
| 61 | } |
| 62 | |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 63 | |
| 64 | /* |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 65 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 66 | * and then reading the PCIE_CONF_DATA register. Need to make sure these |
| 67 | * transactions are atomic. |
| 68 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 69 | static DEFINE_SPINLOCK(orion5x_pcie_lock); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 70 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 71 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
| 72 | int size, u32 *val) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 73 | { |
| 74 | unsigned long flags; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 75 | int ret; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 76 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 77 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 78 | *val = 0xffffffff; |
| 79 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 80 | } |
| 81 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 82 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 83 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 84 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 85 | |
| 86 | return ret; |
| 87 | } |
| 88 | |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 89 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, |
| 90 | int where, int size, u32 *val) |
| 91 | { |
| 92 | int ret; |
| 93 | |
| 94 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
| 95 | *val = 0xffffffff; |
| 96 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * We only support access to the non-extended configuration |
| 101 | * space when using the WA access method (or we would have to |
| 102 | * sacrifice 256M of CPU virtual address space.) |
| 103 | */ |
| 104 | if (where >= 0x100) { |
| 105 | *val = 0xffffffff; |
| 106 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 107 | } |
| 108 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 109 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 110 | bus, devfn, where, size, val); |
| 111 | |
| 112 | return ret; |
| 113 | } |
| 114 | |
| 115 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
| 116 | int where, int size, u32 val) |
| 117 | { |
| 118 | unsigned long flags; |
| 119 | int ret; |
| 120 | |
| 121 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
| 122 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 123 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 124 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 125 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 126 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 127 | |
| 128 | return ret; |
| 129 | } |
| 130 | |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 131 | static struct pci_ops pcie_ops = { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 132 | .read = pcie_rd_conf, |
| 133 | .write = pcie_wr_conf, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | |
Lennert Buytenhek | a998427 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 137 | static int __init pcie_setup(struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 138 | { |
| 139 | struct resource *res; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 140 | int dev; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 141 | |
| 142 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 143 | * Generic PCIe unit setup. |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 144 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 145 | orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 146 | |
| 147 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 148 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
| 149 | * read transaction workaround. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 150 | */ |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 151 | dev = orion_pcie_dev_id(PCIE_BASE); |
| 152 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { |
| 153 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " |
| 154 | "read transaction workaround\n"); |
Lennert Buytenhek | 386a048 | 2008-05-10 17:01:18 +0200 | [diff] [blame^] | 155 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
| 156 | ORION5X_PCIE_WA_SIZE); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 157 | pcie_ops.read = pcie_rd_conf_wa; |
| 158 | } |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 159 | |
| 160 | /* |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 161 | * Request resources. |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 162 | */ |
| 163 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); |
| 164 | if (!res) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 165 | panic("pcie_setup unable to alloc resources"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * IORESOURCE_IO |
| 169 | */ |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 170 | res[0].name = "PCIe I/O Space"; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 171 | res[0].flags = IORESOURCE_IO; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 172 | res[0].start = ORION5X_PCIE_IO_BUS_BASE; |
| 173 | res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 174 | if (request_resource(&ioport_resource, &res[0])) |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 175 | panic("Request PCIe IO resource failed\n"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 176 | sys->resource[0] = &res[0]; |
| 177 | |
| 178 | /* |
| 179 | * IORESOURCE_MEM |
| 180 | */ |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 181 | res[1].name = "PCIe Memory Space"; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 182 | res[1].flags = IORESOURCE_MEM; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 183 | res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; |
| 184 | res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 185 | if (request_resource(&iomem_resource, &res[1])) |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 186 | panic("Request PCIe Memory resource failed\n"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 187 | sys->resource[1] = &res[1]; |
| 188 | |
| 189 | sys->resource[2] = NULL; |
| 190 | sys->io_offset = 0; |
| 191 | |
| 192 | return 1; |
| 193 | } |
| 194 | |
| 195 | /***************************************************************************** |
| 196 | * PCI controller |
| 197 | ****************************************************************************/ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 198 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
| 199 | #define PCI_CMD ORION5X_PCI_REG(0xc00) |
| 200 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) |
| 201 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) |
| 202 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 203 | |
| 204 | /* |
| 205 | * PCI_MODE bits |
| 206 | */ |
| 207 | #define PCI_MODE_64BIT (1 << 2) |
| 208 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) |
| 209 | |
| 210 | /* |
| 211 | * PCI_CMD bits |
| 212 | */ |
| 213 | #define PCI_CMD_HOST_REORDER (1 << 29) |
| 214 | |
| 215 | /* |
| 216 | * PCI_P2P_CONF bits |
| 217 | */ |
| 218 | #define PCI_P2P_BUS_OFFS 16 |
| 219 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) |
| 220 | #define PCI_P2P_DEV_OFFS 24 |
| 221 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) |
| 222 | |
| 223 | /* |
| 224 | * PCI_CONF_ADDR bits |
| 225 | */ |
| 226 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) |
| 227 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) |
| 228 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) |
| 229 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) |
| 230 | #define PCI_CONF_ADDR_EN (1 << 31) |
| 231 | |
| 232 | /* |
| 233 | * Internal configuration space |
| 234 | */ |
| 235 | #define PCI_CONF_FUNC_STAT_CMD 0 |
| 236 | #define PCI_CONF_REG_STAT_CMD 4 |
| 237 | #define PCIX_STAT 0x64 |
| 238 | #define PCIX_STAT_BUS_OFFS 8 |
| 239 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) |
| 240 | |
| 241 | /* |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 242 | * PCI Address Decode Windows registers |
| 243 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 244 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ |
Lennert Buytenhek | e7068ad | 2008-05-10 16:30:01 +0200 | [diff] [blame] | 245 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ |
| 246 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ |
| 247 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) |
| 248 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ |
| 249 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ |
| 250 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ |
| 251 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 252 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) |
| 253 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 254 | |
| 255 | /* |
| 256 | * PCI configuration helpers for BAR settings |
| 257 | */ |
| 258 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) |
| 259 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) |
| 260 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) |
| 261 | |
| 262 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 263 | * PCI config cycles are done by programming the PCI_CONF_ADDR register |
| 264 | * and then reading the PCI_CONF_DATA register. Need to make sure these |
| 265 | * transactions are atomic. |
| 266 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 267 | static DEFINE_SPINLOCK(orion5x_pci_lock); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 268 | |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 269 | static int orion5x_pci_local_bus_nr(void) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 270 | { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 271 | u32 conf = orion5x_read(PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 272 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); |
| 273 | } |
| 274 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 275 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 276 | u32 where, u32 size, u32 *val) |
| 277 | { |
| 278 | unsigned long flags; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 279 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 280 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 281 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 282 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
| 283 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); |
| 284 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 285 | *val = orion5x_read(PCI_CONF_DATA); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 286 | |
| 287 | if (size == 1) |
| 288 | *val = (*val >> (8*(where & 0x3))) & 0xff; |
| 289 | else if (size == 2) |
| 290 | *val = (*val >> (8*(where & 0x3))) & 0xffff; |
| 291 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 292 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 293 | |
| 294 | return PCIBIOS_SUCCESSFUL; |
| 295 | } |
| 296 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 297 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 298 | u32 where, u32 size, u32 val) |
| 299 | { |
| 300 | unsigned long flags; |
| 301 | int ret = PCIBIOS_SUCCESSFUL; |
| 302 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 303 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 304 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 305 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 306 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
| 307 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); |
| 308 | |
| 309 | if (size == 4) { |
| 310 | __raw_writel(val, PCI_CONF_DATA); |
| 311 | } else if (size == 2) { |
| 312 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); |
| 313 | } else if (size == 1) { |
| 314 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); |
| 315 | } else { |
| 316 | ret = PCIBIOS_BAD_REGISTER_NUMBER; |
| 317 | } |
| 318 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 319 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 320 | |
| 321 | return ret; |
| 322 | } |
| 323 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 324 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 325 | int where, int size, u32 *val) |
| 326 | { |
| 327 | /* |
| 328 | * Don't go out for local device |
| 329 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 330 | if (bus->number == orion5x_pci_local_bus_nr() && |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 331 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 332 | *val = 0xffffffff; |
| 333 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 334 | } |
| 335 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 336 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 337 | PCI_FUNC(devfn), where, size, val); |
| 338 | } |
| 339 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 340 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 341 | int where, int size, u32 val) |
| 342 | { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 343 | if (bus->number == orion5x_pci_local_bus_nr() && |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 344 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 345 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 346 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 347 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 348 | PCI_FUNC(devfn), where, size, val); |
| 349 | } |
| 350 | |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 351 | static struct pci_ops pci_ops = { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 352 | .read = orion5x_pci_rd_conf, |
| 353 | .write = orion5x_pci_wr_conf, |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 354 | }; |
| 355 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 356 | static void __init orion5x_pci_set_bus_nr(int nr) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 357 | { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 358 | u32 p2p = orion5x_read(PCI_P2P_CONF); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 359 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 360 | if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 361 | /* |
| 362 | * PCI-X mode |
| 363 | */ |
| 364 | u32 pcix_status, bus, dev; |
| 365 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; |
| 366 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 367 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 368 | pcix_status &= ~PCIX_STAT_BUS_MASK; |
| 369 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 370 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 371 | } else { |
| 372 | /* |
| 373 | * PCI Conventional mode |
| 374 | */ |
| 375 | p2p &= ~PCI_P2P_BUS_MASK; |
| 376 | p2p |= (nr << PCI_P2P_BUS_OFFS); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 377 | orion5x_write(PCI_P2P_CONF, p2p); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 378 | } |
| 379 | } |
| 380 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 381 | static void __init orion5x_pci_master_slave_enable(void) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 382 | { |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 383 | int bus_nr, func, reg; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 384 | u32 val; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 385 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 386 | bus_nr = orion5x_pci_local_bus_nr(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 387 | func = PCI_CONF_FUNC_STAT_CMD; |
| 388 | reg = PCI_CONF_REG_STAT_CMD; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 389 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 390 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 391 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 392 | } |
| 393 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 394 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 395 | { |
| 396 | u32 win_enable; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 397 | int bus; |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 398 | int i; |
| 399 | |
| 400 | /* |
| 401 | * First, disable windows. |
| 402 | */ |
| 403 | win_enable = 0xffffffff; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 404 | orion5x_write(PCI_BAR_ENABLE, win_enable); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 405 | |
| 406 | /* |
| 407 | * Setup windows for DDR banks. |
| 408 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 409 | bus = orion5x_pci_local_bus_nr(); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 410 | |
| 411 | for (i = 0; i < dram->num_cs; i++) { |
| 412 | struct mbus_dram_window *cs = dram->cs + i; |
| 413 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); |
| 414 | u32 reg; |
| 415 | u32 val; |
| 416 | |
| 417 | /* |
| 418 | * Write DRAM bank base address register. |
| 419 | */ |
| 420 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 421 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 422 | val = (cs->base & 0xfffff000) | (val & 0xfff); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 423 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 424 | |
| 425 | /* |
| 426 | * Write DRAM bank size register. |
| 427 | */ |
| 428 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 429 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); |
| 430 | orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 431 | (cs->size - 1) & 0xfffff000); |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 432 | orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 433 | cs->base & 0xfffff000); |
| 434 | |
| 435 | /* |
| 436 | * Enable decode window for this chip select. |
| 437 | */ |
| 438 | win_enable &= ~(1 << cs->cs_index); |
| 439 | } |
| 440 | |
| 441 | /* |
| 442 | * Re-enable decode windows. |
| 443 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 444 | orion5x_write(PCI_BAR_ENABLE, win_enable); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 445 | |
| 446 | /* |
| 447 | * Disable automatic update of address remaping when writing to BARs. |
| 448 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 449 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 450 | } |
| 451 | |
Lennert Buytenhek | a998427 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 452 | static int __init pci_setup(struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 453 | { |
| 454 | struct resource *res; |
| 455 | |
| 456 | /* |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 457 | * Point PCI unit MBUS decode windows to DRAM space. |
| 458 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 459 | orion5x_setup_pci_wins(&orion5x_mbus_dram_info); |
Lennert Buytenhek | 1f2223b | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 460 | |
| 461 | /* |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 462 | * Master + Slave enable |
| 463 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 464 | orion5x_pci_master_slave_enable(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 465 | |
| 466 | /* |
| 467 | * Force ordering |
| 468 | */ |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 469 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 470 | |
| 471 | /* |
| 472 | * Request resources |
| 473 | */ |
| 474 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); |
| 475 | if (!res) |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 476 | panic("pci_setup unable to alloc resources"); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 477 | |
| 478 | /* |
| 479 | * IORESOURCE_IO |
| 480 | */ |
| 481 | res[0].name = "PCI I/O Space"; |
| 482 | res[0].flags = IORESOURCE_IO; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 483 | res[0].start = ORION5X_PCI_IO_BUS_BASE; |
| 484 | res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 485 | if (request_resource(&ioport_resource, &res[0])) |
| 486 | panic("Request PCI IO resource failed\n"); |
| 487 | sys->resource[0] = &res[0]; |
| 488 | |
| 489 | /* |
| 490 | * IORESOURCE_MEM |
| 491 | */ |
| 492 | res[1].name = "PCI Memory Space"; |
| 493 | res[1].flags = IORESOURCE_MEM; |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 494 | res[1].start = ORION5X_PCI_MEM_PHYS_BASE; |
| 495 | res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 496 | if (request_resource(&iomem_resource, &res[1])) |
| 497 | panic("Request PCI Memory resource failed\n"); |
| 498 | sys->resource[1] = &res[1]; |
| 499 | |
| 500 | sys->resource[2] = NULL; |
| 501 | sys->io_offset = 0; |
| 502 | |
| 503 | return 1; |
| 504 | } |
| 505 | |
| 506 | |
| 507 | /***************************************************************************** |
Lennert Buytenhek | 159ffb3 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 508 | * General PCIe + PCI |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 509 | ****************************************************************************/ |
Lennert Buytenhek | d50c60a | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 510 | static void __devinit rc_pci_fixup(struct pci_dev *dev) |
| 511 | { |
| 512 | /* |
| 513 | * Prevent enumeration of root complex. |
| 514 | */ |
| 515 | if (dev->bus->parent == NULL && dev->devfn == 0) { |
| 516 | int i; |
| 517 | |
| 518 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 519 | dev->resource[i].start = 0; |
| 520 | dev->resource[i].end = 0; |
| 521 | dev->resource[i].flags = 0; |
| 522 | } |
| 523 | } |
| 524 | } |
| 525 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); |
| 526 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 527 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 528 | { |
| 529 | int ret = 0; |
| 530 | |
| 531 | if (nr == 0) { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 532 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
| 533 | ret = pcie_setup(sys); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 534 | } else if (nr == 1) { |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 535 | orion5x_pci_set_bus_nr(sys->busnr); |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 536 | ret = pci_setup(sys); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 537 | } |
| 538 | |
| 539 | return ret; |
| 540 | } |
| 541 | |
Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 542 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 543 | { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 544 | struct pci_bus *bus; |
| 545 | |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 546 | if (nr == 0) { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 547 | bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 548 | } else if (nr == 1) { |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 549 | bus = pci_scan_bus(sys->busnr, &pci_ops, sys); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 550 | } else { |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 551 | bus = NULL; |
Lennert Buytenhek | abc0197 | 2008-03-27 14:51:40 -0400 | [diff] [blame] | 552 | BUG(); |
Tzachi Perelstein | 038ee08 | 2007-10-23 15:14:42 -0400 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | return bus; |
| 556 | } |
Lennert Buytenhek | 92b913b | 2008-04-25 16:28:33 -0400 | [diff] [blame] | 557 | |
| 558 | int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 559 | { |
| 560 | int bus = dev->bus->number; |
| 561 | |
| 562 | /* |
| 563 | * PCIe endpoint? |
| 564 | */ |
| 565 | if (bus < orion5x_pci_local_bus_nr()) |
| 566 | return IRQ_ORION5X_PCIE0_INT; |
| 567 | |
| 568 | return -1; |
| 569 | } |