Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 3 | * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
Terje Bergstrom | 4231c6b | 2013-03-22 16:34:05 +0200 | [diff] [blame] | 10 | #ifndef HOST1X_DRM_H |
| 11 | #define HOST1X_DRM_H 1 |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 12 | |
| 13 | #include <drm/drmP.h> |
| 14 | #include <drm/drm_crtc_helper.h> |
| 15 | #include <drm/drm_edid.h> |
| 16 | #include <drm/drm_fb_helper.h> |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 17 | #include <drm/drm_fixed.h> |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 18 | #include <uapi/drm/tegra_drm.h> |
| 19 | |
| 20 | #include "host1x.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 21 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 22 | struct tegra_fb { |
| 23 | struct drm_framebuffer base; |
| 24 | struct tegra_bo **planes; |
| 25 | unsigned int num_planes; |
| 26 | }; |
| 27 | |
| 28 | struct tegra_fbdev { |
| 29 | struct drm_fb_helper base; |
| 30 | struct tegra_fb *fb; |
| 31 | }; |
| 32 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame^] | 33 | struct tegra_drm { |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 34 | struct drm_device *drm; |
| 35 | struct device *dev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 36 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame^] | 37 | struct mutex subdevs_lock; |
| 38 | struct list_head subdevs; |
| 39 | struct list_head active; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 40 | |
| 41 | struct mutex clients_lock; |
| 42 | struct list_head clients; |
| 43 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 44 | struct tegra_fbdev *fbdev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | struct host1x_client; |
| 48 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 49 | struct host1x_drm_context { |
| 50 | struct host1x_client *client; |
| 51 | struct host1x_channel *channel; |
| 52 | struct list_head list; |
| 53 | }; |
| 54 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 55 | struct host1x_client_ops { |
| 56 | int (*drm_init)(struct host1x_client *client, struct drm_device *drm); |
| 57 | int (*drm_exit)(struct host1x_client *client); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 58 | int (*open_channel)(struct host1x_client *client, |
| 59 | struct host1x_drm_context *context); |
| 60 | void (*close_channel)(struct host1x_drm_context *context); |
| 61 | int (*submit)(struct host1x_drm_context *context, |
| 62 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 63 | struct drm_file *file); |
| 64 | }; |
| 65 | |
| 66 | struct host1x_drm_file { |
| 67 | struct list_head contexts; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | struct host1x_client { |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame^] | 71 | struct tegra_drm *tegra; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 72 | struct device *dev; |
| 73 | |
| 74 | const struct host1x_client_ops *ops; |
| 75 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 76 | enum host1x_class class; |
| 77 | struct host1x_channel *channel; |
| 78 | |
| 79 | struct host1x_syncpt **syncpts; |
| 80 | unsigned int num_syncpts; |
| 81 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 82 | struct list_head list; |
| 83 | }; |
| 84 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame^] | 85 | extern int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); |
| 86 | extern int tegra_drm_exit(struct tegra_drm *tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 87 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame^] | 88 | extern int host1x_register_client(struct tegra_drm *tegra, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 89 | struct host1x_client *client); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame^] | 90 | extern int host1x_unregister_client(struct tegra_drm *tegra, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 91 | struct host1x_client *client); |
| 92 | |
| 93 | struct tegra_output; |
| 94 | |
| 95 | struct tegra_dc { |
| 96 | struct host1x_client client; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 97 | struct device *dev; |
Thierry Reding | d18d303 | 2013-09-26 16:09:19 +0200 | [diff] [blame] | 98 | spinlock_t lock; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 99 | |
| 100 | struct drm_crtc base; |
| 101 | int pipe; |
| 102 | |
| 103 | struct clk *clk; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 104 | void __iomem *regs; |
| 105 | int irq; |
| 106 | |
| 107 | struct tegra_output *rgb; |
| 108 | |
| 109 | struct list_head list; |
| 110 | |
| 111 | struct drm_info_list *debugfs_files; |
| 112 | struct drm_minor *minor; |
| 113 | struct dentry *debugfs; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 114 | |
| 115 | /* page-flip handling */ |
| 116 | struct drm_pending_vblank_event *event; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | static inline struct tegra_dc *host1x_client_to_dc(struct host1x_client *client) |
| 120 | { |
| 121 | return container_of(client, struct tegra_dc, client); |
| 122 | } |
| 123 | |
| 124 | static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) |
| 125 | { |
| 126 | return container_of(crtc, struct tegra_dc, base); |
| 127 | } |
| 128 | |
| 129 | static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, |
| 130 | unsigned long reg) |
| 131 | { |
| 132 | writel(value, dc->regs + (reg << 2)); |
| 133 | } |
| 134 | |
| 135 | static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, |
| 136 | unsigned long reg) |
| 137 | { |
| 138 | return readl(dc->regs + (reg << 2)); |
| 139 | } |
| 140 | |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 141 | struct tegra_dc_window { |
| 142 | struct { |
| 143 | unsigned int x; |
| 144 | unsigned int y; |
| 145 | unsigned int w; |
| 146 | unsigned int h; |
| 147 | } src; |
| 148 | struct { |
| 149 | unsigned int x; |
| 150 | unsigned int y; |
| 151 | unsigned int w; |
| 152 | unsigned int h; |
| 153 | } dst; |
| 154 | unsigned int bits_per_pixel; |
| 155 | unsigned int format; |
| 156 | unsigned int stride[2]; |
| 157 | unsigned long base[3]; |
| 158 | }; |
| 159 | |
| 160 | /* from dc.c */ |
| 161 | extern unsigned int tegra_dc_format(uint32_t format); |
| 162 | extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, |
| 163 | const struct tegra_dc_window *window); |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 164 | extern void tegra_dc_enable_vblank(struct tegra_dc *dc); |
| 165 | extern void tegra_dc_disable_vblank(struct tegra_dc *dc); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 166 | extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, |
| 167 | struct drm_file *file); |
Thierry Reding | f34bc78 | 2012-11-04 21:47:13 +0100 | [diff] [blame] | 168 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 169 | struct tegra_output_ops { |
| 170 | int (*enable)(struct tegra_output *output); |
| 171 | int (*disable)(struct tegra_output *output); |
| 172 | int (*setup_clock)(struct tegra_output *output, struct clk *clk, |
| 173 | unsigned long pclk); |
| 174 | int (*check_mode)(struct tegra_output *output, |
| 175 | struct drm_display_mode *mode, |
| 176 | enum drm_mode_status *status); |
| 177 | }; |
| 178 | |
| 179 | enum tegra_output_type { |
| 180 | TEGRA_OUTPUT_RGB, |
Thierry Reding | edec4af | 2012-11-15 21:28:23 +0000 | [diff] [blame] | 181 | TEGRA_OUTPUT_HDMI, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | struct tegra_output { |
| 185 | struct device_node *of_node; |
| 186 | struct device *dev; |
| 187 | |
| 188 | const struct tegra_output_ops *ops; |
| 189 | enum tegra_output_type type; |
| 190 | |
| 191 | struct i2c_adapter *ddc; |
| 192 | const struct edid *edid; |
| 193 | unsigned int hpd_irq; |
| 194 | int hpd_gpio; |
| 195 | |
| 196 | struct drm_encoder encoder; |
| 197 | struct drm_connector connector; |
| 198 | }; |
| 199 | |
| 200 | static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) |
| 201 | { |
| 202 | return container_of(e, struct tegra_output, encoder); |
| 203 | } |
| 204 | |
| 205 | static inline struct tegra_output *connector_to_output(struct drm_connector *c) |
| 206 | { |
| 207 | return container_of(c, struct tegra_output, connector); |
| 208 | } |
| 209 | |
| 210 | static inline int tegra_output_enable(struct tegra_output *output) |
| 211 | { |
| 212 | if (output && output->ops && output->ops->enable) |
| 213 | return output->ops->enable(output); |
| 214 | |
| 215 | return output ? -ENOSYS : -EINVAL; |
| 216 | } |
| 217 | |
| 218 | static inline int tegra_output_disable(struct tegra_output *output) |
| 219 | { |
| 220 | if (output && output->ops && output->ops->disable) |
| 221 | return output->ops->disable(output); |
| 222 | |
| 223 | return output ? -ENOSYS : -EINVAL; |
| 224 | } |
| 225 | |
| 226 | static inline int tegra_output_setup_clock(struct tegra_output *output, |
| 227 | struct clk *clk, unsigned long pclk) |
| 228 | { |
| 229 | if (output && output->ops && output->ops->setup_clock) |
| 230 | return output->ops->setup_clock(output, clk, pclk); |
| 231 | |
| 232 | return output ? -ENOSYS : -EINVAL; |
| 233 | } |
| 234 | |
| 235 | static inline int tegra_output_check_mode(struct tegra_output *output, |
| 236 | struct drm_display_mode *mode, |
| 237 | enum drm_mode_status *status) |
| 238 | { |
| 239 | if (output && output->ops && output->ops->check_mode) |
| 240 | return output->ops->check_mode(output, mode, status); |
| 241 | |
| 242 | return output ? -ENOSYS : -EINVAL; |
| 243 | } |
| 244 | |
| 245 | /* from rgb.c */ |
| 246 | extern int tegra_dc_rgb_probe(struct tegra_dc *dc); |
| 247 | extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); |
| 248 | extern int tegra_dc_rgb_exit(struct tegra_dc *dc); |
| 249 | |
| 250 | /* from output.c */ |
| 251 | extern int tegra_output_parse_dt(struct tegra_output *output); |
| 252 | extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output); |
| 253 | extern int tegra_output_exit(struct tegra_output *output); |
| 254 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 255 | /* from fb.c */ |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 256 | struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, |
| 257 | unsigned int index); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 258 | extern int tegra_drm_fb_init(struct drm_device *drm); |
| 259 | extern void tegra_drm_fb_exit(struct drm_device *drm); |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 260 | extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 261 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 262 | extern struct drm_driver tegra_drm_driver; |
| 263 | |
Terje Bergstrom | 4231c6b | 2013-03-22 16:34:05 +0200 | [diff] [blame] | 264 | #endif /* HOST1X_DRM_H */ |