Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1 | /* |
| 2 | * hdmi.c |
| 3 | * |
| 4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. |
| 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | * Authors: Yong Zhi |
| 7 | * Mythri pk <mythripk@ti.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License version 2 as published by |
| 11 | * the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #define DSS_SUBSYS_NAME "HDMI" |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/mutex.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/string.h> |
Tomi Valkeinen | 24e6289 | 2011-05-23 11:51:18 +0300 | [diff] [blame] | 32 | #include <linux/platform_device.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 33 | #include <linux/pm_runtime.h> |
| 34 | #include <linux/clk.h> |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 35 | #include <video/omapdss.h> |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 36 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 37 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 38 | #include <sound/soc.h> |
| 39 | #include <sound/pcm_params.h> |
| 40 | #endif |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 41 | |
| 42 | #include "dss.h" |
| 43 | #include "hdmi.h" |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 44 | #include "dss_features.h" |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 45 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 46 | #define HDMI_WP 0x0 |
| 47 | #define HDMI_CORE_SYS 0x400 |
| 48 | #define HDMI_CORE_AV 0x900 |
| 49 | #define HDMI_PLLCTRL 0x200 |
| 50 | #define HDMI_PHY 0x300 |
| 51 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 52 | static struct { |
| 53 | struct mutex lock; |
| 54 | struct omap_display_platform_data *pdata; |
| 55 | struct platform_device *pdev; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 56 | struct hdmi_ip_data ip_data; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 57 | int code; |
| 58 | int mode; |
| 59 | u8 edid[HDMI_EDID_MAX_LENGTH]; |
| 60 | u8 edid_set; |
| 61 | bool custom_set; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 62 | |
| 63 | struct clk *sys_clk; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 64 | } hdmi; |
| 65 | |
| 66 | /* |
| 67 | * Logic for the below structure : |
| 68 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. |
| 69 | * There is a correspondence between CEA/VESA timing and code, please |
| 70 | * refer to section 6.3 in HDMI 1.3 specification for timing code. |
| 71 | * |
| 72 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 |
| 73 | * supported CEA and VESA timing values.code_cea corresponds to the CEA |
| 74 | * code, It is used to get the timing from cea_vesa_timing array.Similarly |
| 75 | * with code_vesa. Code_index is used for back mapping, that is once EDID |
| 76 | * is read from the TV, EDID is parsed to find the timing values and then |
| 77 | * map it to corresponding CEA or VESA index. |
| 78 | */ |
| 79 | |
| 80 | static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { |
| 81 | { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0}, |
| 82 | { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1}, |
| 83 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}, |
| 84 | { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0}, |
| 85 | { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0}, |
| 86 | { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0}, |
| 87 | { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0}, |
| 88 | { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1}, |
| 89 | { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1}, |
| 90 | { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1}, |
| 91 | { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0}, |
| 92 | { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0}, |
| 93 | { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1}, |
| 94 | { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0}, |
| 95 | { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1}, |
| 96 | /* VESA From Here */ |
| 97 | { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0}, |
| 98 | { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1}, |
| 99 | { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1}, |
| 100 | { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0}, |
| 101 | { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0}, |
| 102 | { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1}, |
| 103 | { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1}, |
| 104 | { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1}, |
| 105 | { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0}, |
| 106 | { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0}, |
| 107 | { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0}, |
| 108 | { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0}, |
| 109 | { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1}, |
| 110 | { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1}, |
| 111 | { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1}, |
| 112 | { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1}, |
| 113 | { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1}, |
| 114 | { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1}, |
| 115 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1} |
| 116 | }; |
| 117 | |
| 118 | /* |
| 119 | * This is a static mapping array which maps the timing values |
| 120 | * with corresponding CEA / VESA code |
| 121 | */ |
| 122 | static const int code_index[OMAP_HDMI_TIMINGS_NB] = { |
| 123 | 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32, |
| 124 | /* <--15 CEA 17--> vesa*/ |
| 125 | 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A, |
| 126 | 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B |
| 127 | }; |
| 128 | |
| 129 | /* |
| 130 | * This is reverse static mapping which maps the CEA / VESA code |
| 131 | * to the corresponding timing values |
| 132 | */ |
| 133 | static const int code_cea[39] = { |
| 134 | -1, 0, 3, 3, 2, 8, 5, 5, -1, -1, |
| 135 | -1, -1, -1, -1, -1, -1, 9, 10, 10, 1, |
| 136 | 7, 6, 6, -1, -1, -1, -1, -1, -1, 11, |
| 137 | 11, 12, 14, -1, -1, 13, 13, 4, 4 |
| 138 | }; |
| 139 | |
| 140 | static const int code_vesa[85] = { |
| 141 | -1, -1, -1, -1, 15, -1, -1, -1, -1, 16, |
| 142 | -1, -1, -1, -1, 17, -1, 23, -1, -1, -1, |
| 143 | -1, -1, 29, 18, -1, -1, -1, 32, 19, -1, |
| 144 | -1, -1, 21, -1, -1, 22, -1, -1, -1, 20, |
| 145 | -1, 30, 24, -1, -1, -1, -1, 25, -1, -1, |
| 146 | -1, -1, -1, -1, -1, -1, -1, 31, 26, -1, |
| 147 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 148 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 149 | -1, 27, 28, -1, 33}; |
| 150 | |
| 151 | static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; |
| 152 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 153 | static inline void hdmi_write_reg(void __iomem *base_addr, |
| 154 | const struct hdmi_reg idx, u32 val) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 155 | { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 156 | __raw_writel(val, base_addr + idx.idx); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 157 | } |
| 158 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 159 | static inline u32 hdmi_read_reg(void __iomem *base_addr, |
| 160 | const struct hdmi_reg idx) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 161 | { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 162 | return __raw_readl(base_addr + idx.idx); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 163 | } |
| 164 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 165 | static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data) |
| 166 | { |
| 167 | return ip_data->base_wp; |
| 168 | } |
| 169 | |
| 170 | static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data) |
| 171 | { |
| 172 | return ip_data->base_wp + ip_data->phy_offset; |
| 173 | } |
| 174 | |
| 175 | static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data) |
| 176 | { |
| 177 | return ip_data->base_wp + ip_data->pll_offset; |
| 178 | } |
| 179 | |
| 180 | static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data) |
| 181 | { |
| 182 | return ip_data->base_wp + ip_data->core_av_offset; |
| 183 | } |
| 184 | |
| 185 | static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data) |
| 186 | { |
| 187 | return ip_data->base_wp + ip_data->core_sys_offset; |
| 188 | } |
| 189 | |
| 190 | static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, |
| 191 | const struct hdmi_reg idx, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 192 | int b2, int b1, u32 val) |
| 193 | { |
| 194 | u32 t = 0; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 195 | while (val != REG_GET(base_addr, idx, b2, b1)) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 196 | udelay(1); |
| 197 | if (t++ > 10000) |
| 198 | return !val; |
| 199 | } |
| 200 | return val; |
| 201 | } |
| 202 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 203 | static int hdmi_runtime_get(void) |
| 204 | { |
| 205 | int r; |
| 206 | |
| 207 | DSSDBG("hdmi_runtime_get\n"); |
| 208 | |
| 209 | r = pm_runtime_get_sync(&hdmi.pdev->dev); |
| 210 | WARN_ON(r < 0); |
| 211 | return r < 0 ? r : 0; |
| 212 | } |
| 213 | |
| 214 | static void hdmi_runtime_put(void) |
| 215 | { |
| 216 | int r; |
| 217 | |
| 218 | DSSDBG("hdmi_runtime_put\n"); |
| 219 | |
| 220 | r = pm_runtime_put(&hdmi.pdev->dev); |
| 221 | WARN_ON(r < 0); |
| 222 | } |
| 223 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 224 | int hdmi_init_display(struct omap_dss_device *dssdev) |
| 225 | { |
| 226 | DSSDBG("init_display\n"); |
| 227 | |
| 228 | return 0; |
| 229 | } |
| 230 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 231 | static int hdmi_pll_init(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 232 | { |
| 233 | u32 r; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 234 | void __iomem *pll_base = hdmi_pll_base(ip_data); |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 235 | struct hdmi_pll_info *fmt = &ip_data->pll_data; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 236 | |
| 237 | /* PLL start always use manual mode */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 238 | REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 239 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 240 | r = hdmi_read_reg(pll_base, PLLCTRL_CFG1); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 241 | r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ |
| 242 | r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ |
| 243 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 244 | hdmi_write_reg(pll_base, PLLCTRL_CFG1, r); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 245 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 246 | r = hdmi_read_reg(pll_base, PLLCTRL_CFG2); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 247 | |
| 248 | r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ |
| 249 | r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ |
| 250 | r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 251 | r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 252 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 253 | if (fmt->dcofreq) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 254 | /* divider programming for frequency beyond 1000Mhz */ |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 255 | REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 256 | r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ |
| 257 | } else { |
| 258 | r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ |
| 259 | } |
| 260 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 261 | hdmi_write_reg(pll_base, PLLCTRL_CFG2, r); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 262 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 263 | r = hdmi_read_reg(pll_base, PLLCTRL_CFG4); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 264 | r = FLD_MOD(r, fmt->regm2, 24, 18); |
| 265 | r = FLD_MOD(r, fmt->regmf, 17, 0); |
| 266 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 267 | hdmi_write_reg(pll_base, PLLCTRL_CFG4, r); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 268 | |
| 269 | /* go now */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 270 | REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 271 | |
| 272 | /* wait for bit change */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 273 | if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO, |
| 274 | 0, 0, 1) != 1) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 275 | DSSERR("PLL GO bit not set\n"); |
| 276 | return -ETIMEDOUT; |
| 277 | } |
| 278 | |
| 279 | /* Wait till the lock bit is set in PLL status */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 280 | if (hdmi_wait_for_bit_change(pll_base, |
| 281 | PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 282 | DSSWARN("cannot lock PLL\n"); |
| 283 | DSSWARN("CFG1 0x%x\n", |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 284 | hdmi_read_reg(pll_base, PLLCTRL_CFG1)); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 285 | DSSWARN("CFG2 0x%x\n", |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 286 | hdmi_read_reg(pll_base, PLLCTRL_CFG2)); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 287 | DSSWARN("CFG4 0x%x\n", |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 288 | hdmi_read_reg(pll_base, PLLCTRL_CFG4)); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 289 | return -ETIMEDOUT; |
| 290 | } |
| 291 | |
| 292 | DSSDBG("PLL locked!\n"); |
| 293 | |
| 294 | return 0; |
| 295 | } |
| 296 | |
| 297 | /* PHY_PWR_CMD */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 298 | static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 299 | { |
| 300 | /* Command for power control of HDMI PHY */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 301 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 302 | |
| 303 | /* Status of the power control of HDMI PHY */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 304 | if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), |
| 305 | HDMI_WP_PWR_CTRL, 5, 4, val) != val) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 306 | DSSERR("Failed to set PHY power mode to %d\n", val); |
| 307 | return -ETIMEDOUT; |
| 308 | } |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
| 313 | /* PLL_PWR_CMD */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 314 | int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 315 | { |
| 316 | /* Command for power control of HDMI PLL */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 317 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 318 | |
| 319 | /* wait till PHY_PWR_STATUS is set */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 320 | if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, |
| 321 | 1, 0, val) != val) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 322 | DSSERR("Failed to set PHY_PWR_STATUS\n"); |
| 323 | return -ETIMEDOUT; |
| 324 | } |
| 325 | |
| 326 | return 0; |
| 327 | } |
| 328 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 329 | static int hdmi_pll_reset(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 330 | { |
| 331 | /* SYSRESET controlled by power FSM */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 332 | REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 333 | |
| 334 | /* READ 0x0 reset is in progress */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 335 | if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data), |
| 336 | PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 337 | DSSERR("Failed to sysreset PLL\n"); |
| 338 | return -ETIMEDOUT; |
| 339 | } |
| 340 | |
| 341 | return 0; |
| 342 | } |
| 343 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 344 | static int hdmi_phy_init(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 345 | { |
| 346 | u16 r = 0; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 347 | void __iomem *phy_base = hdmi_phy_base(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 348 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 349 | r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 350 | if (r) |
| 351 | return r; |
| 352 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 353 | r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 354 | if (r) |
| 355 | return r; |
| 356 | |
| 357 | /* |
| 358 | * Read address 0 in order to get the SCP reset done completed |
| 359 | * Dummy access performed to make sure reset is done |
| 360 | */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 361 | hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 362 | |
| 363 | /* |
| 364 | * Write to phy address 0 to configure the clock |
| 365 | * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field |
| 366 | */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 367 | REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 368 | |
| 369 | /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 370 | hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 371 | |
| 372 | /* Setup max LDO voltage */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 373 | REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 374 | |
| 375 | /* Write to phy address 3 to change the polarity control */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 376 | REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 381 | static int hdmi_pll_program(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 382 | { |
| 383 | u16 r = 0; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 384 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 385 | r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 386 | if (r) |
| 387 | return r; |
| 388 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 389 | r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 390 | if (r) |
| 391 | return r; |
| 392 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 393 | r = hdmi_pll_reset(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 394 | if (r) |
| 395 | return r; |
| 396 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 397 | r = hdmi_pll_init(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 398 | if (r) |
| 399 | return r; |
| 400 | |
| 401 | return 0; |
| 402 | } |
| 403 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 404 | static void hdmi_phy_off(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 405 | { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 406 | hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 407 | } |
| 408 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 409 | static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, |
| 410 | u8 *pedid, int ext) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 411 | { |
| 412 | u32 i, j; |
| 413 | char checksum = 0; |
| 414 | u32 offset = 0; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 415 | void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 416 | |
| 417 | /* Turn on CLK for DDC */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 418 | REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 419 | |
| 420 | /* |
| 421 | * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / |
| 422 | * right shifted values( The behavior is not consistent and seen only |
| 423 | * with some TV's) |
| 424 | */ |
| 425 | usleep_range(800, 1000); |
| 426 | |
| 427 | if (!ext) { |
| 428 | /* Clk SCL Devices */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 429 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 430 | |
| 431 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 432 | if (hdmi_wait_for_bit_change(core_sys_base, |
| 433 | HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 434 | DSSERR("Failed to program DDC\n"); |
| 435 | return -ETIMEDOUT; |
| 436 | } |
| 437 | |
| 438 | /* Clear FIFO */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 439 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 440 | |
| 441 | /* HDMI_CORE_DDC_STATUS_IN_PROG */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 442 | if (hdmi_wait_for_bit_change(core_sys_base, |
| 443 | HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 444 | DSSERR("Failed to program DDC\n"); |
| 445 | return -ETIMEDOUT; |
| 446 | } |
| 447 | |
| 448 | } else { |
| 449 | if (ext % 2 != 0) |
| 450 | offset = 0x80; |
| 451 | } |
| 452 | |
| 453 | /* Load Segment Address Register */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 454 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 455 | |
| 456 | /* Load Slave Address Register */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 457 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 458 | |
| 459 | /* Load Offset Address Register */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 460 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 461 | |
| 462 | /* Load Byte Count */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 463 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); |
| 464 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 465 | |
| 466 | /* Set DDC_CMD */ |
| 467 | if (ext) |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 468 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 469 | else |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 470 | REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 471 | |
| 472 | /* HDMI_CORE_DDC_STATUS_BUS_LOW */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 473 | if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 474 | DSSWARN("I2C Bus Low?\n"); |
| 475 | return -EIO; |
| 476 | } |
| 477 | /* HDMI_CORE_DDC_STATUS_NO_ACK */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 478 | if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 479 | DSSWARN("I2C No Ack\n"); |
| 480 | return -EIO; |
| 481 | } |
| 482 | |
| 483 | i = ext * 128; |
| 484 | j = 0; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 485 | while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) || |
| 486 | (REG_GET(core_sys_base, |
| 487 | HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 488 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 489 | if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 490 | /* FIFO not empty */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 491 | pedid[i++] = REG_GET(core_sys_base, |
| 492 | HDMI_CORE_DDC_DATA, 7, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 493 | j++; |
| 494 | } |
| 495 | } |
| 496 | |
| 497 | for (j = 0; j < 128; j++) |
| 498 | checksum += pedid[j]; |
| 499 | |
| 500 | if (checksum != 0) { |
| 501 | DSSERR("E-EDID checksum failed!!\n"); |
| 502 | return -EIO; |
| 503 | } |
| 504 | |
| 505 | return 0; |
| 506 | } |
| 507 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 508 | static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 509 | { |
| 510 | int r = 0, n = 0, i = 0; |
| 511 | int max_ext_blocks = (max_length / 128) - 1; |
| 512 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 513 | r = hdmi_core_ddc_edid(ip_data, pedid, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 514 | if (r) { |
| 515 | return r; |
| 516 | } else { |
| 517 | n = pedid[0x7e]; |
| 518 | |
| 519 | /* |
| 520 | * README: need to comply with max_length set by the caller. |
| 521 | * Better implementation should be to allocate necessary |
| 522 | * memory to store EDID according to nb_block field found |
| 523 | * in first block |
| 524 | */ |
| 525 | if (n > max_ext_blocks) |
| 526 | n = max_ext_blocks; |
| 527 | |
| 528 | for (i = 1; i <= n; i++) { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 529 | r = hdmi_core_ddc_edid(ip_data, pedid, i); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 530 | if (r) |
| 531 | return r; |
| 532 | } |
| 533 | } |
| 534 | return 0; |
| 535 | } |
| 536 | |
Mythri P K | 38863b7 | 2011-09-08 19:06:20 +0530 | [diff] [blame^] | 537 | static void copy_hdmi_to_dss_timings( |
| 538 | const struct hdmi_video_timings *hdmi_timings, |
| 539 | struct omap_video_timings *timings) |
| 540 | { |
| 541 | timings->x_res = hdmi_timings->x_res; |
| 542 | timings->y_res = hdmi_timings->y_res; |
| 543 | timings->pixel_clock = hdmi_timings->pixel_clock; |
| 544 | timings->hbp = hdmi_timings->hbp; |
| 545 | timings->hfp = hdmi_timings->hfp; |
| 546 | timings->hsw = hdmi_timings->hsw; |
| 547 | timings->vbp = hdmi_timings->vbp; |
| 548 | timings->vfp = hdmi_timings->vfp; |
| 549 | timings->vsw = hdmi_timings->vsw; |
| 550 | } |
| 551 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 552 | static int get_timings_index(void) |
| 553 | { |
| 554 | int code; |
| 555 | |
| 556 | if (hdmi.mode == 0) |
| 557 | code = code_vesa[hdmi.code]; |
| 558 | else |
| 559 | code = code_cea[hdmi.code]; |
| 560 | |
| 561 | if (code == -1) { |
| 562 | /* HDMI code 4 corresponds to 640 * 480 VGA */ |
| 563 | hdmi.code = 4; |
| 564 | /* DVI mode 1 corresponds to HDMI 0 to DVI */ |
| 565 | hdmi.mode = HDMI_DVI; |
| 566 | |
| 567 | code = code_vesa[hdmi.code]; |
| 568 | } |
| 569 | return code; |
| 570 | } |
| 571 | |
| 572 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) |
| 573 | { |
| 574 | int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; |
| 575 | int timing_vsync = 0, timing_hsync = 0; |
Mythri P K | 38863b7 | 2011-09-08 19:06:20 +0530 | [diff] [blame^] | 576 | struct hdmi_video_timings temp; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 577 | struct hdmi_cm cm = {-1}; |
| 578 | DSSDBG("hdmi_get_code\n"); |
| 579 | |
| 580 | for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) { |
| 581 | temp = cea_vesa_timings[i].timings; |
| 582 | if ((temp.pixel_clock == timing->pixel_clock) && |
| 583 | (temp.x_res == timing->x_res) && |
| 584 | (temp.y_res == timing->y_res)) { |
| 585 | |
| 586 | temp_hsync = temp.hfp + temp.hsw + temp.hbp; |
| 587 | timing_hsync = timing->hfp + timing->hsw + timing->hbp; |
| 588 | temp_vsync = temp.vfp + temp.vsw + temp.vbp; |
| 589 | timing_vsync = timing->vfp + timing->vsw + timing->vbp; |
| 590 | |
| 591 | DSSDBG("temp_hsync = %d , temp_vsync = %d" |
| 592 | "timing_hsync = %d, timing_vsync = %d\n", |
| 593 | temp_hsync, temp_hsync, |
| 594 | timing_hsync, timing_vsync); |
| 595 | |
| 596 | if ((temp_hsync == timing_hsync) && |
| 597 | (temp_vsync == timing_vsync)) { |
| 598 | code = i; |
| 599 | cm.code = code_index[i]; |
| 600 | if (code < 14) |
| 601 | cm.mode = HDMI_HDMI; |
| 602 | else |
| 603 | cm.mode = HDMI_DVI; |
| 604 | DSSDBG("Hdmi_code = %d mode = %d\n", |
| 605 | cm.code, cm.mode); |
| 606 | break; |
| 607 | } |
| 608 | } |
| 609 | } |
| 610 | |
| 611 | return cm; |
| 612 | } |
| 613 | |
| 614 | static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid , |
| 615 | struct omap_video_timings *timings) |
| 616 | { |
| 617 | /* X and Y resolution */ |
| 618 | timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) | |
| 619 | edid[current_descriptor_addrs + 2]); |
| 620 | timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) | |
| 621 | edid[current_descriptor_addrs + 5]); |
| 622 | |
| 623 | timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) | |
| 624 | edid[current_descriptor_addrs]); |
| 625 | |
| 626 | timings->pixel_clock = 10 * timings->pixel_clock; |
| 627 | |
| 628 | /* HORIZONTAL FRONT PORCH */ |
| 629 | timings->hfp = edid[current_descriptor_addrs + 8] | |
| 630 | ((edid[current_descriptor_addrs + 11] & 0xc0) << 2); |
| 631 | /* HORIZONTAL SYNC WIDTH */ |
| 632 | timings->hsw = edid[current_descriptor_addrs + 9] | |
| 633 | ((edid[current_descriptor_addrs + 11] & 0x30) << 4); |
| 634 | /* HORIZONTAL BACK PORCH */ |
| 635 | timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) | |
| 636 | edid[current_descriptor_addrs + 3]) - |
| 637 | (timings->hfp + timings->hsw); |
| 638 | /* VERTICAL FRONT PORCH */ |
| 639 | timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) | |
| 640 | ((edid[current_descriptor_addrs + 11] & 0x0f) << 2); |
| 641 | /* VERTICAL SYNC WIDTH */ |
| 642 | timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) | |
| 643 | ((edid[current_descriptor_addrs + 11] & 0x03) << 4); |
| 644 | /* VERTICAL BACK PORCH */ |
| 645 | timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) | |
| 646 | edid[current_descriptor_addrs + 6]) - |
| 647 | (timings->vfp + timings->vsw); |
| 648 | |
| 649 | } |
| 650 | |
| 651 | /* Description : This function gets the resolution information from EDID */ |
| 652 | static void get_edid_timing_data(u8 *edid) |
| 653 | { |
| 654 | u8 count; |
| 655 | u16 current_descriptor_addrs; |
| 656 | struct hdmi_cm cm; |
| 657 | struct omap_video_timings edid_timings; |
| 658 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 659 | /* search block 0, there are 4 DTDs arranged in priority order */ |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 660 | for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) { |
| 661 | current_descriptor_addrs = |
| 662 | EDID_DESCRIPTOR_BLOCK0_ADDRESS + |
| 663 | count * EDID_TIMING_DESCRIPTOR_SIZE; |
| 664 | get_horz_vert_timing_info(current_descriptor_addrs, |
| 665 | edid, &edid_timings); |
| 666 | cm = hdmi_get_code(&edid_timings); |
| 667 | DSSDBG("Block0[%d] value matches code = %d , mode = %d\n", |
| 668 | count, cm.code, cm.mode); |
| 669 | if (cm.code == -1) { |
| 670 | continue; |
| 671 | } else { |
| 672 | hdmi.code = cm.code; |
| 673 | hdmi.mode = cm.mode; |
| 674 | DSSDBG("code = %d , mode = %d\n", |
| 675 | hdmi.code, hdmi.mode); |
| 676 | return; |
| 677 | } |
| 678 | } |
| 679 | if (edid[0x7e] != 0x00) { |
| 680 | for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR; |
| 681 | count++) { |
| 682 | current_descriptor_addrs = |
| 683 | EDID_DESCRIPTOR_BLOCK1_ADDRESS + |
| 684 | count * EDID_TIMING_DESCRIPTOR_SIZE; |
| 685 | get_horz_vert_timing_info(current_descriptor_addrs, |
| 686 | edid, &edid_timings); |
| 687 | cm = hdmi_get_code(&edid_timings); |
| 688 | DSSDBG("Block1[%d] value matches code = %d, mode = %d", |
| 689 | count, cm.code, cm.mode); |
| 690 | if (cm.code == -1) { |
| 691 | continue; |
| 692 | } else { |
| 693 | hdmi.code = cm.code; |
| 694 | hdmi.mode = cm.mode; |
| 695 | DSSDBG("code = %d , mode = %d\n", |
| 696 | hdmi.code, hdmi.mode); |
| 697 | return; |
| 698 | } |
| 699 | } |
| 700 | } |
| 701 | |
| 702 | DSSINFO("no valid timing found , falling back to VGA\n"); |
| 703 | hdmi.code = 4; /* setting default value of 640 480 VGA */ |
| 704 | hdmi.mode = HDMI_DVI; |
| 705 | } |
| 706 | |
| 707 | static void hdmi_read_edid(struct omap_video_timings *dp) |
| 708 | { |
| 709 | int ret = 0, code; |
| 710 | |
| 711 | memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); |
| 712 | |
| 713 | if (!hdmi.edid_set) |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 714 | ret = read_edid(&hdmi.ip_data, hdmi.edid, |
| 715 | HDMI_EDID_MAX_LENGTH); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 716 | if (!ret) { |
| 717 | if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { |
| 718 | /* search for timings of default resolution */ |
| 719 | get_edid_timing_data(hdmi.edid); |
| 720 | hdmi.edid_set = true; |
| 721 | } |
| 722 | } else { |
| 723 | DSSWARN("failed to read E-EDID\n"); |
| 724 | } |
| 725 | |
| 726 | if (!hdmi.edid_set) { |
| 727 | DSSINFO("fallback to VGA\n"); |
| 728 | hdmi.code = 4; /* setting default value of 640 480 VGA */ |
| 729 | hdmi.mode = HDMI_DVI; |
| 730 | } |
| 731 | |
| 732 | code = get_timings_index(); |
| 733 | |
Mythri P K | 38863b7 | 2011-09-08 19:06:20 +0530 | [diff] [blame^] | 734 | copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings, dp); |
| 735 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 736 | } |
| 737 | |
| 738 | static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, |
| 739 | struct hdmi_core_infoframe_avi *avi_cfg, |
| 740 | struct hdmi_core_packet_enable_repeat *repeat_cfg) |
| 741 | { |
| 742 | DSSDBG("Enter hdmi_core_init\n"); |
| 743 | |
| 744 | /* video core */ |
| 745 | video_cfg->ip_bus_width = HDMI_INPUT_8BIT; |
| 746 | video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; |
| 747 | video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; |
| 748 | video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; |
| 749 | video_cfg->hdmi_dvi = HDMI_DVI; |
| 750 | video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; |
| 751 | |
| 752 | /* info frame */ |
| 753 | avi_cfg->db1_format = 0; |
| 754 | avi_cfg->db1_active_info = 0; |
| 755 | avi_cfg->db1_bar_info_dv = 0; |
| 756 | avi_cfg->db1_scan_info = 0; |
| 757 | avi_cfg->db2_colorimetry = 0; |
| 758 | avi_cfg->db2_aspect_ratio = 0; |
| 759 | avi_cfg->db2_active_fmt_ar = 0; |
| 760 | avi_cfg->db3_itc = 0; |
| 761 | avi_cfg->db3_ec = 0; |
| 762 | avi_cfg->db3_q_range = 0; |
| 763 | avi_cfg->db3_nup_scaling = 0; |
| 764 | avi_cfg->db4_videocode = 0; |
| 765 | avi_cfg->db5_pixel_repeat = 0; |
| 766 | avi_cfg->db6_7_line_eoftop = 0 ; |
| 767 | avi_cfg->db8_9_line_sofbottom = 0; |
| 768 | avi_cfg->db10_11_pixel_eofleft = 0; |
| 769 | avi_cfg->db12_13_pixel_sofright = 0; |
| 770 | |
| 771 | /* packet enable and repeat */ |
| 772 | repeat_cfg->audio_pkt = 0; |
| 773 | repeat_cfg->audio_pkt_repeat = 0; |
| 774 | repeat_cfg->avi_infoframe = 0; |
| 775 | repeat_cfg->avi_infoframe_repeat = 0; |
| 776 | repeat_cfg->gen_cntrl_pkt = 0; |
| 777 | repeat_cfg->gen_cntrl_pkt_repeat = 0; |
| 778 | repeat_cfg->generic_pkt = 0; |
| 779 | repeat_cfg->generic_pkt_repeat = 0; |
| 780 | } |
| 781 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 782 | static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 783 | { |
| 784 | DSSDBG("Enter hdmi_core_powerdown_disable\n"); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 785 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 786 | } |
| 787 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 788 | static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 789 | { |
| 790 | DSSDBG("Enter hdmi_core_swreset_release\n"); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 791 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 792 | } |
| 793 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 794 | static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 795 | { |
| 796 | DSSDBG("Enter hdmi_core_swreset_assert\n"); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 797 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 798 | } |
| 799 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 800 | /* HDMI_CORE_VIDEO_CONFIG */ |
| 801 | static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, |
| 802 | struct hdmi_core_video_config *cfg) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 803 | { |
| 804 | u32 r = 0; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 805 | void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 806 | |
| 807 | /* sys_ctrl1 default configuration not tunable */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 808 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 809 | r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); |
| 810 | r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); |
| 811 | r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); |
| 812 | r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 813 | hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 814 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 815 | REG_FLD_MOD(core_sys_base, |
| 816 | HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 817 | |
| 818 | /* Vid_Mode */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 819 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 820 | |
| 821 | /* dither truncation configuration */ |
| 822 | if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { |
| 823 | r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); |
| 824 | r = FLD_MOD(r, 1, 5, 5); |
| 825 | } else { |
| 826 | r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); |
| 827 | r = FLD_MOD(r, 0, 5, 5); |
| 828 | } |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 829 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 830 | |
| 831 | /* HDMI_Ctrl */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 832 | r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 833 | r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); |
| 834 | r = FLD_MOD(r, cfg->pkt_mode, 5, 3); |
| 835 | r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 836 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 837 | |
| 838 | /* TMDS_CTRL */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 839 | REG_FLD_MOD(core_sys_base, |
| 840 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 841 | } |
| 842 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 843 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 844 | struct hdmi_core_infoframe_avi info_avi) |
| 845 | { |
| 846 | u32 val; |
| 847 | char sum = 0, checksum = 0; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 848 | void __iomem *av_base = hdmi_av_base(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 849 | |
| 850 | sum += 0x82 + 0x002 + 0x00D; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 851 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); |
| 852 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002); |
| 853 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 854 | |
| 855 | val = (info_avi.db1_format << 5) | |
| 856 | (info_avi.db1_active_info << 4) | |
| 857 | (info_avi.db1_bar_info_dv << 2) | |
| 858 | (info_avi.db1_scan_info); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 859 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 860 | sum += val; |
| 861 | |
| 862 | val = (info_avi.db2_colorimetry << 6) | |
| 863 | (info_avi.db2_aspect_ratio << 4) | |
| 864 | (info_avi.db2_active_fmt_ar); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 865 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 866 | sum += val; |
| 867 | |
| 868 | val = (info_avi.db3_itc << 7) | |
| 869 | (info_avi.db3_ec << 4) | |
| 870 | (info_avi.db3_q_range << 2) | |
| 871 | (info_avi.db3_nup_scaling); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 872 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 873 | sum += val; |
| 874 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 875 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3), |
| 876 | info_avi.db4_videocode); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 877 | sum += info_avi.db4_videocode; |
| 878 | |
| 879 | val = info_avi.db5_pixel_repeat; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 880 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 881 | sum += val; |
| 882 | |
| 883 | val = info_avi.db6_7_line_eoftop & 0x00FF; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 884 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 885 | sum += val; |
| 886 | |
| 887 | val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 888 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 889 | sum += val; |
| 890 | |
| 891 | val = info_avi.db8_9_line_sofbottom & 0x00FF; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 892 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 893 | sum += val; |
| 894 | |
| 895 | val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 896 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 897 | sum += val; |
| 898 | |
| 899 | val = info_avi.db10_11_pixel_eofleft & 0x00FF; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 900 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 901 | sum += val; |
| 902 | |
| 903 | val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 904 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 905 | sum += val; |
| 906 | |
| 907 | val = info_avi.db12_13_pixel_sofright & 0x00FF; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 908 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 909 | sum += val; |
| 910 | |
| 911 | val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 912 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 913 | sum += val; |
| 914 | |
| 915 | checksum = 0x100 - sum; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 916 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 917 | } |
| 918 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 919 | static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 920 | struct hdmi_core_packet_enable_repeat repeat_cfg) |
| 921 | { |
| 922 | /* enable/repeat the infoframe */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 923 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 924 | (repeat_cfg.audio_pkt << 5) | |
| 925 | (repeat_cfg.audio_pkt_repeat << 4) | |
| 926 | (repeat_cfg.avi_infoframe << 1) | |
| 927 | (repeat_cfg.avi_infoframe_repeat)); |
| 928 | |
| 929 | /* enable/repeat the packet */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 930 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 931 | (repeat_cfg.gen_cntrl_pkt << 3) | |
| 932 | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | |
| 933 | (repeat_cfg.generic_pkt << 1) | |
| 934 | (repeat_cfg.generic_pkt_repeat)); |
| 935 | } |
| 936 | |
| 937 | static void hdmi_wp_init(struct omap_video_timings *timings, |
| 938 | struct hdmi_video_format *video_fmt, |
| 939 | struct hdmi_video_interface *video_int) |
| 940 | { |
| 941 | DSSDBG("Enter hdmi_wp_init\n"); |
| 942 | |
| 943 | timings->hbp = 0; |
| 944 | timings->hfp = 0; |
| 945 | timings->hsw = 0; |
| 946 | timings->vbp = 0; |
| 947 | timings->vfp = 0; |
| 948 | timings->vsw = 0; |
| 949 | |
| 950 | video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; |
| 951 | video_fmt->y_res = 0; |
| 952 | video_fmt->x_res = 0; |
| 953 | |
| 954 | video_int->vsp = 0; |
| 955 | video_int->hsp = 0; |
| 956 | |
| 957 | video_int->interlacing = 0; |
| 958 | video_int->tm = 0; /* HDMI_TIMING_SLAVE */ |
| 959 | |
| 960 | } |
| 961 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 962 | static void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 963 | { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 964 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 965 | } |
| 966 | |
| 967 | static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, |
| 968 | struct omap_video_timings *timings, struct hdmi_config *param) |
| 969 | { |
| 970 | DSSDBG("Enter hdmi_wp_video_init_format\n"); |
| 971 | |
| 972 | video_fmt->y_res = param->timings.timings.y_res; |
| 973 | video_fmt->x_res = param->timings.timings.x_res; |
| 974 | |
| 975 | timings->hbp = param->timings.timings.hbp; |
| 976 | timings->hfp = param->timings.timings.hfp; |
| 977 | timings->hsw = param->timings.timings.hsw; |
| 978 | timings->vbp = param->timings.timings.vbp; |
| 979 | timings->vfp = param->timings.timings.vfp; |
| 980 | timings->vsw = param->timings.timings.vsw; |
| 981 | } |
| 982 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 983 | static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 984 | struct hdmi_video_format *video_fmt) |
| 985 | { |
| 986 | u32 l = 0; |
| 987 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 988 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, |
| 989 | video_fmt->packing_mode, 10, 8); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 990 | |
| 991 | l |= FLD_VAL(video_fmt->y_res, 31, 16); |
| 992 | l |= FLD_VAL(video_fmt->x_res, 15, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 993 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 994 | } |
| 995 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 996 | static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 997 | struct hdmi_video_interface *video_int) |
| 998 | { |
| 999 | u32 r; |
| 1000 | DSSDBG("Enter hdmi_wp_video_config_interface\n"); |
| 1001 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1002 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1003 | r = FLD_MOD(r, video_int->vsp, 7, 7); |
| 1004 | r = FLD_MOD(r, video_int->hsp, 6, 6); |
| 1005 | r = FLD_MOD(r, video_int->interlacing, 3, 3); |
| 1006 | r = FLD_MOD(r, video_int->tm, 1, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1007 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1008 | } |
| 1009 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1010 | static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1011 | struct omap_video_timings *timings) |
| 1012 | { |
| 1013 | u32 timing_h = 0; |
| 1014 | u32 timing_v = 0; |
| 1015 | |
| 1016 | DSSDBG("Enter hdmi_wp_video_config_timing\n"); |
| 1017 | |
| 1018 | timing_h |= FLD_VAL(timings->hbp, 31, 20); |
| 1019 | timing_h |= FLD_VAL(timings->hfp, 19, 8); |
| 1020 | timing_h |= FLD_VAL(timings->hsw, 7, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1021 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1022 | |
| 1023 | timing_v |= FLD_VAL(timings->vbp, 31, 20); |
| 1024 | timing_v |= FLD_VAL(timings->vfp, 19, 8); |
| 1025 | timing_v |= FLD_VAL(timings->vsw, 7, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1026 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1027 | } |
| 1028 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1029 | static void hdmi_basic_configure(struct hdmi_ip_data *ip_data) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1030 | { |
| 1031 | /* HDMI */ |
| 1032 | struct omap_video_timings video_timing; |
| 1033 | struct hdmi_video_format video_format; |
| 1034 | struct hdmi_video_interface video_interface; |
| 1035 | /* HDMI core */ |
| 1036 | struct hdmi_core_infoframe_avi avi_cfg; |
| 1037 | struct hdmi_core_video_config v_core_cfg; |
| 1038 | struct hdmi_core_packet_enable_repeat repeat_cfg; |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1039 | struct hdmi_config *cfg = &ip_data->cfg; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1040 | |
| 1041 | hdmi_wp_init(&video_timing, &video_format, |
| 1042 | &video_interface); |
| 1043 | |
| 1044 | hdmi_core_init(&v_core_cfg, |
| 1045 | &avi_cfg, |
| 1046 | &repeat_cfg); |
| 1047 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1048 | hdmi_wp_video_init_format(&video_format, &video_timing, cfg); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1049 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1050 | hdmi_wp_video_config_timing(ip_data, &video_timing); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1051 | |
| 1052 | /* video config */ |
| 1053 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; |
| 1054 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1055 | hdmi_wp_video_config_format(ip_data, &video_format); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1056 | |
| 1057 | video_interface.vsp = cfg->timings.vsync_pol; |
| 1058 | video_interface.hsp = cfg->timings.hsync_pol; |
| 1059 | video_interface.interlacing = cfg->interlace; |
| 1060 | video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ |
| 1061 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1062 | hdmi_wp_video_config_interface(ip_data, &video_interface); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1063 | |
| 1064 | /* |
| 1065 | * configure core video part |
| 1066 | * set software reset in the core |
| 1067 | */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1068 | hdmi_core_swreset_assert(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1069 | |
| 1070 | /* power down off */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1071 | hdmi_core_powerdown_disable(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1072 | |
| 1073 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; |
| 1074 | v_core_cfg.hdmi_dvi = cfg->cm.mode; |
| 1075 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1076 | hdmi_core_video_config(ip_data, &v_core_cfg); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1077 | |
| 1078 | /* release software reset in the core */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1079 | hdmi_core_swreset_release(ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1080 | |
| 1081 | /* |
| 1082 | * configure packet |
| 1083 | * info frame video see doc CEA861-D page 65 |
| 1084 | */ |
| 1085 | avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; |
| 1086 | avi_cfg.db1_active_info = |
| 1087 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; |
| 1088 | avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; |
| 1089 | avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; |
| 1090 | avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; |
| 1091 | avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; |
| 1092 | avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; |
| 1093 | avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; |
| 1094 | avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; |
| 1095 | avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; |
| 1096 | avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; |
| 1097 | avi_cfg.db4_videocode = cfg->cm.code; |
| 1098 | avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; |
| 1099 | avi_cfg.db6_7_line_eoftop = 0; |
| 1100 | avi_cfg.db8_9_line_sofbottom = 0; |
| 1101 | avi_cfg.db10_11_pixel_eofleft = 0; |
| 1102 | avi_cfg.db12_13_pixel_sofright = 0; |
| 1103 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1104 | hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1105 | |
| 1106 | /* enable/repeat the infoframe */ |
| 1107 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; |
| 1108 | repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; |
| 1109 | /* wakeup */ |
| 1110 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; |
| 1111 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1112 | hdmi_core_av_packet_config(ip_data, repeat_cfg); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1113 | } |
| 1114 | |
| 1115 | static void update_hdmi_timings(struct hdmi_config *cfg, |
| 1116 | struct omap_video_timings *timings, int code) |
| 1117 | { |
| 1118 | cfg->timings.timings.x_res = timings->x_res; |
| 1119 | cfg->timings.timings.y_res = timings->y_res; |
| 1120 | cfg->timings.timings.hbp = timings->hbp; |
| 1121 | cfg->timings.timings.hfp = timings->hfp; |
| 1122 | cfg->timings.timings.hsw = timings->hsw; |
| 1123 | cfg->timings.timings.vbp = timings->vbp; |
| 1124 | cfg->timings.timings.vfp = timings->vfp; |
| 1125 | cfg->timings.timings.vsw = timings->vsw; |
| 1126 | cfg->timings.timings.pixel_clock = timings->pixel_clock; |
| 1127 | cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol; |
| 1128 | cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; |
| 1129 | } |
| 1130 | |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1131 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
| 1132 | struct hdmi_pll_info *pi) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1133 | { |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1134 | unsigned long clkin, refclk; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1135 | u32 mf; |
| 1136 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1137 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1138 | /* |
| 1139 | * Input clock is predivided by N + 1 |
| 1140 | * out put of which is reference clk |
| 1141 | */ |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1142 | pi->regn = dssdev->clocks.hdmi.regn; |
| 1143 | refclk = clkin / (pi->regn + 1); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1144 | |
| 1145 | /* |
| 1146 | * multiplier is pixel_clk/ref_clk |
| 1147 | * Multiplying by 100 to avoid fractional part removal |
| 1148 | */ |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1149 | pi->regm = (phy * 100 / (refclk)) / 100; |
| 1150 | pi->regm2 = dssdev->clocks.hdmi.regm2; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1151 | |
| 1152 | /* |
| 1153 | * fractional multiplier is remainder of the difference between |
| 1154 | * multiplier and actual phy(required pixel clock thus should be |
| 1155 | * multiplied by 2^18(262144) divided by the reference clock |
| 1156 | */ |
| 1157 | mf = (phy - pi->regm * refclk) * 262144; |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1158 | pi->regmf = mf / (refclk); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1159 | |
| 1160 | /* |
| 1161 | * Dcofreq should be set to 1 if required pixel clock |
| 1162 | * is greater than 1000MHz |
| 1163 | */ |
| 1164 | pi->dcofreq = phy > 1000 * 100; |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1165 | pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1166 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1167 | /* Set the reference clock to sysclk reference */ |
| 1168 | pi->refsel = HDMI_REFSEL_SYSCLK; |
| 1169 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1170 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
| 1171 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); |
| 1172 | } |
| 1173 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1174 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
| 1175 | { |
| 1176 | int r, code = 0; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1177 | struct omap_video_timings *p; |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1178 | unsigned long phy; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1179 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1180 | r = hdmi_runtime_get(); |
| 1181 | if (r) |
| 1182 | return r; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1183 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1184 | dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1185 | |
| 1186 | p = &dssdev->panel.timings; |
| 1187 | |
| 1188 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", |
| 1189 | dssdev->panel.timings.x_res, |
| 1190 | dssdev->panel.timings.y_res); |
| 1191 | |
| 1192 | if (!hdmi.custom_set) { |
| 1193 | DSSDBG("Read EDID as no EDID is not set on poweron\n"); |
| 1194 | hdmi_read_edid(p); |
| 1195 | } |
| 1196 | code = get_timings_index(); |
Mythri P K | 38863b7 | 2011-09-08 19:06:20 +0530 | [diff] [blame^] | 1197 | copy_hdmi_to_dss_timings(&cea_vesa_timings[code].timings, |
| 1198 | &dssdev->panel.timings); |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1199 | update_hdmi_timings(&hdmi.ip_data.cfg, p, code); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1200 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1201 | phy = p->pixel_clock; |
| 1202 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1203 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1204 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1205 | hdmi_wp_video_start(&hdmi.ip_data, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1206 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1207 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1208 | r = hdmi_pll_program(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1209 | if (r) { |
| 1210 | DSSDBG("Failed to lock PLL\n"); |
| 1211 | goto err; |
| 1212 | } |
| 1213 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1214 | r = hdmi_phy_init(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1215 | if (r) { |
| 1216 | DSSDBG("Failed to start PHY\n"); |
| 1217 | goto err; |
| 1218 | } |
| 1219 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 1220 | hdmi.ip_data.cfg.cm.mode = hdmi.mode; |
| 1221 | hdmi.ip_data.cfg.cm.code = hdmi.code; |
| 1222 | hdmi_basic_configure(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1223 | |
| 1224 | /* Make selection of HDMI in DSS */ |
| 1225 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); |
| 1226 | |
| 1227 | /* Select the dispc clock source as PRCM clock, to ensure that it is not |
| 1228 | * DSI PLL source as the clock selected by DSI PLL might not be |
| 1229 | * sufficient for the resolution selected / that can be changed |
| 1230 | * dynamically by user. This can be moved to single location , say |
| 1231 | * Boardfile. |
| 1232 | */ |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 1233 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1234 | |
| 1235 | /* bypass TV gamma table */ |
| 1236 | dispc_enable_gamma_table(0); |
| 1237 | |
| 1238 | /* tv size */ |
| 1239 | dispc_set_digit_size(dssdev->panel.timings.x_res, |
| 1240 | dssdev->panel.timings.y_res); |
| 1241 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1242 | dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1243 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1244 | hdmi_wp_video_start(&hdmi.ip_data, 1); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1245 | |
| 1246 | return 0; |
| 1247 | err: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1248 | hdmi_runtime_put(); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1249 | return -EIO; |
| 1250 | } |
| 1251 | |
| 1252 | static void hdmi_power_off(struct omap_dss_device *dssdev) |
| 1253 | { |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 1254 | dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1255 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1256 | hdmi_wp_video_start(&hdmi.ip_data, 0); |
| 1257 | hdmi_phy_off(&hdmi.ip_data); |
| 1258 | hdmi_set_pll_pwr(&hdmi.ip_data, HDMI_PLLPWRCMD_ALLOFF); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1259 | hdmi_runtime_put(); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1260 | |
| 1261 | hdmi.edid_set = 0; |
| 1262 | } |
| 1263 | |
| 1264 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, |
| 1265 | struct omap_video_timings *timings) |
| 1266 | { |
| 1267 | struct hdmi_cm cm; |
| 1268 | |
| 1269 | cm = hdmi_get_code(timings); |
| 1270 | if (cm.code == -1) { |
| 1271 | DSSERR("Invalid timing entered\n"); |
| 1272 | return -EINVAL; |
| 1273 | } |
| 1274 | |
| 1275 | return 0; |
| 1276 | |
| 1277 | } |
| 1278 | |
| 1279 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) |
| 1280 | { |
| 1281 | struct hdmi_cm cm; |
| 1282 | |
| 1283 | hdmi.custom_set = 1; |
| 1284 | cm = hdmi_get_code(&dssdev->panel.timings); |
| 1285 | hdmi.code = cm.code; |
| 1286 | hdmi.mode = cm.mode; |
| 1287 | omapdss_hdmi_display_enable(dssdev); |
| 1288 | hdmi.custom_set = 0; |
| 1289 | } |
| 1290 | |
| 1291 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
| 1292 | { |
| 1293 | int r = 0; |
| 1294 | |
| 1295 | DSSDBG("ENTER hdmi_display_enable\n"); |
| 1296 | |
| 1297 | mutex_lock(&hdmi.lock); |
| 1298 | |
Tomi Valkeinen | 05e1d60 | 2011-06-23 16:38:21 +0300 | [diff] [blame] | 1299 | if (dssdev->manager == NULL) { |
| 1300 | DSSERR("failed to enable display: no manager\n"); |
| 1301 | r = -ENODEV; |
| 1302 | goto err0; |
| 1303 | } |
| 1304 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1305 | r = omap_dss_start_device(dssdev); |
| 1306 | if (r) { |
| 1307 | DSSERR("failed to start device\n"); |
| 1308 | goto err0; |
| 1309 | } |
| 1310 | |
| 1311 | if (dssdev->platform_enable) { |
| 1312 | r = dssdev->platform_enable(dssdev); |
| 1313 | if (r) { |
| 1314 | DSSERR("failed to enable GPIO's\n"); |
| 1315 | goto err1; |
| 1316 | } |
| 1317 | } |
| 1318 | |
| 1319 | r = hdmi_power_on(dssdev); |
| 1320 | if (r) { |
| 1321 | DSSERR("failed to power on device\n"); |
| 1322 | goto err2; |
| 1323 | } |
| 1324 | |
| 1325 | mutex_unlock(&hdmi.lock); |
| 1326 | return 0; |
| 1327 | |
| 1328 | err2: |
| 1329 | if (dssdev->platform_disable) |
| 1330 | dssdev->platform_disable(dssdev); |
| 1331 | err1: |
| 1332 | omap_dss_stop_device(dssdev); |
| 1333 | err0: |
| 1334 | mutex_unlock(&hdmi.lock); |
| 1335 | return r; |
| 1336 | } |
| 1337 | |
| 1338 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) |
| 1339 | { |
| 1340 | DSSDBG("Enter hdmi_display_disable\n"); |
| 1341 | |
| 1342 | mutex_lock(&hdmi.lock); |
| 1343 | |
| 1344 | hdmi_power_off(dssdev); |
| 1345 | |
| 1346 | if (dssdev->platform_disable) |
| 1347 | dssdev->platform_disable(dssdev); |
| 1348 | |
| 1349 | omap_dss_stop_device(dssdev); |
| 1350 | |
| 1351 | mutex_unlock(&hdmi.lock); |
| 1352 | } |
| 1353 | |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1354 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 1355 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1356 | static void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data, |
| 1357 | struct hdmi_audio_format *aud_fmt) |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1358 | { |
| 1359 | u32 r; |
| 1360 | |
| 1361 | DSSDBG("Enter hdmi_wp_audio_config_format\n"); |
| 1362 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1363 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1364 | r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); |
| 1365 | r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); |
| 1366 | r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); |
| 1367 | r = FLD_MOD(r, aud_fmt->type, 4, 4); |
| 1368 | r = FLD_MOD(r, aud_fmt->justification, 3, 3); |
| 1369 | r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); |
| 1370 | r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); |
| 1371 | r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1372 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1373 | } |
| 1374 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1375 | static void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data, |
| 1376 | struct hdmi_audio_dma *aud_dma) |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1377 | { |
| 1378 | u32 r; |
| 1379 | |
| 1380 | DSSDBG("Enter hdmi_wp_audio_config_dma\n"); |
| 1381 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1382 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1383 | r = FLD_MOD(r, aud_dma->transfer_size, 15, 8); |
| 1384 | r = FLD_MOD(r, aud_dma->block_size, 7, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1385 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1386 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1387 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1388 | r = FLD_MOD(r, aud_dma->mode, 9, 9); |
| 1389 | r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1390 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1391 | } |
| 1392 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1393 | static void hdmi_core_audio_config(struct hdmi_ip_data *ip_data, |
| 1394 | struct hdmi_core_audio_config *cfg) |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1395 | { |
| 1396 | u32 r; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1397 | void __iomem *av_base = hdmi_av_base(ip_data); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1398 | |
| 1399 | /* audio clock recovery parameters */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1400 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1401 | r = FLD_MOD(r, cfg->use_mclk, 2, 2); |
| 1402 | r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); |
| 1403 | r = FLD_MOD(r, cfg->cts_mode, 0, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1404 | hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1405 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1406 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); |
| 1407 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); |
| 1408 | REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1409 | |
| 1410 | if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1411 | REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); |
| 1412 | REG_FLD_MOD(av_base, |
| 1413 | HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); |
| 1414 | REG_FLD_MOD(av_base, |
| 1415 | HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1416 | } else { |
| 1417 | /* |
| 1418 | * HDMI IP uses this configuration to divide the MCLK to |
| 1419 | * update CTS value. |
| 1420 | */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1421 | REG_FLD_MOD(av_base, |
| 1422 | HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1423 | |
| 1424 | /* Configure clock for audio packets */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1425 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, |
| 1426 | cfg->aud_par_busclk, 7, 0); |
| 1427 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, |
| 1428 | (cfg->aud_par_busclk >> 8), 7, 0); |
| 1429 | REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, |
| 1430 | (cfg->aud_par_busclk >> 16), 7, 0); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1431 | } |
| 1432 | |
| 1433 | /* Override of SPDIF sample frequency with value in I2S_CHST4 */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1434 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, |
| 1435 | cfg->fs_override, 1, 1); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1436 | |
| 1437 | /* I2S parameters */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1438 | REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4, |
| 1439 | cfg->freq_sample, 3, 0); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1440 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1441 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1442 | r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7); |
| 1443 | r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); |
| 1444 | r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5); |
| 1445 | r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); |
| 1446 | r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3); |
| 1447 | r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); |
| 1448 | r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); |
| 1449 | r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1450 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1451 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1452 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1453 | r = FLD_MOD(r, cfg->freq_sample, 7, 4); |
| 1454 | r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1); |
| 1455 | r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1456 | hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1457 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1458 | REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, |
| 1459 | cfg->i2s_cfg.in_length_bits, 3, 0); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1460 | |
| 1461 | /* Audio channels and mode parameters */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1462 | REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); |
| 1463 | r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1464 | r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); |
| 1465 | r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); |
| 1466 | r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); |
| 1467 | r = FLD_MOD(r, cfg->en_spdif, 1, 1); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1468 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1469 | } |
| 1470 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1471 | static void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data, |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1472 | struct hdmi_core_infoframe_audio *info_aud) |
| 1473 | { |
| 1474 | u8 val; |
| 1475 | u8 sum = 0, checksum = 0; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1476 | void __iomem *av_base = hdmi_av_base(ip_data); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1477 | |
| 1478 | /* |
| 1479 | * Set audio info frame type, version and length as |
| 1480 | * described in HDMI 1.4a Section 8.2.2 specification. |
| 1481 | * Checksum calculation is defined in Section 5.3.5. |
| 1482 | */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1483 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); |
| 1484 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); |
| 1485 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1486 | sum += 0x84 + 0x001 + 0x00a; |
| 1487 | |
| 1488 | val = (info_aud->db1_coding_type << 4) |
| 1489 | | (info_aud->db1_channel_count - 1); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1490 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1491 | sum += val; |
| 1492 | |
| 1493 | val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1494 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1495 | sum += val; |
| 1496 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1497 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1498 | |
| 1499 | val = info_aud->db4_channel_alloc; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1500 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1501 | sum += val; |
| 1502 | |
| 1503 | val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3); |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1504 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1505 | sum += val; |
| 1506 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1507 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); |
| 1508 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); |
| 1509 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); |
| 1510 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); |
| 1511 | hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1512 | |
| 1513 | checksum = 0x100 - sum; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1514 | hdmi_write_reg(av_base, |
| 1515 | HDMI_CORE_AV_AUDIO_CHSUM, checksum); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1516 | |
| 1517 | /* |
| 1518 | * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing |
| 1519 | * is available. |
| 1520 | */ |
| 1521 | } |
| 1522 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1523 | static int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data, |
| 1524 | u32 sample_freq, u32 *n, u32 *cts) |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1525 | { |
| 1526 | u32 r; |
| 1527 | u32 deep_color = 0; |
| 1528 | u32 pclk = hdmi.cfg.timings.timings.pixel_clock; |
| 1529 | |
| 1530 | if (n == NULL || cts == NULL) |
| 1531 | return -EINVAL; |
| 1532 | /* |
| 1533 | * Obtain current deep color configuration. This needed |
| 1534 | * to calculate the TMDS clock based on the pixel clock. |
| 1535 | */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1536 | r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0); |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1537 | switch (r) { |
| 1538 | case 1: /* No deep color selected */ |
| 1539 | deep_color = 100; |
| 1540 | break; |
| 1541 | case 2: /* 10-bit deep color selected */ |
| 1542 | deep_color = 125; |
| 1543 | break; |
| 1544 | case 3: /* 12-bit deep color selected */ |
| 1545 | deep_color = 150; |
| 1546 | break; |
| 1547 | default: |
| 1548 | return -EINVAL; |
| 1549 | } |
| 1550 | |
| 1551 | switch (sample_freq) { |
| 1552 | case 32000: |
| 1553 | if ((deep_color == 125) && ((pclk == 54054) |
| 1554 | || (pclk == 74250))) |
| 1555 | *n = 8192; |
| 1556 | else |
| 1557 | *n = 4096; |
| 1558 | break; |
| 1559 | case 44100: |
| 1560 | *n = 6272; |
| 1561 | break; |
| 1562 | case 48000: |
| 1563 | if ((deep_color == 125) && ((pclk == 54054) |
| 1564 | || (pclk == 74250))) |
| 1565 | *n = 8192; |
| 1566 | else |
| 1567 | *n = 6144; |
| 1568 | break; |
| 1569 | default: |
| 1570 | *n = 0; |
| 1571 | return -EINVAL; |
| 1572 | } |
| 1573 | |
| 1574 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ |
| 1575 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); |
| 1576 | |
| 1577 | return 0; |
| 1578 | } |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1579 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1580 | static int hdmi_audio_hw_params(struct hdmi_ip_data *ip_data, |
| 1581 | struct snd_pcm_substream *substream, |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1582 | struct snd_pcm_hw_params *params, |
| 1583 | struct snd_soc_dai *dai) |
| 1584 | { |
| 1585 | struct hdmi_audio_format audio_format; |
| 1586 | struct hdmi_audio_dma audio_dma; |
| 1587 | struct hdmi_core_audio_config core_cfg; |
| 1588 | struct hdmi_core_infoframe_audio aud_if_cfg; |
| 1589 | int err, n, cts; |
| 1590 | enum hdmi_core_audio_sample_freq sample_freq; |
| 1591 | |
| 1592 | switch (params_format(params)) { |
| 1593 | case SNDRV_PCM_FORMAT_S16_LE: |
| 1594 | core_cfg.i2s_cfg.word_max_length = |
| 1595 | HDMI_AUDIO_I2S_MAX_WORD_20BITS; |
| 1596 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS; |
| 1597 | core_cfg.i2s_cfg.in_length_bits = |
| 1598 | HDMI_AUDIO_I2S_INPUT_LENGTH_16; |
| 1599 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
| 1600 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; |
| 1601 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; |
| 1602 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
| 1603 | audio_dma.transfer_size = 0x10; |
| 1604 | break; |
| 1605 | case SNDRV_PCM_FORMAT_S24_LE: |
| 1606 | core_cfg.i2s_cfg.word_max_length = |
| 1607 | HDMI_AUDIO_I2S_MAX_WORD_24BITS; |
| 1608 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS; |
| 1609 | core_cfg.i2s_cfg.in_length_bits = |
| 1610 | HDMI_AUDIO_I2S_INPUT_LENGTH_24; |
| 1611 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; |
| 1612 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; |
| 1613 | audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
| 1614 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
| 1615 | audio_dma.transfer_size = 0x20; |
| 1616 | break; |
| 1617 | default: |
| 1618 | return -EINVAL; |
| 1619 | } |
| 1620 | |
| 1621 | switch (params_rate(params)) { |
| 1622 | case 32000: |
| 1623 | sample_freq = HDMI_AUDIO_FS_32000; |
| 1624 | break; |
| 1625 | case 44100: |
| 1626 | sample_freq = HDMI_AUDIO_FS_44100; |
| 1627 | break; |
| 1628 | case 48000: |
| 1629 | sample_freq = HDMI_AUDIO_FS_48000; |
| 1630 | break; |
| 1631 | default: |
| 1632 | return -EINVAL; |
| 1633 | } |
| 1634 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1635 | err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1636 | if (err < 0) |
| 1637 | return err; |
| 1638 | |
| 1639 | /* Audio wrapper config */ |
| 1640 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; |
| 1641 | audio_format.active_chnnls_msk = 0x03; |
| 1642 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; |
| 1643 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; |
| 1644 | /* Disable start/stop signals of IEC 60958 blocks */ |
| 1645 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF; |
| 1646 | |
| 1647 | audio_dma.block_size = 0xC0; |
| 1648 | audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; |
| 1649 | audio_dma.fifo_threshold = 0x20; /* in number of samples */ |
| 1650 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1651 | hdmi_wp_audio_config_dma(ip_data, &audio_dma); |
| 1652 | hdmi_wp_audio_config_format(ip_data, &audio_format); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1653 | |
| 1654 | /* |
| 1655 | * I2S config |
| 1656 | */ |
| 1657 | core_cfg.i2s_cfg.en_high_bitrate_aud = false; |
| 1658 | /* Only used with high bitrate audio */ |
| 1659 | core_cfg.i2s_cfg.cbit_order = false; |
| 1660 | /* Serial data and word select should change on sck rising edge */ |
| 1661 | core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; |
| 1662 | core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; |
| 1663 | /* Set I2S word select polarity */ |
| 1664 | core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT; |
| 1665 | core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; |
| 1666 | /* Set serial data to word select shift. See Phillips spec. */ |
| 1667 | core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; |
| 1668 | /* Enable one of the four available serial data channels */ |
| 1669 | core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; |
| 1670 | |
| 1671 | /* Core audio config */ |
| 1672 | core_cfg.freq_sample = sample_freq; |
| 1673 | core_cfg.n = n; |
| 1674 | core_cfg.cts = cts; |
| 1675 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { |
| 1676 | core_cfg.aud_par_busclk = 0; |
| 1677 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW; |
| 1678 | core_cfg.use_mclk = false; |
| 1679 | } else { |
| 1680 | core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8); |
| 1681 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW; |
| 1682 | core_cfg.use_mclk = true; |
| 1683 | core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS; |
| 1684 | } |
| 1685 | core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; |
| 1686 | core_cfg.en_spdif = false; |
| 1687 | /* Use sample frequency from channel status word */ |
| 1688 | core_cfg.fs_override = true; |
| 1689 | /* Enable ACR packets */ |
| 1690 | core_cfg.en_acr_pkt = true; |
| 1691 | /* Disable direct streaming digital audio */ |
| 1692 | core_cfg.en_dsd_audio = false; |
| 1693 | /* Use parallel audio interface */ |
| 1694 | core_cfg.en_parallel_aud_input = true; |
| 1695 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1696 | hdmi_core_audio_config(ip_data, &core_cfg); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1697 | |
| 1698 | /* |
| 1699 | * Configure packet |
| 1700 | * info frame audio see doc CEA861-D page 74 |
| 1701 | */ |
| 1702 | aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM; |
| 1703 | aud_if_cfg.db1_channel_count = 2; |
| 1704 | aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM; |
| 1705 | aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM; |
| 1706 | aud_if_cfg.db4_channel_alloc = 0x00; |
| 1707 | aud_if_cfg.db5_downmix_inh = false; |
| 1708 | aud_if_cfg.db5_lsv = 0; |
| 1709 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1710 | hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1711 | return 0; |
| 1712 | } |
| 1713 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1714 | static int hdmi_audio_trigger(struct hdmi_ip_data *ip_data, |
| 1715 | struct snd_pcm_substream *substream, int cmd, |
| 1716 | struct snd_soc_dai *dai) |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1717 | { |
| 1718 | int err = 0; |
| 1719 | switch (cmd) { |
| 1720 | case SNDRV_PCM_TRIGGER_START: |
| 1721 | case SNDRV_PCM_TRIGGER_RESUME: |
| 1722 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1723 | REG_FLD_MOD(hdmi_av_base(ip_data), |
| 1724 | HDMI_CORE_AV_AUD_MODE, 1, 0, 0); |
| 1725 | REG_FLD_MOD(hdmi_wp_base(ip_data), |
| 1726 | HDMI_WP_AUDIO_CTRL, 1, 31, 31); |
| 1727 | REG_FLD_MOD(hdmi_wp_base(ip_data), |
| 1728 | HDMI_WP_AUDIO_CTRL, 1, 30, 30); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1729 | break; |
| 1730 | |
| 1731 | case SNDRV_PCM_TRIGGER_STOP: |
| 1732 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 1733 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1734 | REG_FLD_MOD(hdmi_av_base(ip_data), |
| 1735 | HDMI_CORE_AV_AUD_MODE, 0, 0, 0); |
| 1736 | REG_FLD_MOD(hdmi_wp_base(ip_data), |
| 1737 | HDMI_WP_AUDIO_CTRL, 0, 30, 30); |
| 1738 | REG_FLD_MOD(hdmi_wp_base(ip_data), |
| 1739 | HDMI_WP_AUDIO_CTRL, 0, 31, 31); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1740 | break; |
| 1741 | default: |
| 1742 | err = -EINVAL; |
| 1743 | } |
| 1744 | return err; |
| 1745 | } |
| 1746 | |
| 1747 | static int hdmi_audio_startup(struct snd_pcm_substream *substream, |
| 1748 | struct snd_soc_dai *dai) |
| 1749 | { |
| 1750 | if (!hdmi.mode) { |
| 1751 | pr_err("Current video settings do not support audio.\n"); |
| 1752 | return -EIO; |
| 1753 | } |
| 1754 | return 0; |
| 1755 | } |
| 1756 | |
| 1757 | static struct snd_soc_codec_driver hdmi_audio_codec_drv = { |
| 1758 | }; |
| 1759 | |
| 1760 | static struct snd_soc_dai_ops hdmi_audio_codec_ops = { |
| 1761 | .hw_params = hdmi_audio_hw_params, |
| 1762 | .trigger = hdmi_audio_trigger, |
| 1763 | .startup = hdmi_audio_startup, |
| 1764 | }; |
| 1765 | |
| 1766 | static struct snd_soc_dai_driver hdmi_codec_dai_drv = { |
| 1767 | .name = "hdmi-audio-codec", |
| 1768 | .playback = { |
| 1769 | .channels_min = 2, |
| 1770 | .channels_max = 2, |
| 1771 | .rates = SNDRV_PCM_RATE_32000 | |
| 1772 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, |
| 1773 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
| 1774 | SNDRV_PCM_FMTBIT_S24_LE, |
| 1775 | }, |
| 1776 | .ops = &hdmi_audio_codec_ops, |
| 1777 | }; |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 1778 | #endif |
| 1779 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1780 | static int hdmi_get_clocks(struct platform_device *pdev) |
| 1781 | { |
| 1782 | struct clk *clk; |
| 1783 | |
| 1784 | clk = clk_get(&pdev->dev, "sys_clk"); |
| 1785 | if (IS_ERR(clk)) { |
| 1786 | DSSERR("can't get sys_clk\n"); |
| 1787 | return PTR_ERR(clk); |
| 1788 | } |
| 1789 | |
| 1790 | hdmi.sys_clk = clk; |
| 1791 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1792 | return 0; |
| 1793 | } |
| 1794 | |
| 1795 | static void hdmi_put_clocks(void) |
| 1796 | { |
| 1797 | if (hdmi.sys_clk) |
| 1798 | clk_put(hdmi.sys_clk); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1799 | } |
| 1800 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1801 | /* HDMI HW IP initialisation */ |
| 1802 | static int omapdss_hdmihw_probe(struct platform_device *pdev) |
| 1803 | { |
| 1804 | struct resource *hdmi_mem; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1805 | int r; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1806 | |
| 1807 | hdmi.pdata = pdev->dev.platform_data; |
| 1808 | hdmi.pdev = pdev; |
| 1809 | |
| 1810 | mutex_init(&hdmi.lock); |
| 1811 | |
| 1812 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); |
| 1813 | if (!hdmi_mem) { |
| 1814 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); |
| 1815 | return -EINVAL; |
| 1816 | } |
| 1817 | |
| 1818 | /* Base address taken from platform */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1819 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
| 1820 | resource_size(hdmi_mem)); |
| 1821 | if (!hdmi.ip_data.base_wp) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1822 | DSSERR("can't ioremap WP\n"); |
| 1823 | return -ENOMEM; |
| 1824 | } |
| 1825 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1826 | r = hdmi_get_clocks(pdev); |
| 1827 | if (r) { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1828 | iounmap(hdmi.ip_data.base_wp); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1829 | return r; |
| 1830 | } |
| 1831 | |
| 1832 | pm_runtime_enable(&pdev->dev); |
| 1833 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1834 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
| 1835 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; |
| 1836 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; |
| 1837 | hdmi.ip_data.phy_offset = HDMI_PHY; |
| 1838 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1839 | hdmi_panel_init(); |
| 1840 | |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1841 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 1842 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 1843 | |
| 1844 | /* Register ASoC codec DAI */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1845 | r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv, |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1846 | &hdmi_codec_dai_drv, 1); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1847 | if (r) { |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1848 | DSSERR("can't register ASoC HDMI audio codec\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1849 | return r; |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1850 | } |
| 1851 | #endif |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1852 | return 0; |
| 1853 | } |
| 1854 | |
| 1855 | static int omapdss_hdmihw_remove(struct platform_device *pdev) |
| 1856 | { |
| 1857 | hdmi_panel_exit(); |
| 1858 | |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 1859 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 1860 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 1861 | snd_soc_unregister_codec(&pdev->dev); |
| 1862 | #endif |
| 1863 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1864 | pm_runtime_disable(&pdev->dev); |
| 1865 | |
| 1866 | hdmi_put_clocks(); |
| 1867 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 1868 | iounmap(hdmi.ip_data.base_wp); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1869 | |
| 1870 | return 0; |
| 1871 | } |
| 1872 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1873 | static int hdmi_runtime_suspend(struct device *dev) |
| 1874 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1875 | clk_disable(hdmi.sys_clk); |
| 1876 | |
| 1877 | dispc_runtime_put(); |
| 1878 | dss_runtime_put(); |
| 1879 | |
| 1880 | return 0; |
| 1881 | } |
| 1882 | |
| 1883 | static int hdmi_runtime_resume(struct device *dev) |
| 1884 | { |
| 1885 | int r; |
| 1886 | |
| 1887 | r = dss_runtime_get(); |
| 1888 | if (r < 0) |
| 1889 | goto err_get_dss; |
| 1890 | |
| 1891 | r = dispc_runtime_get(); |
| 1892 | if (r < 0) |
| 1893 | goto err_get_dispc; |
| 1894 | |
| 1895 | |
| 1896 | clk_enable(hdmi.sys_clk); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1897 | |
| 1898 | return 0; |
| 1899 | |
| 1900 | err_get_dispc: |
| 1901 | dss_runtime_put(); |
| 1902 | err_get_dss: |
| 1903 | return r; |
| 1904 | } |
| 1905 | |
| 1906 | static const struct dev_pm_ops hdmi_pm_ops = { |
| 1907 | .runtime_suspend = hdmi_runtime_suspend, |
| 1908 | .runtime_resume = hdmi_runtime_resume, |
| 1909 | }; |
| 1910 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1911 | static struct platform_driver omapdss_hdmihw_driver = { |
| 1912 | .probe = omapdss_hdmihw_probe, |
| 1913 | .remove = omapdss_hdmihw_remove, |
| 1914 | .driver = { |
| 1915 | .name = "omapdss_hdmi", |
| 1916 | .owner = THIS_MODULE, |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1917 | .pm = &hdmi_pm_ops, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1918 | }, |
| 1919 | }; |
| 1920 | |
| 1921 | int hdmi_init_platform_driver(void) |
| 1922 | { |
| 1923 | return platform_driver_register(&omapdss_hdmihw_driver); |
| 1924 | } |
| 1925 | |
| 1926 | void hdmi_uninit_platform_driver(void) |
| 1927 | { |
| 1928 | return platform_driver_unregister(&omapdss_hdmihw_driver); |
| 1929 | } |