blob: 1e61250f6ddbfe843e0254c852e856b63c9a2f15 [file] [log] [blame]
Anurag Chouhana53cf212017-12-22 13:24:39 +05301/* Copyright (c) 2011-2015, 2018 The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17#include <linux/delay.h>
18#include <linux/regulator/consumer.h>
19#include <linux/regulator/rpm-smd-regulator.h>
20#include <linux/wcnss_wlan.h>
21#include <linux/semaphore.h>
22#include <linux/list.h>
23#include <linux/slab.h>
24#include <linux/clk.h>
25
26static void __iomem *msm_wcnss_base;
27static LIST_HEAD(power_on_lock_list);
28static DEFINE_MUTEX(list_lock);
29static DEFINE_SEMAPHORE(wcnss_power_on_lock);
30static int auto_detect;
31static int is_power_on;
32
33#define RIVA_PMU_OFFSET 0x28
34
35#define RIVA_SPARE_OFFSET 0x0b4
36#define PRONTO_SPARE_OFFSET 0x1088
37#define NVBIN_DLND_BIT BIT(25)
38
39#define PRONTO_IRIS_REG_READ_OFFSET 0x1134
40#define PRONTO_IRIS_REG_CHIP_ID 0x04
41/* IRIS card chip ID's */
42#define WCN3660 0x0200
43#define WCN3660A 0x0300
44#define WCN3660B 0x0400
45#define WCN3620 0x5111
46#define WCN3620A 0x5112
47#define WCN3610 0x9101
48#define WCN3610V1 0x9110
49
50#define WCNSS_PMU_CFG_IRIS_XO_CFG BIT(3)
51#define WCNSS_PMU_CFG_IRIS_XO_EN BIT(4)
52#define WCNSS_PMU_CFG_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
53
54#define WCNSS_PMU_CFG_IRIS_RESET BIT(7)
55#define WCNSS_PMU_CFG_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
56#define WCNSS_PMU_CFG_IRIS_XO_READ BIT(9)
57#define WCNSS_PMU_CFG_IRIS_XO_READ_STS BIT(10)
58
59#define WCNSS_PMU_CFG_IRIS_XO_MODE 0x6
60#define WCNSS_PMU_CFG_IRIS_XO_MODE_48 (3 << 1)
61
62#define VREG_NULL_CONFIG 0x0000
63#define VREG_GET_REGULATOR_MASK 0x0001
64#define VREG_SET_VOLTAGE_MASK 0x0002
65#define VREG_OPTIMUM_MODE_MASK 0x0004
66#define VREG_ENABLE_MASK 0x0008
67#define VDD_PA "qcom,iris-vddpa"
68
69#define WCNSS_INVALID_IRIS_REG 0xbaadbaad
70
71struct vregs_info {
72 const char * const name;
73 const char * const curr;
74 const char * const volt;
75 int state;
76 bool required;
77 struct regulator *regulator;
78};
79
80/* IRIS regulators for Pronto hardware */
81static struct vregs_info iris_vregs[] = {
82 {"qcom,iris-vddxo", "qcom,iris-vddxo-current",
83 "qcom,iris-vddxo-voltage-level", VREG_NULL_CONFIG, true, NULL},
84 {"qcom,iris-vddrfa", "qcom,iris-vddrfa-current",
85 "qcom,iris-vddrfa-voltage-level", VREG_NULL_CONFIG, true, NULL},
86 {"qcom,iris-vddpa", "qcom,iris-vddpa-current",
87 "qcom,iris-vddpa-voltage-level", VREG_NULL_CONFIG, false, NULL},
88 {"qcom,iris-vdddig", "qcom,iris-vdddig-current",
89 "qcom,iris-vdddig-voltage-level", VREG_NULL_CONFIG, true, NULL},
90};
91
92/* WCNSS regulators for Pronto hardware */
93static struct vregs_info pronto_vregs[] = {
94 {"qcom,pronto-vddmx", "qcom,pronto-vddmx-current",
95 "qcom,vddmx-voltage-level", VREG_NULL_CONFIG, true, NULL},
96 {"qcom,pronto-vddcx", "qcom,pronto-vddcx-current",
97 "qcom,vddcx-voltage-level", VREG_NULL_CONFIG, true, NULL},
98 {"qcom,pronto-vddpx", "qcom,pronto-vddpx-current",
99 "qcom,vddpx-voltage-level", VREG_NULL_CONFIG, true, NULL},
100};
101
102struct host_driver {
103 char name[20];
104 struct list_head list;
105};
106
107enum {
108 IRIS_3660, /* also 3660A and 3680 */
109 IRIS_3620,
110 IRIS_3610
111};
112
113int xo_auto_detect(u32 reg)
114{
115 reg >>= 30;
116
117 switch (reg) {
118 case IRIS_3660:
119 return WCNSS_XO_48MHZ;
120
121 case IRIS_3620:
122 return WCNSS_XO_19MHZ;
123
124 case IRIS_3610:
125 return WCNSS_XO_19MHZ;
126
127 default:
128 return WCNSS_XO_INVALID;
129 }
130}
131
132int wcnss_get_iris_name(char *iris_name)
133{
134 struct wcnss_wlan_config *cfg = NULL;
135 int iris_id;
136
137 cfg = wcnss_get_wlan_config();
138
139 if (cfg) {
140 iris_id = cfg->iris_id;
141 iris_id = iris_id >> 16;
142 } else {
143 return 1;
144 }
145
146 switch (iris_id) {
147 case WCN3660:
148 memcpy(iris_name, "WCN3660", sizeof("WCN3660"));
149 break;
150 case WCN3660A:
151 memcpy(iris_name, "WCN3660A", sizeof("WCN3660A"));
152 break;
153 case WCN3660B:
154 memcpy(iris_name, "WCN3660B", sizeof("WCN3660B"));
155 break;
156 case WCN3620:
157 memcpy(iris_name, "WCN3620", sizeof("WCN3620"));
158 break;
159 case WCN3620A:
160 memcpy(iris_name, "WCN3620A", sizeof("WCN3620A"));
161 break;
162 case WCN3610:
163 memcpy(iris_name, "WCN3610", sizeof("WCN3610"));
164 break;
165 case WCN3610V1:
166 memcpy(iris_name, "WCN3610V1", sizeof("WCN3610V1"));
167 break;
168 default:
169 return 1;
170 }
171
172 return 0;
173}
174EXPORT_SYMBOL(wcnss_get_iris_name);
175
176int validate_iris_chip_id(u32 reg)
177{
178 int iris_id;
179
180 iris_id = reg >> 16;
181
182 switch (iris_id) {
183 case WCN3660:
184 case WCN3660A:
185 case WCN3660B:
186 case WCN3620:
187 case WCN3620A:
188 case WCN3610:
189 case WCN3610V1:
190 return 0;
191 default:
192 return 1;
193 }
194}
195
Anurag Chouhana53cf212017-12-22 13:24:39 +0530196static int
197wcnss_dt_parse_vreg_level(struct device *dev, int index,
198 const char *current_vreg_name, const char *vreg_name,
199 struct vregs_level *vlevel)
200{
201 int ret = 0;
202 /* array used to store nominal, low and high voltage values */
203 u32 voltage_levels[3], current_vreg;
204
205 ret = of_property_read_u32_array(dev->of_node, vreg_name,
206 voltage_levels,
207 ARRAY_SIZE(voltage_levels));
208 if (ret) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530209 wcnss_log(ERR, "error reading %s property\n", vreg_name);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530210 return ret;
211 }
212
213 vlevel[index].nominal_min = voltage_levels[0];
214 vlevel[index].low_power_min = voltage_levels[1];
215 vlevel[index].max_voltage = voltage_levels[2];
216
217 ret = of_property_read_u32(dev->of_node, current_vreg_name,
218 &current_vreg);
219 if (ret) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530220 wcnss_log(ERR, "error reading %s property\n",
221 current_vreg_name);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530222 return ret;
223 }
224
225 vlevel[index].uA_load = current_vreg;
226
227 return ret;
228}
229
230int
231wcnss_parse_voltage_regulator(struct wcnss_wlan_config *wlan_config,
232 struct device *dev)
233{
234 int rc, vreg_i;
235
236 /* Parse pronto voltage regulators from device node */
237 for (vreg_i = 0; vreg_i < PRONTO_REGULATORS; vreg_i++) {
238 pronto_vregs[vreg_i].regulator =
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530239 devm_regulator_get_optional(dev,
240 pronto_vregs[vreg_i].name);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530241 if (IS_ERR(pronto_vregs[vreg_i].regulator)) {
242 if (pronto_vregs[vreg_i].required) {
243 rc = PTR_ERR(pronto_vregs[vreg_i].regulator);
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530244 wcnss_log(ERR,
245 "regulator get of %s failed (%d)\n",
Anurag Chouhana53cf212017-12-22 13:24:39 +0530246 pronto_vregs[vreg_i].name, rc);
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530247 return rc;
Anurag Chouhana53cf212017-12-22 13:24:39 +0530248 } else {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530249 wcnss_log(DBG,
250 "Skip optional regulator configuration: %s\n",
251 pronto_vregs[vreg_i].name);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530252 continue;
253 }
254 }
255
Anurag Chouhana53cf212017-12-22 13:24:39 +0530256 rc = wcnss_dt_parse_vreg_level(dev, vreg_i,
257 pronto_vregs[vreg_i].curr,
258 pronto_vregs[vreg_i].volt,
259 wlan_config->pronto_vlevel);
260 if (rc) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530261 wcnss_log(ERR,
262 "error reading voltage-level property\n");
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530263 return rc;
Anurag Chouhana53cf212017-12-22 13:24:39 +0530264 }
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530265 pronto_vregs[vreg_i].state |= VREG_GET_REGULATOR_MASK;
Anurag Chouhana53cf212017-12-22 13:24:39 +0530266 }
267
268 /* Parse iris voltage regulators from device node */
269 for (vreg_i = 0; vreg_i < IRIS_REGULATORS; vreg_i++) {
270 iris_vregs[vreg_i].regulator =
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530271 devm_regulator_get_optional(dev,
272 iris_vregs[vreg_i].name);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530273 if (IS_ERR(iris_vregs[vreg_i].regulator)) {
274 if (iris_vregs[vreg_i].required) {
275 rc = PTR_ERR(iris_vregs[vreg_i].regulator);
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530276 wcnss_log(ERR,
277 "regulator get of %s failed (%d)\n",
Anurag Chouhana53cf212017-12-22 13:24:39 +0530278 iris_vregs[vreg_i].name, rc);
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530279 return rc;
Anurag Chouhana53cf212017-12-22 13:24:39 +0530280 } else {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530281 wcnss_log(DBG,
282 "Skip optional regulator configuration: %s\n",
283 iris_vregs[vreg_i].name);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530284 continue;
285 }
286 }
287
Anurag Chouhana53cf212017-12-22 13:24:39 +0530288 rc = wcnss_dt_parse_vreg_level(dev, vreg_i,
289 iris_vregs[vreg_i].curr,
290 iris_vregs[vreg_i].volt,
291 wlan_config->iris_vlevel);
292 if (rc) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530293 wcnss_log(ERR,
294 "error reading voltage-level property\n");
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530295 return rc;
Anurag Chouhana53cf212017-12-22 13:24:39 +0530296 }
Sarada Prasanna Garnayak1c873ea2018-03-28 12:59:52 +0530297 iris_vregs[vreg_i].state |= VREG_GET_REGULATOR_MASK;
Anurag Chouhana53cf212017-12-22 13:24:39 +0530298 }
299
300 return 0;
Anurag Chouhana53cf212017-12-22 13:24:39 +0530301}
302
303void wcnss_iris_reset(u32 reg, void __iomem *pmu_conf_reg)
304{
305 /* Reset IRIS */
306 reg |= WCNSS_PMU_CFG_IRIS_RESET;
307 writel_relaxed(reg, pmu_conf_reg);
308
309 /* Wait for PMU_CFG.iris_reg_reset_sts */
310 while (readl_relaxed(pmu_conf_reg) &
311 WCNSS_PMU_CFG_IRIS_RESET_STS)
312 cpu_relax();
313
314 /* Reset iris reset bit */
315 reg &= ~WCNSS_PMU_CFG_IRIS_RESET;
316 writel_relaxed(reg, pmu_conf_reg);
317}
318
319static int
320configure_iris_xo(struct device *dev,
321 struct wcnss_wlan_config *cfg,
322 int on, int *iris_xo_set)
323{
324 u32 reg = 0, i = 0;
325 u32 iris_reg = WCNSS_INVALID_IRIS_REG;
326 int rc = 0;
327 int pmu_offset = 0;
328 int spare_offset = 0;
329 void __iomem *pmu_conf_reg;
330 void __iomem *spare_reg;
331 void __iomem *iris_read_reg;
332 struct clk *clk;
333 struct clk *clk_rf = NULL;
334 bool use_48mhz_xo;
335
336 use_48mhz_xo = cfg->use_48mhz_xo;
337
338 if (wcnss_hardware_type() == WCNSS_PRONTO_HW) {
339 pmu_offset = PRONTO_PMU_OFFSET;
340 spare_offset = PRONTO_SPARE_OFFSET;
341
342 clk = clk_get(dev, "xo");
343 if (IS_ERR(clk)) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530344 wcnss_log(ERR, "Couldn't get xo clock\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530345 return PTR_ERR(clk);
346 }
347
348 } else {
349 pmu_offset = RIVA_PMU_OFFSET;
350 spare_offset = RIVA_SPARE_OFFSET;
351
352 clk = clk_get(dev, "cxo");
353 if (IS_ERR(clk)) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530354 wcnss_log(ERR, "Couldn't get cxo clock\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530355 return PTR_ERR(clk);
356 }
357 }
358
359 if (on) {
360 msm_wcnss_base = cfg->msm_wcnss_base;
361 if (!msm_wcnss_base) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530362 wcnss_log(ERR, "ioremap wcnss physical failed\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530363 goto fail;
364 }
365
366 /* Enable IRIS XO */
367 rc = clk_prepare_enable(clk);
368 if (rc) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530369 wcnss_log(ERR, "clk enable failed\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530370 goto fail;
371 }
372
373 /* NV bit is set to indicate that platform driver is capable
374 * of doing NV download.
375 */
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530376 wcnss_log(DBG, "Indicate NV bin download\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530377 spare_reg = msm_wcnss_base + spare_offset;
378 reg = readl_relaxed(spare_reg);
379 reg |= NVBIN_DLND_BIT;
380 writel_relaxed(reg, spare_reg);
381
382 pmu_conf_reg = msm_wcnss_base + pmu_offset;
383 writel_relaxed(0, pmu_conf_reg);
384 reg = readl_relaxed(pmu_conf_reg);
385 reg |= WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP |
386 WCNSS_PMU_CFG_IRIS_XO_EN;
387 writel_relaxed(reg, pmu_conf_reg);
388
389 if (wcnss_xo_auto_detect_enabled()) {
390 iris_read_reg = msm_wcnss_base +
391 PRONTO_IRIS_REG_READ_OFFSET;
392 iris_reg = readl_relaxed(iris_read_reg);
393 }
394
395 wcnss_iris_reset(reg, pmu_conf_reg);
396
397 if (iris_reg != WCNSS_INVALID_IRIS_REG) {
398 iris_reg &= 0xffff;
399 iris_reg |= PRONTO_IRIS_REG_CHIP_ID;
400 writel_relaxed(iris_reg, iris_read_reg);
401 do {
402 /* Iris read */
403 reg = readl_relaxed(pmu_conf_reg);
404 reg |= WCNSS_PMU_CFG_IRIS_XO_READ;
405 writel_relaxed(reg, pmu_conf_reg);
406
407 /* Wait for PMU_CFG.iris_reg_read_sts */
408 while (readl_relaxed(pmu_conf_reg) &
409 WCNSS_PMU_CFG_IRIS_XO_READ_STS)
410 cpu_relax();
411
412 iris_reg = readl_relaxed(iris_read_reg);
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530413 wcnss_log(INFO, "IRIS Reg: %08x\n", iris_reg);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530414
415 if (validate_iris_chip_id(iris_reg) && i >= 4) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530416 wcnss_log(INFO,
417 "IRIS Card absent/invalid\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530418 auto_detect = WCNSS_XO_INVALID;
419 /* Reset iris read bit */
420 reg &= ~WCNSS_PMU_CFG_IRIS_XO_READ;
421 /* Clear XO_MODE[b2:b1] bits.
422 * Clear implies 19.2 MHz TCXO
423 */
424 reg &= ~(WCNSS_PMU_CFG_IRIS_XO_MODE);
425 goto xo_configure;
426 } else if (!validate_iris_chip_id(iris_reg)) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530427 wcnss_log(DBG,
428 "IRIS Card is present\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530429 break;
430 }
431 reg &= ~WCNSS_PMU_CFG_IRIS_XO_READ;
432 writel_relaxed(reg, pmu_conf_reg);
433 wcnss_iris_reset(reg, pmu_conf_reg);
434 } while (i++ < 5);
435 auto_detect = xo_auto_detect(iris_reg);
436
437 /* Reset iris read bit */
438 reg &= ~WCNSS_PMU_CFG_IRIS_XO_READ;
439
440 } else if (wcnss_xo_auto_detect_enabled()) {
441 /* Default to 48 MHZ */
442 auto_detect = WCNSS_XO_48MHZ;
443 } else {
444 auto_detect = WCNSS_XO_INVALID;
445 }
446
447 cfg->iris_id = iris_reg;
448
449 /* Clear XO_MODE[b2:b1] bits. Clear implies 19.2 MHz TCXO */
450 reg &= ~(WCNSS_PMU_CFG_IRIS_XO_MODE);
451
452 if ((use_48mhz_xo && auto_detect == WCNSS_XO_INVALID) ||
453 auto_detect == WCNSS_XO_48MHZ) {
454 reg |= WCNSS_PMU_CFG_IRIS_XO_MODE_48;
455
456 if (iris_xo_set)
457 *iris_xo_set = WCNSS_XO_48MHZ;
458 }
459
460xo_configure:
461 writel_relaxed(reg, pmu_conf_reg);
462
463 wcnss_iris_reset(reg, pmu_conf_reg);
464
465 /* Start IRIS XO configuration */
466 reg |= WCNSS_PMU_CFG_IRIS_XO_CFG;
467 writel_relaxed(reg, pmu_conf_reg);
468
469 /* Wait for XO configuration to finish */
470 while (readl_relaxed(pmu_conf_reg) &
471 WCNSS_PMU_CFG_IRIS_XO_CFG_STS)
472 cpu_relax();
473
474 /* Stop IRIS XO configuration */
475 reg &= ~(WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP |
476 WCNSS_PMU_CFG_IRIS_XO_CFG);
477 writel_relaxed(reg, pmu_conf_reg);
478 clk_disable_unprepare(clk);
479
480 if ((!use_48mhz_xo && auto_detect == WCNSS_XO_INVALID) ||
481 auto_detect == WCNSS_XO_19MHZ) {
482 clk_rf = clk_get(dev, "rf_clk");
483 if (IS_ERR(clk_rf)) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530484 wcnss_log(ERR, "Couldn't get rf_clk\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530485 goto fail;
486 }
487
488 rc = clk_prepare_enable(clk_rf);
489 if (rc) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530490 wcnss_log(ERR, "clk_rf enable failed\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530491 goto fail;
492 }
493 if (iris_xo_set)
494 *iris_xo_set = WCNSS_XO_19MHZ;
495 }
496
497 } else if ((!use_48mhz_xo && auto_detect == WCNSS_XO_INVALID) ||
498 auto_detect == WCNSS_XO_19MHZ) {
499 clk_rf = clk_get(dev, "rf_clk");
500 if (IS_ERR(clk_rf)) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530501 wcnss_log(ERR, "Couldn't get rf_clk\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530502 goto fail;
503 }
504 clk_disable_unprepare(clk_rf);
505 }
506
507 /* Add some delay for XO to settle */
508 msleep(20);
509
510fail:
511 clk_put(clk);
512
513 if (clk_rf)
514 clk_put(clk_rf);
515
516 return rc;
517}
518
519/* Helper routine to turn off all WCNSS & IRIS vregs */
520static void wcnss_vregs_off(struct vregs_info regulators[], uint size,
521 struct vregs_level *voltage_level)
522{
523 int i, rc = 0;
524 struct wcnss_wlan_config *cfg;
525
526 cfg = wcnss_get_wlan_config();
527
528 if (!cfg) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530529 wcnss_log(ERR, "Failed to get WLAN configuration\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530530 return;
531 }
532
533 /* Regulators need to be turned off in the reverse order */
534 for (i = (size - 1); i >= 0; i--) {
535 if (regulators[i].state == VREG_NULL_CONFIG)
536 continue;
537
538 /* Remove PWM mode */
539 if (regulators[i].state & VREG_OPTIMUM_MODE_MASK) {
540 rc = regulator_set_load(regulators[i].regulator, 0);
541 if (rc < 0) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530542 wcnss_log(ERR,
543 "regulator set load(%s) failed (%d)\n",
Anurag Chouhana53cf212017-12-22 13:24:39 +0530544 regulators[i].name, rc);
545 }
546 }
547
548 /* Set voltage to lowest level */
549 if (regulators[i].state & VREG_SET_VOLTAGE_MASK) {
550 if (cfg->is_pronto_vadc) {
551 if (cfg->vbatt < WCNSS_VBATT_THRESHOLD &&
552 !memcmp(regulators[i].name,
553 VDD_PA, sizeof(VDD_PA))) {
554 voltage_level[i].max_voltage =
555 WCNSS_VBATT_LOW;
556 }
557 }
558
559 rc = regulator_set_voltage(regulators[i].regulator,
560 voltage_level[i].
561 low_power_min,
562 voltage_level[i].
563 max_voltage);
564
565 if (rc)
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530566 wcnss_log(ERR,
567 "regulator_set_voltage(%s) failed (%d)\n",
568 regulators[i].name, rc);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530569 }
570
571 /* Disable regulator */
572 if (regulators[i].state & VREG_ENABLE_MASK) {
573 rc = regulator_disable(regulators[i].regulator);
574 if (rc < 0)
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530575 wcnss_log(ERR, "vreg %s disable failed (%d)\n",
Anurag Chouhana53cf212017-12-22 13:24:39 +0530576 regulators[i].name, rc);
577 }
Anurag Chouhana53cf212017-12-22 13:24:39 +0530578 }
Sarada Prasanna Garnayakbe261352018-03-22 19:19:58 +0530579
Anurag Chouhana53cf212017-12-22 13:24:39 +0530580}
581
582/* Common helper routine to turn on all WCNSS & IRIS vregs */
583static int wcnss_vregs_on(struct device *dev,
584 struct vregs_info regulators[], uint size,
585 struct vregs_level *voltage_level)
586{
587 int i, rc = 0, reg_cnt;
588 struct wcnss_wlan_config *cfg;
589
590 cfg = wcnss_get_wlan_config();
591
592 if (!cfg) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530593 wcnss_log(ERR, "Failed to get WLAN configuration\n");
Anurag Chouhana53cf212017-12-22 13:24:39 +0530594 return -EINVAL;
595 }
596
597 for (i = 0; i < size; i++) {
598 if (regulators[i].state == VREG_NULL_CONFIG)
599 continue;
600
601 reg_cnt = regulator_count_voltages(regulators[i].regulator);
602 /* Set voltage to nominal. Exclude swtiches e.g. LVS */
603 if ((voltage_level[i].nominal_min ||
604 voltage_level[i].max_voltage) && (reg_cnt > 0)) {
605 if (cfg->is_pronto_vadc) {
606 if (cfg->vbatt < WCNSS_VBATT_THRESHOLD &&
607 !memcmp(regulators[i].name,
608 VDD_PA, sizeof(VDD_PA))) {
609 voltage_level[i].nominal_min =
610 WCNSS_VBATT_INITIAL;
611 voltage_level[i].max_voltage =
612 WCNSS_VBATT_LOW;
613 }
614 }
615
616 rc = regulator_set_voltage(regulators[i].regulator,
617 voltage_level[i].nominal_min,
618 voltage_level[i].
619 max_voltage);
620
621 if (rc) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530622 wcnss_log(ERR,
623 "regulator_set_voltage(%s) failed (%d)\n",
Anurag Chouhana53cf212017-12-22 13:24:39 +0530624 regulators[i].name, rc);
625 goto fail;
626 }
627 regulators[i].state |= VREG_SET_VOLTAGE_MASK;
628 }
629
630 /* Vote for PWM/PFM mode if needed */
631 if (voltage_level[i].uA_load && (reg_cnt > 0)) {
632 rc = regulator_set_load(regulators[i].regulator,
633 voltage_level[i].uA_load);
634 if (rc < 0) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530635 wcnss_log(ERR,
636 "regulator set load(%s) failed (%d)\n",
Anurag Chouhana53cf212017-12-22 13:24:39 +0530637 regulators[i].name, rc);
638 goto fail;
639 }
640 regulators[i].state |= VREG_OPTIMUM_MODE_MASK;
641 }
642
643 /* Enable the regulator */
644 rc = regulator_enable(regulators[i].regulator);
645 if (rc) {
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530646 wcnss_log(ERR, "vreg %s enable failed (%d)\n",
Anurag Chouhana53cf212017-12-22 13:24:39 +0530647 regulators[i].name, rc);
648 goto fail;
649 }
650 regulators[i].state |= VREG_ENABLE_MASK;
651 }
652
653 return rc;
654
655fail:
656 wcnss_vregs_off(regulators, size, voltage_level);
657 return rc;
658}
659
660static void wcnss_iris_vregs_off(enum wcnss_hw_type hw_type,
661 struct wcnss_wlan_config *cfg)
662{
663 switch (hw_type) {
664 case WCNSS_PRONTO_HW:
665 wcnss_vregs_off(iris_vregs, ARRAY_SIZE(iris_vregs),
666 cfg->iris_vlevel);
667 break;
668 default:
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530669 wcnss_log(ERR, "%s invalid hardware %d\n", __func__, hw_type);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530670 }
671}
672
673static int wcnss_iris_vregs_on(struct device *dev,
674 enum wcnss_hw_type hw_type,
675 struct wcnss_wlan_config *cfg)
676{
677 int ret = -1;
678
679 switch (hw_type) {
680 case WCNSS_PRONTO_HW:
681 ret = wcnss_vregs_on(dev, iris_vregs, ARRAY_SIZE(iris_vregs),
682 cfg->iris_vlevel);
683 break;
684 default:
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530685 wcnss_log(ERR, "%s invalid hardware %d\n", __func__, hw_type);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530686 }
687 return ret;
688}
689
690static void wcnss_core_vregs_off(enum wcnss_hw_type hw_type,
691 struct wcnss_wlan_config *cfg)
692{
693 switch (hw_type) {
694 case WCNSS_PRONTO_HW:
695 wcnss_vregs_off(pronto_vregs,
696 ARRAY_SIZE(pronto_vregs), cfg->pronto_vlevel);
697 break;
698 default:
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530699 wcnss_log(ERR, "%s invalid hardware %d\n", __func__, hw_type);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530700 }
701}
702
703static int wcnss_core_vregs_on(struct device *dev,
704 enum wcnss_hw_type hw_type,
705 struct wcnss_wlan_config *cfg)
706{
707 int ret = -1;
708
709 switch (hw_type) {
710 case WCNSS_PRONTO_HW:
711 ret = wcnss_vregs_on(dev, pronto_vregs,
712 ARRAY_SIZE(pronto_vregs),
713 cfg->pronto_vlevel);
714 break;
715 default:
Sarada Prasanna Garnayak26afe2b2018-05-01 18:44:44 +0530716 wcnss_log(ERR, "%s invalid hardware %d\n", __func__, hw_type);
Anurag Chouhana53cf212017-12-22 13:24:39 +0530717 }
718
719 return ret;
720}
721
722int wcnss_wlan_power(struct device *dev,
723 struct wcnss_wlan_config *cfg,
724 enum wcnss_opcode on, int *iris_xo_set)
725{
726 int rc = 0;
727 enum wcnss_hw_type hw_type = wcnss_hardware_type();
728
729 down(&wcnss_power_on_lock);
730 if (on) {
731 /* RIVA regulator settings */
732 rc = wcnss_core_vregs_on(dev, hw_type,
733 cfg);
734 if (rc)
735 goto fail_wcnss_on;
736
737 /* IRIS regulator settings */
738 rc = wcnss_iris_vregs_on(dev, hw_type,
739 cfg);
740 if (rc)
741 goto fail_iris_on;
742
743 /* Configure IRIS XO */
744 rc = configure_iris_xo(dev, cfg,
745 WCNSS_WLAN_SWITCH_ON, iris_xo_set);
746 if (rc)
747 goto fail_iris_xo;
748
749 is_power_on = true;
750
751 } else if (is_power_on) {
752 is_power_on = false;
753 configure_iris_xo(dev, cfg,
754 WCNSS_WLAN_SWITCH_OFF, NULL);
755 wcnss_iris_vregs_off(hw_type, cfg);
756 wcnss_core_vregs_off(hw_type, cfg);
757 }
758
759 up(&wcnss_power_on_lock);
760 return rc;
761
762fail_iris_xo:
763 wcnss_iris_vregs_off(hw_type, cfg);
764
765fail_iris_on:
766 wcnss_core_vregs_off(hw_type, cfg);
767
768fail_wcnss_on:
769 up(&wcnss_power_on_lock);
770 return rc;
771}
772EXPORT_SYMBOL(wcnss_wlan_power);
773
774/*
775 * During SSR WCNSS should not be 'powered on' until all the host drivers
776 * finish their shutdown routines. Host drivers use below APIs to
777 * synchronize power-on. WCNSS will not be 'powered on' until all the
778 * requests(to lock power-on) are freed.
779 */
780int wcnss_req_power_on_lock(char *driver_name)
781{
782 struct host_driver *node;
783
784 if (!driver_name)
785 goto err;
786
787 node = kmalloc(sizeof(*node), GFP_KERNEL);
788 if (!node)
789 goto err;
790 strlcpy(node->name, driver_name, sizeof(node->name));
791
792 mutex_lock(&list_lock);
793 /* Lock when the first request is added */
794 if (list_empty(&power_on_lock_list))
795 down(&wcnss_power_on_lock);
796 list_add(&node->list, &power_on_lock_list);
797 mutex_unlock(&list_lock);
798
799 return 0;
800
801err:
802 return -EINVAL;
803}
804EXPORT_SYMBOL(wcnss_req_power_on_lock);
805
806int wcnss_free_power_on_lock(char *driver_name)
807{
808 int ret = -1;
809 struct host_driver *node;
810
811 mutex_lock(&list_lock);
812 list_for_each_entry(node, &power_on_lock_list, list) {
813 if (!strcmp(node->name, driver_name)) {
814 list_del(&node->list);
815 kfree(node);
816 ret = 0;
817 break;
818 }
819 }
820 /* unlock when the last host driver frees the lock */
821 if (list_empty(&power_on_lock_list))
822 up(&wcnss_power_on_lock);
823 mutex_unlock(&list_lock);
824
825 return ret;
826}
827EXPORT_SYMBOL(wcnss_free_power_on_lock);