| Alexey Charkov | 21f47fb | 2010-12-23 13:11:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-vt8500/include/mach/wm8505_regs.h |
| 3 | * |
| 4 | * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | #ifndef __ASM_ARM_ARCH_WM8505_REGS_H |
| 21 | #define __ASM_ARM_ARCH_WM8505_REGS_H |
| 22 | |
| 23 | /* WM8505 Registers Map */ |
| 24 | |
| 25 | #define WM8505_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */ |
| 26 | #define WM8505_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */ |
| 27 | |
| 28 | #define WM8505_DDR_BASE 0xd8000400 /* 1k DDR/DDR2 Memory |
| 29 | Controller */ |
| 30 | #define WM8505_DMA_BASE 0xd8001800 /* 1k DMA Controller */ |
| 31 | #define WM8505_VDMA_BASE 0xd8001c00 /* 1k VDMA */ |
| 32 | #define WM8505_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory |
| 33 | Controller */ |
| 34 | #define WM8505_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */ |
| 35 | #define WM8505_CIPHER_BASE 0xd8006000 /* 4k Cipher */ |
| 36 | #define WM8505_USB_BASE 0xd8007000 /* 2k USB 2.0 Host */ |
| 37 | # define WM8505_EHCI_BASE 0xd8007100 /* EHCI */ |
| 38 | # define WM8505_UHCI_BASE 0xd8007301 /* UHCI */ |
| 39 | #define WM8505_PS2_BASE 0xd8008800 /* 1k PS/2 */ |
| 40 | #define WM8505_NAND_BASE 0xd8009000 /* 1k NAND Controller */ |
| 41 | #define WM8505_NOR_BASE 0xd8009400 /* 1k NOR Controller */ |
| 42 | #define WM8505_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */ |
| 43 | #define WM8505_VPU_BASE 0xd8050000 /* 256 VPU */ |
| 44 | #define WM8505_GOV_BASE 0xd8050300 /* 256 GOV */ |
| 45 | #define WM8505_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */ |
| 46 | #define WM8505_GOVR_BASE 0xd8050800 /* 512 GOVR (frambuffer) */ |
| 47 | #define WM8505_VID_BASE 0xd8050a00 /* 256 VID */ |
| 48 | #define WM8505_SCL_BASE 0xd8050d00 /* 256 SCL */ |
| 49 | #define WM8505_VPP_BASE 0xd8050f00 /* 256 VPP */ |
| 50 | #define WM8505_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */ |
| 51 | #define WM8505_RTC_BASE 0xd8100000 /* 64k RTC */ |
| 52 | #define WM8505_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */ |
| 53 | #define WM8505_SCC_BASE 0xd8120000 /* 64k System Configuration*/ |
| 54 | #define WM8505_PMC_BASE 0xd8130000 /* 64k PMC Configuration */ |
| 55 | #define WM8505_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/ |
| 56 | #define WM8505_SIC_BASE 0xd8150000 /* 64k Secondary IC */ |
| 57 | #define WM8505_UART0_BASE 0xd8200000 /* 64k UART 0 */ |
| 58 | #define WM8505_UART2_BASE 0xd8210000 /* 64k UART 2 */ |
| 59 | #define WM8505_PWM_BASE 0xd8220000 /* 64k PWM Configuration */ |
| 60 | #define WM8505_SPI0_BASE 0xd8240000 /* 64k SPI 0 */ |
| 61 | #define WM8505_SPI1_BASE 0xd8250000 /* 64k SPI 1 */ |
| 62 | #define WM8505_KEYPAD_BASE 0xd8260000 /* 64k Keypad control */ |
| 63 | #define WM8505_CIR_BASE 0xd8270000 /* 64k CIR */ |
| 64 | #define WM8505_I2C0_BASE 0xd8280000 /* 64k I2C 0 */ |
| 65 | #define WM8505_AC97_BASE 0xd8290000 /* 64k AC97 */ |
| 66 | #define WM8505_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */ |
| 67 | #define WM8505_UART1_BASE 0xd82b0000 /* 64k UART 1 */ |
| 68 | #define WM8505_UART3_BASE 0xd82c0000 /* 64k UART 3 */ |
| 69 | #define WM8505_I2C1_BASE 0xd8320000 /* 64k I2C 1 */ |
| 70 | #define WM8505_I2S_BASE 0xd8330000 /* 64k I2S */ |
| 71 | #define WM8505_UART4_BASE 0xd8370000 /* 64k UART 4 */ |
| 72 | #define WM8505_UART5_BASE 0xd8380000 /* 64k UART 5 */ |
| 73 | |
| 74 | #define WM8505_REGS_END_PHYS 0xd838ffff /* End of MMIO registers */ |
| 75 | #define WM8505_REGS_LENGTH (WM8505_REGS_END_PHYS \ |
| 76 | - WM8505_REGS_START_PHYS + 1) |
| 77 | |
| 78 | #endif |