Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1 | /* |
| 2 | * File: arch/blackfin/mach-bf548/head.S |
| 3 | * Based on: arch/blackfin/mach-bf537/head.S |
| 4 | * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne |
| 5 | * |
| 6 | * Created: 1998 |
| 7 | * Description: Startup code for Blackfin BF548 |
| 8 | * |
| 9 | * Modified: |
| 10 | * Copyright 2004-2007 Analog Devices Inc. |
| 11 | * |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, see the file COPYING, or write |
| 26 | * to the Free Software Foundation, Inc., |
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ |
| 29 | |
| 30 | #include <linux/linkage.h> |
Bryan Wu | c051489 | 2008-02-29 12:02:10 +0800 | [diff] [blame] | 31 | #include <linux/init.h> |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 32 | #include <asm/blackfin.h> |
Michael Hennerich | 68e2fc7 | 2008-07-14 16:51:57 +0800 | [diff] [blame] | 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
Bryan Wu | 639f657 | 2008-08-27 10:51:02 +0800 | [diff] [blame] | 34 | #include <asm/clocks.h> |
| 35 | #include <mach/mem_init.h> |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 36 | #endif |
| 37 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 38 | .section .l1.text |
Michael Hennerich | 68e2fc7 | 2008-07-14 16:51:57 +0800 | [diff] [blame] | 39 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 40 | ENTRY(_start_dma_code) |
| 41 | |
| 42 | /* Enable PHY CLK buffer output */ |
| 43 | p0.h = hi(VR_CTL); |
| 44 | p0.l = lo(VR_CTL); |
| 45 | r0.l = w[p0]; |
| 46 | bitset(r0, 14); |
| 47 | w[p0] = r0.l; |
| 48 | ssync; |
| 49 | |
Sonic Zhang | fb5f004 | 2007-12-23 23:02:13 +0800 | [diff] [blame] | 50 | p0.h = hi(SIC_IWR0); |
| 51 | p0.l = lo(SIC_IWR0); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 52 | r0.l = 0x1; |
| 53 | r0.h = 0x0; |
| 54 | [p0] = r0; |
| 55 | SSYNC; |
| 56 | |
| 57 | /* |
| 58 | * Set PLL_CTL |
| 59 | * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors |
| 60 | * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK |
| 61 | * - [7] = output delay (add 200ps of delay to mem signals) |
| 62 | * - [6] = input delay (add 200ps of input delay to mem signals) |
| 63 | * - [5] = PDWN : 1=All Clocks off |
| 64 | * - [3] = STOPCK : 1=Core Clock off |
| 65 | * - [1] = PLL_OFF : 1=Disable Power to PLL |
| 66 | * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL |
| 67 | * all other bits set to zero |
| 68 | */ |
| 69 | |
| 70 | p0.h = hi(PLL_LOCKCNT); |
| 71 | p0.l = lo(PLL_LOCKCNT); |
| 72 | r0 = 0x300(Z); |
| 73 | w[p0] = r0.l; |
| 74 | ssync; |
| 75 | |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 76 | #if defined(CONFIG_BF54x) |
| 77 | P2.H = hi(EBIU_RSTCTL); |
| 78 | P2.L = lo(EBIU_RSTCTL); |
| 79 | R0 = [P2]; |
| 80 | BITSET (R0, 3); |
| 81 | #else |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 82 | P2.H = hi(EBIU_SDGCTL); |
| 83 | P2.L = lo(EBIU_SDGCTL); |
| 84 | R0 = [P2]; |
| 85 | BITSET (R0, 24); |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 86 | #endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 87 | [P2] = R0; |
| 88 | SSYNC; |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 89 | #if defined(CONFIG_BF54x) |
| 90 | .LSRR_MODE: |
| 91 | R0 = [P2]; |
| 92 | CC = BITTST(R0, 4); |
| 93 | if !CC JUMP .LSRR_MODE; |
| 94 | #endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 95 | |
| 96 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ |
| 97 | r0 = r0 << 9; /* Shift it over, */ |
| 98 | r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ |
| 99 | r0 = r1 | r0; |
| 100 | r1 = PLL_BYPASS; /* Bypass the PLL? */ |
| 101 | r1 = r1 << 8; /* Shift it over */ |
| 102 | r0 = r1 | r0; /* add them all together */ |
| 103 | |
| 104 | p0.h = hi(PLL_CTL); |
| 105 | p0.l = lo(PLL_CTL); /* Load the address */ |
| 106 | cli r2; /* Disable interrupts */ |
| 107 | ssync; |
| 108 | w[p0] = r0.l; /* Set the value */ |
| 109 | idle; /* Wait for the PLL to stablize */ |
| 110 | sti r2; /* Enable interrupts */ |
| 111 | |
| 112 | .Lcheck_again: |
| 113 | p0.h = hi(PLL_STAT); |
| 114 | p0.l = lo(PLL_STAT); |
| 115 | R0 = W[P0](Z); |
| 116 | CC = BITTST(R0,5); |
| 117 | if ! CC jump .Lcheck_again; |
| 118 | |
| 119 | /* Configure SCLK & CCLK Dividers */ |
| 120 | r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); |
| 121 | p0.h = hi(PLL_DIV); |
| 122 | p0.l = lo(PLL_DIV); |
| 123 | w[p0] = r0.l; |
| 124 | ssync; |
| 125 | |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 126 | #if defined(CONFIG_BF54x) |
| 127 | P2.H = hi(EBIU_RSTCTL); |
| 128 | P2.L = lo(EBIU_RSTCTL); |
| 129 | R0 = [P2]; |
| 130 | CC = BITTST(R0, 0); |
| 131 | if CC jump .Lskipddrrst; |
| 132 | BITSET (R0, 0); |
| 133 | .Lskipddrrst: |
| 134 | BITCLR (R0, 3); |
| 135 | [P2] = R0; |
| 136 | SSYNC; |
| 137 | |
| 138 | p0.l = lo(EBIU_DDRCTL0); |
| 139 | p0.h = hi(EBIU_DDRCTL0); |
| 140 | r0.l = lo(mem_DDRCTL0); |
| 141 | r0.h = hi(mem_DDRCTL0); |
| 142 | [p0] = r0; |
| 143 | ssync; |
| 144 | |
| 145 | p0.l = lo(EBIU_DDRCTL1); |
| 146 | p0.h = hi(EBIU_DDRCTL1); |
| 147 | r0.l = lo(mem_DDRCTL1); |
| 148 | r0.h = hi(mem_DDRCTL1); |
| 149 | [p0] = r0; |
| 150 | ssync; |
| 151 | |
| 152 | p0.l = lo(EBIU_DDRCTL2); |
| 153 | p0.h = hi(EBIU_DDRCTL2); |
| 154 | r0.l = lo(mem_DDRCTL2); |
| 155 | r0.h = hi(mem_DDRCTL2); |
| 156 | [p0] = r0; |
| 157 | ssync; |
| 158 | #else |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 159 | p0.l = lo(EBIU_SDRRC); |
| 160 | p0.h = hi(EBIU_SDRRC); |
| 161 | r0 = mem_SDRRC; |
| 162 | w[p0] = r0.l; |
| 163 | ssync; |
| 164 | |
Mike Frysinger | e208f83 | 2007-07-25 10:11:42 +0800 | [diff] [blame] | 165 | p0.l = LO(EBIU_SDBCTL); |
| 166 | p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 167 | r0 = mem_SDBCTL; |
| 168 | w[p0] = r0.l; |
| 169 | ssync; |
| 170 | |
| 171 | P2.H = hi(EBIU_SDGCTL); |
| 172 | P2.L = lo(EBIU_SDGCTL); |
| 173 | R0 = [P2]; |
| 174 | BITCLR (R0, 24); |
| 175 | p0.h = hi(EBIU_SDSTAT); |
| 176 | p0.l = lo(EBIU_SDSTAT); |
| 177 | r2.l = w[p0]; |
| 178 | cc = bittst(r2,3); |
| 179 | if !cc jump .Lskip; |
| 180 | NOP; |
| 181 | BITSET (R0, 23); |
| 182 | .Lskip: |
| 183 | [P2] = R0; |
| 184 | SSYNC; |
| 185 | |
| 186 | R0.L = lo(mem_SDGCTL); |
| 187 | R0.H = hi(mem_SDGCTL); |
| 188 | R1 = [p2]; |
| 189 | R1 = R1 | R0; |
| 190 | [P2] = R1; |
| 191 | SSYNC; |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 192 | #endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 193 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 194 | RTS; |
Bryan Wu | c051489 | 2008-02-29 12:02:10 +0800 | [diff] [blame] | 195 | ENDPROC(_start_dma_code) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 196 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ |