Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
| 18 | |
Steven Rostedt | f069686 | 2012-01-25 20:18:55 -0500 | [diff] [blame] | 19 | #include <trace/events/irq.h> |
| 20 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 21 | #include "internals.h" |
| 22 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 23 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 24 | * irq_set_chip - set the irq chip for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 25 | * @irq: irq number |
| 26 | * @chip: pointer to irq chip description structure |
| 27 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 28 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 29 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 30 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 31 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 32 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 33 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 34 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 35 | |
| 36 | if (!chip) |
| 37 | chip = &no_irq_chip; |
| 38 | |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 39 | desc->irq_data.chip = chip; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 40 | irq_put_desc_unlock(desc, flags); |
David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 41 | /* |
| 42 | * For !CONFIG_SPARSE_IRQ make the irq show up in |
| 43 | * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is |
| 44 | * already marked, and this call is harmless. |
| 45 | */ |
| 46 | irq_reserve_irq(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 47 | return 0; |
| 48 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 49 | EXPORT_SYMBOL(irq_set_chip); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 50 | |
| 51 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 52 | * irq_set_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 53 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 54 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 55 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 56 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 57 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 58 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 59 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 60 | int ret = 0; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 61 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 62 | if (!desc) |
| 63 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 64 | |
David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 65 | type &= IRQ_TYPE_SENSE_MASK; |
Russell King | a09b659 | 2012-03-05 15:07:25 -0800 | [diff] [blame] | 66 | ret = __irq_set_trigger(desc, irq, type); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 67 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 68 | return ret; |
| 69 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 70 | EXPORT_SYMBOL(irq_set_irq_type); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 71 | |
| 72 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 73 | * irq_set_handler_data - set irq handler data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 74 | * @irq: Interrupt number |
| 75 | * @data: Pointer to interrupt specific data |
| 76 | * |
| 77 | * Set the hardware irq controller data for an irq |
| 78 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 79 | int irq_set_handler_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 80 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 81 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 82 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 83 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 84 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 85 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 86 | desc->irq_data.handler_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 87 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 88 | return 0; |
| 89 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 90 | EXPORT_SYMBOL(irq_set_handler_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 91 | |
| 92 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 93 | * irq_set_msi_desc - set MSI descriptor data for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 94 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 95 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 96 | * |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 97 | * Set the MSI descriptor entry for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 98 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 99 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 100 | { |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 101 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 102 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 103 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 104 | if (!desc) |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 105 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 106 | desc->irq_data.msi_desc = entry; |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 107 | if (entry) |
| 108 | entry->irq = irq; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 109 | irq_put_desc_unlock(desc, flags); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 110 | return 0; |
| 111 | } |
| 112 | |
| 113 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 114 | * irq_set_chip_data - set irq chip data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 115 | * @irq: Interrupt number |
| 116 | * @data: Pointer to chip specific data |
| 117 | * |
| 118 | * Set the hardware irq chip data for an irq |
| 119 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 120 | int irq_set_chip_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 121 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 122 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 123 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 124 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 125 | if (!desc) |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 126 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 127 | desc->irq_data.chip_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 128 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 129 | return 0; |
| 130 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 131 | EXPORT_SYMBOL(irq_set_chip_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 132 | |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 133 | struct irq_data *irq_get_irq_data(unsigned int irq) |
| 134 | { |
| 135 | struct irq_desc *desc = irq_to_desc(irq); |
| 136 | |
| 137 | return desc ? &desc->irq_data : NULL; |
| 138 | } |
| 139 | EXPORT_SYMBOL_GPL(irq_get_irq_data); |
| 140 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 141 | static void irq_state_clr_disabled(struct irq_desc *desc) |
| 142 | { |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 143 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | static void irq_state_set_disabled(struct irq_desc *desc) |
| 147 | { |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 148 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 149 | } |
| 150 | |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 151 | static void irq_state_clr_masked(struct irq_desc *desc) |
| 152 | { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 153 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static void irq_state_set_masked(struct irq_desc *desc) |
| 157 | { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 158 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 159 | } |
| 160 | |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 161 | int irq_startup(struct irq_desc *desc, bool resend) |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 162 | { |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 163 | int ret = 0; |
| 164 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 165 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 166 | desc->depth = 0; |
| 167 | |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 168 | if (desc->irq_data.chip->irq_startup) { |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 169 | ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 170 | irq_state_clr_masked(desc); |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 171 | } else { |
| 172 | irq_enable(desc); |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 173 | } |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 174 | if (resend) |
| 175 | check_irq_resend(desc, desc->irq_data.irq); |
| 176 | return ret; |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | void irq_shutdown(struct irq_desc *desc) |
| 180 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 181 | irq_state_set_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 182 | desc->depth = 1; |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 183 | if (desc->irq_data.chip->irq_shutdown) |
| 184 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); |
Geert Uytterhoeven | ed585a6 | 2011-09-11 13:59:27 +0200 | [diff] [blame] | 185 | else if (desc->irq_data.chip->irq_disable) |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 186 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 187 | else |
| 188 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 189 | irq_state_set_masked(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 190 | } |
| 191 | |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 192 | void irq_enable(struct irq_desc *desc) |
| 193 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 194 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 195 | if (desc->irq_data.chip->irq_enable) |
| 196 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 197 | else |
| 198 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 199 | irq_state_clr_masked(desc); |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | void irq_disable(struct irq_desc *desc) |
| 203 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 204 | irq_state_set_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 205 | if (desc->irq_data.chip->irq_disable) { |
| 206 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
Thomas Gleixner | a61d825 | 2011-02-21 12:54:34 +0100 | [diff] [blame] | 207 | irq_state_set_masked(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 208 | } |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 209 | } |
| 210 | |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 211 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
| 212 | { |
| 213 | if (desc->irq_data.chip->irq_enable) |
| 214 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 215 | else |
| 216 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
| 217 | cpumask_set_cpu(cpu, desc->percpu_enabled); |
| 218 | } |
| 219 | |
| 220 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) |
| 221 | { |
| 222 | if (desc->irq_data.chip->irq_disable) |
| 223 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 224 | else |
| 225 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
| 226 | cpumask_clear_cpu(cpu, desc->percpu_enabled); |
| 227 | } |
| 228 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 229 | static inline void mask_ack_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 230 | { |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 231 | if (desc->irq_data.chip->irq_mask_ack) |
| 232 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 233 | else { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 234 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 235 | if (desc->irq_data.chip->irq_ack) |
| 236 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 237 | } |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 238 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 239 | } |
| 240 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 241 | void mask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 242 | { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 243 | if (desc->irq_data.chip->irq_mask) { |
| 244 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 245 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 246 | } |
| 247 | } |
| 248 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 249 | void unmask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 250 | { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 251 | if (desc->irq_data.chip->irq_unmask) { |
| 252 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 253 | irq_state_clr_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 254 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 255 | } |
| 256 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 257 | /* |
| 258 | * handle_nested_irq - Handle a nested irq from a irq thread |
| 259 | * @irq: the interrupt number |
| 260 | * |
| 261 | * Handle interrupts which are nested into a threaded interrupt |
| 262 | * handler. The handler function is called inside the calling |
| 263 | * threads context. |
| 264 | */ |
| 265 | void handle_nested_irq(unsigned int irq) |
| 266 | { |
| 267 | struct irq_desc *desc = irq_to_desc(irq); |
| 268 | struct irqaction *action; |
| 269 | irqreturn_t action_ret; |
| 270 | |
| 271 | might_sleep(); |
| 272 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 273 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 274 | |
| 275 | kstat_incr_irqs_this_cpu(irq, desc); |
| 276 | |
| 277 | action = desc->action; |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 278 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 279 | goto out_unlock; |
| 280 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 281 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 282 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 283 | |
| 284 | action_ret = action->thread_fn(action->irq, action->dev_id); |
| 285 | if (!noirqdebug) |
| 286 | note_interrupt(irq, desc, action_ret); |
| 287 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 288 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 289 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 290 | |
| 291 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 292 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 293 | } |
| 294 | EXPORT_SYMBOL_GPL(handle_nested_irq); |
| 295 | |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 296 | static bool irq_check_poll(struct irq_desc *desc) |
| 297 | { |
Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 298 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 299 | return false; |
| 300 | return irq_wait_for_poll(desc); |
| 301 | } |
| 302 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 303 | /** |
| 304 | * handle_simple_irq - Simple and software-decoded IRQs. |
| 305 | * @irq: the interrupt number |
| 306 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 307 | * |
| 308 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 309 | * handler or come from hardware, where no interrupt hardware control |
| 310 | * is necessary. |
| 311 | * |
| 312 | * Note: The caller is expected to handle the ack, clear, mask and |
| 313 | * unmask issues if necessary. |
| 314 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 315 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 316 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 317 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 318 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 319 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 320 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 321 | if (!irq_check_poll(desc)) |
| 322 | goto out_unlock; |
| 323 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 324 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 325 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 326 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 327 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 328 | goto out_unlock; |
| 329 | |
Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 330 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 331 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 332 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 333 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 334 | } |
Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 335 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 336 | |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 337 | /* |
| 338 | * Called unconditionally from handle_level_irq() and only for oneshot |
| 339 | * interrupts from handle_fasteoi_irq() |
| 340 | */ |
| 341 | static void cond_unmask_irq(struct irq_desc *desc) |
| 342 | { |
| 343 | /* |
| 344 | * We need to unmask in the following cases: |
| 345 | * - Standard level irq (IRQF_ONESHOT is not set) |
| 346 | * - Oneshot irq which did not wake the thread (caused by a |
| 347 | * spurious interrupt or a primary handler handling it |
| 348 | * completely). |
| 349 | */ |
| 350 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 351 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) |
| 352 | unmask_irq(desc); |
| 353 | } |
| 354 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 355 | /** |
| 356 | * handle_level_irq - Level type irq handler |
| 357 | * @irq: the interrupt number |
| 358 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 359 | * |
| 360 | * Level type interrupts are active as long as the hardware line has |
| 361 | * the active level. This may require to mask the interrupt and unmask |
| 362 | * it after the associated handler has acknowledged the device, so the |
| 363 | * interrupt line is back to inactive. |
| 364 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 365 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 366 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 367 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 368 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 369 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 370 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 371 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 372 | if (!irq_check_poll(desc)) |
| 373 | goto out_unlock; |
| 374 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 375 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 376 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 377 | |
| 378 | /* |
| 379 | * If its disabled or no action available |
| 380 | * keep it masked and get out of here |
| 381 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 382 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 383 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 384 | |
Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 385 | handle_irq_event(desc); |
Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 386 | |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 387 | cond_unmask_irq(desc); |
| 388 | |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 389 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 390 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 391 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 392 | EXPORT_SYMBOL_GPL(handle_level_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 393 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 394 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
| 395 | static inline void preflow_handler(struct irq_desc *desc) |
| 396 | { |
| 397 | if (desc->preflow_handler) |
| 398 | desc->preflow_handler(&desc->irq_data); |
| 399 | } |
| 400 | #else |
| 401 | static inline void preflow_handler(struct irq_desc *desc) { } |
| 402 | #endif |
| 403 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 404 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 405 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 406 | * @irq: the interrupt number |
| 407 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 408 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 409 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 410 | * call when the interrupt has been serviced. This enables support |
| 411 | * for modern forms of interrupt handlers, which handle the flow |
| 412 | * details in hardware, transparently. |
| 413 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 414 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 415 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 416 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 417 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 418 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 419 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 420 | if (!irq_check_poll(desc)) |
| 421 | goto out; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 422 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 423 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 424 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 425 | |
| 426 | /* |
| 427 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 428 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 429 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 430 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 431 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 432 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 433 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 434 | } |
Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 435 | |
| 436 | if (desc->istate & IRQS_ONESHOT) |
| 437 | mask_irq(desc); |
| 438 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 439 | preflow_handler(desc); |
Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 440 | handle_irq_event(desc); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 441 | |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 442 | if (desc->istate & IRQS_ONESHOT) |
| 443 | cond_unmask_irq(desc); |
| 444 | |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 445 | out_eoi: |
Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 446 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 447 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 448 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 449 | return; |
| 450 | out: |
| 451 | if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
| 452 | goto out_eoi; |
| 453 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 454 | } |
| 455 | |
| 456 | /** |
| 457 | * handle_edge_irq - edge type IRQ handler |
| 458 | * @irq: the interrupt number |
| 459 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 460 | * |
| 461 | * Interrupt occures on the falling and/or rising edge of a hardware |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 462 | * signal. The occurrence is latched into the irq controller hardware |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 463 | * and must be acked in order to be reenabled. After the ack another |
| 464 | * interrupt can happen on the same source even before the first one |
Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 465 | * is handled by the associated event handler. If this happens it |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 466 | * might be necessary to disable (mask) the interrupt depending on the |
| 467 | * controller hardware. This requires to reenable the interrupt inside |
| 468 | * of the loop which handles the interrupts which have arrived while |
| 469 | * the handler was running. If all pending interrupts are handled, the |
| 470 | * loop is left. |
| 471 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 472 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 473 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 474 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 475 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 476 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 477 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 478 | /* |
| 479 | * If we're currently running this IRQ, or its disabled, |
| 480 | * we shouldn't process the IRQ. Mark it pending, handle |
| 481 | * the necessary masking and go out |
| 482 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 483 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || |
| 484 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 485 | if (!irq_check_poll(desc)) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 486 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 487 | mask_ack_irq(desc); |
| 488 | goto out_unlock; |
| 489 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 490 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 491 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 492 | |
| 493 | /* Start handling the irq */ |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 494 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 495 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 496 | do { |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 497 | if (unlikely(!desc->action)) { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 498 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 499 | goto out_unlock; |
| 500 | } |
| 501 | |
| 502 | /* |
| 503 | * When another irq arrived while we were handling |
| 504 | * one, we could have masked the irq. |
| 505 | * Renable it, if it was not disabled in meantime. |
| 506 | */ |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 507 | if (unlikely(desc->istate & IRQS_PENDING)) { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 508 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 509 | irqd_irq_masked(&desc->irq_data)) |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 510 | unmask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 511 | } |
| 512 | |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 513 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 514 | |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 515 | } while ((desc->istate & IRQS_PENDING) && |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 516 | !irqd_irq_disabled(&desc->irq_data)); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 517 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 518 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 519 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 520 | } |
Jiri Kosina | 3911ff3 | 2012-05-13 12:13:15 +0200 | [diff] [blame^] | 521 | EXPORT_SYMBOL(handle_edge_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 522 | |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 523 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
| 524 | /** |
| 525 | * handle_edge_eoi_irq - edge eoi type IRQ handler |
| 526 | * @irq: the interrupt number |
| 527 | * @desc: the interrupt description structure for this irq |
| 528 | * |
| 529 | * Similar as the above handle_edge_irq, but using eoi and w/o the |
| 530 | * mask/unmask logic. |
| 531 | */ |
| 532 | void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc) |
| 533 | { |
| 534 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 535 | |
| 536 | raw_spin_lock(&desc->lock); |
| 537 | |
| 538 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
| 539 | /* |
| 540 | * If we're currently running this IRQ, or its disabled, |
| 541 | * we shouldn't process the IRQ. Mark it pending, handle |
| 542 | * the necessary masking and go out |
| 543 | */ |
| 544 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || |
| 545 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { |
| 546 | if (!irq_check_poll(desc)) { |
| 547 | desc->istate |= IRQS_PENDING; |
| 548 | goto out_eoi; |
| 549 | } |
| 550 | } |
| 551 | kstat_incr_irqs_this_cpu(irq, desc); |
| 552 | |
| 553 | do { |
| 554 | if (unlikely(!desc->action)) |
| 555 | goto out_eoi; |
| 556 | |
| 557 | handle_irq_event(desc); |
| 558 | |
| 559 | } while ((desc->istate & IRQS_PENDING) && |
| 560 | !irqd_irq_disabled(&desc->irq_data)); |
| 561 | |
Stephen Rothwell | ac0e044 | 2011-03-30 10:55:12 +1100 | [diff] [blame] | 562 | out_eoi: |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 563 | chip->irq_eoi(&desc->irq_data); |
| 564 | raw_spin_unlock(&desc->lock); |
| 565 | } |
| 566 | #endif |
| 567 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 568 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 569 | * handle_percpu_irq - Per CPU local irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 570 | * @irq: the interrupt number |
| 571 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 572 | * |
| 573 | * Per CPU interrupts on SMP machines without locking requirements |
| 574 | */ |
Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 575 | void |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 576 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 577 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 578 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 579 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 580 | kstat_incr_irqs_this_cpu(irq, desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 581 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 582 | if (chip->irq_ack) |
| 583 | chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 584 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 585 | handle_irq_event_percpu(desc, desc->action); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 586 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 587 | if (chip->irq_eoi) |
| 588 | chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 589 | } |
| 590 | |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 591 | /** |
| 592 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids |
| 593 | * @irq: the interrupt number |
| 594 | * @desc: the interrupt description structure for this irq |
| 595 | * |
| 596 | * Per CPU interrupts on SMP machines without locking requirements. Same as |
| 597 | * handle_percpu_irq() above but with the following extras: |
| 598 | * |
| 599 | * action->percpu_dev_id is a pointer to percpu variables which |
| 600 | * contain the real device id for the cpu on which this handler is |
| 601 | * called |
| 602 | */ |
| 603 | void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc) |
| 604 | { |
| 605 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 606 | struct irqaction *action = desc->action; |
| 607 | void *dev_id = __this_cpu_ptr(action->percpu_dev_id); |
| 608 | irqreturn_t res; |
| 609 | |
| 610 | kstat_incr_irqs_this_cpu(irq, desc); |
| 611 | |
| 612 | if (chip->irq_ack) |
| 613 | chip->irq_ack(&desc->irq_data); |
| 614 | |
| 615 | trace_irq_handler_entry(irq, action); |
| 616 | res = action->handler(irq, dev_id); |
| 617 | trace_irq_handler_exit(irq, action, res); |
| 618 | |
| 619 | if (chip->irq_eoi) |
| 620 | chip->irq_eoi(&desc->irq_data); |
| 621 | } |
| 622 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 623 | void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 624 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 625 | const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 626 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 627 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 628 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 629 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 630 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 631 | return; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 632 | |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 633 | if (!handle) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 634 | handle = handle_bad_irq; |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 635 | } else { |
| 636 | if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 637 | goto out; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 638 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 639 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 640 | /* Uninstall? */ |
| 641 | if (handle == handle_bad_irq) { |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 642 | if (desc->irq_data.chip != &no_irq_chip) |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 643 | mask_ack_irq(desc); |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 644 | irq_state_set_disabled(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 645 | desc->depth = 1; |
| 646 | } |
| 647 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 648 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 649 | |
| 650 | if (handle != handle_bad_irq && is_chained) { |
Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 651 | irq_settings_set_noprobe(desc); |
| 652 | irq_settings_set_norequest(desc); |
Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 653 | irq_settings_set_nothread(desc); |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 654 | irq_startup(desc, true); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 655 | } |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 656 | out: |
| 657 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 658 | } |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 659 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 660 | |
| 661 | void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 662 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 663 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 664 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 665 | irq_set_chip(irq, chip); |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 666 | __irq_set_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 667 | } |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 668 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 669 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 670 | { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 671 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 672 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 673 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 674 | if (!desc) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 675 | return; |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 676 | irq_settings_clr_and_set(desc, clr, set); |
| 677 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 678 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 679 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 680 | if (irq_settings_has_no_balance_set(desc)) |
| 681 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); |
| 682 | if (irq_settings_is_per_cpu(desc)) |
| 683 | irqd_set(&desc->irq_data, IRQD_PER_CPU); |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 684 | if (irq_settings_can_move_pcntxt(desc)) |
| 685 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); |
Thomas Gleixner | 0ef5ca1 | 2011-03-28 21:59:37 +0200 | [diff] [blame] | 686 | if (irq_settings_is_level(desc)) |
| 687 | irqd_set(&desc->irq_data, IRQD_LEVEL); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 688 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 689 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
| 690 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 691 | irq_put_desc_unlock(desc, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 692 | } |
Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 693 | EXPORT_SYMBOL_GPL(irq_modify_status); |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 694 | |
| 695 | /** |
| 696 | * irq_cpu_online - Invoke all irq_cpu_online functions. |
| 697 | * |
| 698 | * Iterate through all irqs and invoke the chip.irq_cpu_online() |
| 699 | * for each. |
| 700 | */ |
| 701 | void irq_cpu_online(void) |
| 702 | { |
| 703 | struct irq_desc *desc; |
| 704 | struct irq_chip *chip; |
| 705 | unsigned long flags; |
| 706 | unsigned int irq; |
| 707 | |
| 708 | for_each_active_irq(irq) { |
| 709 | desc = irq_to_desc(irq); |
| 710 | if (!desc) |
| 711 | continue; |
| 712 | |
| 713 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 714 | |
| 715 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 716 | if (chip && chip->irq_cpu_online && |
| 717 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 718 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 719 | chip->irq_cpu_online(&desc->irq_data); |
| 720 | |
| 721 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 722 | } |
| 723 | } |
| 724 | |
| 725 | /** |
| 726 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. |
| 727 | * |
| 728 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() |
| 729 | * for each. |
| 730 | */ |
| 731 | void irq_cpu_offline(void) |
| 732 | { |
| 733 | struct irq_desc *desc; |
| 734 | struct irq_chip *chip; |
| 735 | unsigned long flags; |
| 736 | unsigned int irq; |
| 737 | |
| 738 | for_each_active_irq(irq) { |
| 739 | desc = irq_to_desc(irq); |
| 740 | if (!desc) |
| 741 | continue; |
| 742 | |
| 743 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 744 | |
| 745 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 746 | if (chip && chip->irq_cpu_offline && |
| 747 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 748 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 749 | chip->irq_cpu_offline(&desc->irq_data); |
| 750 | |
| 751 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 752 | } |
| 753 | } |