blob: 444e7bea23bcbe81ac5005177f13e12e27192caf [file] [log] [blame]
Sam Ravnborgf5e706a2008-07-17 21:55:51 -07001#ifndef _SPARC64_FUTEX_H
2#define _SPARC64_FUTEX_H
3
4#include <linux/futex.h>
5#include <linux/uaccess.h>
6#include <asm/errno.h>
7#include <asm/system.h>
8
9#define __futex_cas_op(insn, ret, oldval, uaddr, oparg) \
10 __asm__ __volatile__( \
11 "\n1: lduwa [%3] %%asi, %2\n" \
12 " " insn "\n" \
13 "2: casa [%3] %%asi, %2, %1\n" \
14 " cmp %2, %1\n" \
15 " bne,pn %%icc, 1b\n" \
16 " mov 0, %0\n" \
17 "3:\n" \
18 " .section .fixup,#alloc,#execinstr\n" \
19 " .align 4\n" \
20 "4: sethi %%hi(3b), %0\n" \
21 " jmpl %0 + %%lo(3b), %%g0\n" \
22 " mov %5, %0\n" \
23 " .previous\n" \
24 " .section __ex_table,\"a\"\n" \
25 " .align 4\n" \
26 " .word 1b, 4b\n" \
27 " .word 2b, 4b\n" \
28 " .previous\n" \
29 : "=&r" (ret), "=&r" (oldval), "=&r" (tem) \
30 : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \
31 : "memory")
32
Michel Lespinasse8d7718a2011-03-10 18:50:58 -080033static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070034{
35 int op = (encoded_op >> 28) & 7;
36 int cmp = (encoded_op >> 24) & 15;
37 int oparg = (encoded_op << 8) >> 20;
38 int cmparg = (encoded_op << 20) >> 20;
39 int oldval = 0, ret, tem;
40
Michel Lespinasse8d7718a2011-03-10 18:50:58 -080041 if (unlikely(!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))))
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070042 return -EFAULT;
43 if (unlikely((((unsigned long) uaddr) & 0x3UL)))
44 return -EINVAL;
45
46 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
47 oparg = 1 << oparg;
48
49 pagefault_disable();
50
51 switch (op) {
52 case FUTEX_OP_SET:
53 __futex_cas_op("mov\t%4, %1", ret, oldval, uaddr, oparg);
54 break;
55 case FUTEX_OP_ADD:
56 __futex_cas_op("add\t%2, %4, %1", ret, oldval, uaddr, oparg);
57 break;
58 case FUTEX_OP_OR:
59 __futex_cas_op("or\t%2, %4, %1", ret, oldval, uaddr, oparg);
60 break;
61 case FUTEX_OP_ANDN:
Mikael Petterssond72609e2008-07-30 15:40:50 -070062 __futex_cas_op("andn\t%2, %4, %1", ret, oldval, uaddr, oparg);
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070063 break;
64 case FUTEX_OP_XOR:
65 __futex_cas_op("xor\t%2, %4, %1", ret, oldval, uaddr, oparg);
66 break;
67 default:
68 ret = -ENOSYS;
69 }
70
71 pagefault_enable();
72
73 if (!ret) {
74 switch (cmp) {
75 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
76 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
77 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
78 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
79 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
80 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
81 default: ret = -ENOSYS;
82 }
83 }
84 return ret;
85}
86
87static inline int
Michel Lespinasse8d7718a2011-03-10 18:50:58 -080088futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
89 u32 oldval, u32 newval)
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070090{
Michel Lespinasse37a9d912011-03-10 18:48:51 -080091 int ret = 0;
92
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070093 __asm__ __volatile__(
Michel Lespinasse37a9d912011-03-10 18:48:51 -080094 "\n1: casa [%4] %%asi, %3, %1\n"
Sam Ravnborgf5e706a2008-07-17 21:55:51 -070095 "2:\n"
96 " .section .fixup,#alloc,#execinstr\n"
97 " .align 4\n"
98 "3: sethi %%hi(2b), %0\n"
99 " jmpl %0 + %%lo(2b), %%g0\n"
Michel Lespinasse37a9d912011-03-10 18:48:51 -0800100 " mov %5, %0\n"
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700101 " .previous\n"
102 " .section __ex_table,\"a\"\n"
103 " .align 4\n"
104 " .word 1b, 3b\n"
105 " .previous\n"
Michel Lespinasse37a9d912011-03-10 18:48:51 -0800106 : "+r" (ret), "=r" (newval)
107 : "1" (newval), "r" (oldval), "r" (uaddr), "i" (-EFAULT)
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700108 : "memory");
109
Michel Lespinasse37a9d912011-03-10 18:48:51 -0800110 *uval = newval;
111 return ret;
Sam Ravnborgf5e706a2008-07-17 21:55:51 -0700112}
113
114#endif /* !(_SPARC64_FUTEX_H) */