Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 1 | #ifndef __SPARC64_PCI_H |
| 2 | #define __SPARC64_PCI_H |
| 3 | |
| 4 | #ifdef __KERNEL__ |
| 5 | |
| 6 | #include <linux/dma-mapping.h> |
| 7 | |
| 8 | /* Can be used to override the logic in pci_scan_bus for skipping |
| 9 | * already-configured bus numbers - to be used for buggy BIOSes |
| 10 | * or architectures with incomplete PCI setup by the loader. |
| 11 | */ |
| 12 | #define pcibios_assign_all_busses() 0 |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 13 | |
| 14 | #define PCIBIOS_MIN_IO 0UL |
| 15 | #define PCIBIOS_MIN_MEM 0UL |
| 16 | |
| 17 | #define PCI_IRQ_NONE 0xffffffff |
| 18 | |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 19 | static inline void pcibios_penalize_isa_irq(int irq, int active) |
| 20 | { |
| 21 | /* We don't do dynamic PCI IRQ allocation */ |
| 22 | } |
| 23 | |
| 24 | /* The PCI address space does not equal the physical memory |
| 25 | * address space. The networking and block device layers use |
| 26 | * this boolean for bounce buffer decisions. |
| 27 | */ |
| 28 | #define PCI_DMA_BUS_IS_PHYS (0) |
| 29 | |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 30 | /* PCI IOMMU mapping bypass support. */ |
| 31 | |
| 32 | /* PCI 64-bit addressing works for all slots on all controller |
| 33 | * types on sparc64. However, it requires that the device |
| 34 | * can drive enough of the 64 bits. |
| 35 | */ |
FUJITA Tomonori | 4ad9b20 | 2010-10-27 15:34:47 -0700 | [diff] [blame] | 36 | #define PCI64_REQUIRED_MASK (~(u64)0) |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 37 | #define PCI64_ADDR_BASE 0xfffc000000000000UL |
| 38 | |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 39 | #ifdef CONFIG_PCI |
| 40 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
| 41 | enum pci_dma_burst_strategy *strat, |
| 42 | unsigned long *strategy_parameter) |
| 43 | { |
| 44 | unsigned long cacheline_size; |
| 45 | u8 byte; |
| 46 | |
| 47 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); |
| 48 | if (byte == 0) |
| 49 | cacheline_size = 1024; |
| 50 | else |
| 51 | cacheline_size = (int) byte * 4; |
| 52 | |
| 53 | *strat = PCI_DMA_BURST_BOUNDARY; |
| 54 | *strategy_parameter = cacheline_size; |
| 55 | } |
| 56 | #endif |
| 57 | |
| 58 | /* Return the index of the PCI controller for device PDEV. */ |
| 59 | |
| 60 | extern int pci_domain_nr(struct pci_bus *bus); |
| 61 | static inline int pci_proc_domain(struct pci_bus *bus) |
| 62 | { |
| 63 | return 1; |
| 64 | } |
| 65 | |
| 66 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ |
| 67 | |
| 68 | #define HAVE_PCI_MMAP |
| 69 | #define HAVE_ARCH_PCI_GET_UNMAPPED_AREA |
| 70 | #define get_pci_unmapped_area get_fb_unmapped_area |
| 71 | |
| 72 | extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
| 73 | enum pci_mmap_state mmap_state, |
| 74 | int write_combine); |
| 75 | |
| 76 | extern void |
| 77 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
| 78 | struct resource *res); |
| 79 | |
| 80 | extern void |
| 81 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
| 82 | struct pci_bus_region *region); |
| 83 | |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 84 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) |
| 85 | { |
| 86 | return PCI_IRQ_NONE; |
| 87 | } |
| 88 | |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 89 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER |
| 90 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, |
| 91 | const struct resource *rsrc, |
| 92 | resource_size_t *start, resource_size_t *end); |
| 93 | #endif /* __KERNEL__ */ |
| 94 | |
| 95 | #endif /* __SPARC64_PCI_H */ |