| Sachin Bhayare | 2d28642 | 2018-02-13 19:55:23 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
| 14 | mdss_dsi0_pll: qcom,mdss_dsi_pll@1a94a00 { |
| 15 | compatible = "qcom,mdss_dsi_pll_8937"; |
| 16 | label = "MDSS DSI 0 PLL"; |
| 17 | cell-index = <0>; |
| 18 | #clock-cells = <1>; |
| 19 | |
| 20 | reg = <0x001a94a00 0xd4>, |
| 21 | <0x0184d074 0x8>; |
| 22 | reg-names = "pll_base", "gdsc_base"; |
| 23 | |
| 24 | gdsc-supply = <&gdsc_mdss>; |
| 25 | vddio-supply = <&pm8937_l6>; |
| 26 | |
| 27 | clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>; |
| 28 | clock-names = "iface_clk"; |
| 29 | clock-rate = <0>; |
| 30 | qcom,dsi-pll-ssc-en; |
| 31 | qcom,dsi-pll-ssc-mode = "down-spread"; |
| 32 | qcom,ssc-frequency-hz = <30000>; |
| 33 | qcom,ssc-ppm = <5000>; |
| 34 | |
| 35 | qcom,platform-supply-entries { |
| 36 | #address-cells = <1>; |
| 37 | #size-cells = <0>; |
| 38 | |
| 39 | qcom,platform-supply-entry@0 { |
| 40 | reg = <0>; |
| 41 | qcom,supply-name = "gdsc"; |
| 42 | qcom,supply-min-voltage = <0>; |
| 43 | qcom,supply-max-voltage = <0>; |
| 44 | qcom,supply-enable-load = <0>; |
| 45 | qcom,supply-disable-load = <0>; |
| 46 | }; |
| 47 | |
| 48 | qcom,platform-supply-entry@1 { |
| 49 | reg = <1>; |
| 50 | qcom,supply-name = "vddio"; |
| 51 | qcom,supply-min-voltage = <1800000>; |
| 52 | qcom,supply-max-voltage = <1800000>; |
| 53 | qcom,supply-enable-load = <100000>; |
| 54 | qcom,supply-disable-load = <100>; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
| 58 | |
| 59 | mdss_dsi1_pll: qcom,mdss_dsi_pll@1a96a00 { |
| 60 | compatible = "qcom,mdss_dsi_pll_8937"; |
| 61 | label = "MDSS DSI 1 PLL"; |
| 62 | cell-index = <1>; |
| 63 | #clock-cells = <1>; |
| 64 | |
| 65 | reg = <0x001a96a00 0xd4>, |
| 66 | <0x0184d074 0x8>; |
| 67 | reg-names = "pll_base", "gdsc_base"; |
| 68 | |
| 69 | gdsc-supply = <&gdsc_mdss>; |
| 70 | vddio-supply = <&pm8937_l6>; |
| 71 | |
| 72 | clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>; |
| 73 | clock-names = "iface_clk"; |
| 74 | clock-rate = <0>; |
| 75 | qcom,dsi-pll-ssc-en; |
| 76 | qcom,dsi-pll-ssc-mode = "down-spread"; |
| 77 | qcom,ssc-frequency-hz = <30000>; |
| 78 | qcom,ssc-ppm = <5000>; |
| 79 | |
| 80 | qcom,platform-supply-entries { |
| 81 | #address-cells = <1>; |
| 82 | #size-cells = <0>; |
| 83 | |
| 84 | qcom,platform-supply-entry@0 { |
| 85 | reg = <0>; |
| 86 | qcom,supply-name = "gdsc"; |
| 87 | qcom,supply-min-voltage = <0>; |
| 88 | qcom,supply-max-voltage = <0>; |
| 89 | qcom,supply-enable-load = <0>; |
| 90 | qcom,supply-disable-load = <0>; |
| 91 | }; |
| 92 | |
| 93 | qcom,platform-supply-entry@1 { |
| 94 | reg = <1>; |
| 95 | qcom,supply-name = "vddio"; |
| 96 | qcom,supply-min-voltage = <1800000>; |
| 97 | qcom,supply-max-voltage = <1800000>; |
| 98 | qcom,supply-enable-load = <100000>; |
| 99 | qcom,supply-disable-load = <100>; |
| 100 | }; |
| 101 | }; |
| 102 | }; |
| 103 | }; |