| Paul Mundt | 1d6a21b | 2012-08-01 17:13:46 +0900 | [diff] [blame] | 1 | config SH_INTC |
| 2 | def_bool y |
| 3 | select IRQ_DOMAIN |
| 4 | |
| Paul Mundt | 33fc1a2 | 2010-10-06 15:38:16 +0900 | [diff] [blame] | 5 | comment "Interrupt controller options" |
| 6 | |
| 7 | config INTC_USERIMASK |
| 8 | bool "Userspace interrupt masking support" |
| Geert Uytterhoeven | 39c5abb | 2014-05-22 20:00:06 +0200 | [diff] [blame^] | 9 | depends on (SUPERH && CPU_SH4A) || COMPILE_TEST |
| Paul Mundt | 33fc1a2 | 2010-10-06 15:38:16 +0900 | [diff] [blame] | 10 | help |
| 11 | This enables support for hardware-assisted userspace hardirq |
| 12 | masking. |
| 13 | |
| 14 | SH-4A and newer interrupt blocks all support a special shadowed |
| 15 | page with all non-masking registers obscured when mapped in to |
| 16 | userspace. This is primarily for use by userspace device |
| 17 | drivers that are using special priority levels. |
| 18 | |
| 19 | If in doubt, say N. |
| 20 | |
| 21 | config INTC_BALANCING |
| 22 | bool "Hardware IRQ balancing support" |
| 23 | depends on SMP && SUPERH && CPU_SHX3 |
| 24 | help |
| 25 | This enables support for IRQ auto-distribution mode on SH-X3 |
| 26 | SMP parts. All of the balancing and CPU wakeup decisions are |
| 27 | taken care of automatically by hardware for distributed |
| 28 | vectors. |
| 29 | |
| 30 | If in doubt, say N. |
| 31 | |
| 32 | config INTC_MAPPING_DEBUG |
| 33 | bool "Expose IRQ to per-controller id mapping via debugfs" |
| 34 | depends on DEBUG_FS |
| 35 | help |
| 36 | This will create a debugfs entry for showing the relationship |
| 37 | between system IRQs and the per-controller id tables. |
| 38 | |
| 39 | If in doubt, say N. |