Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1 | /* |
| 2 | * QLogic iSCSI HBA Driver |
Vikas Chaudhary | c68cdbf | 2012-08-22 07:55:09 -0400 | [diff] [blame] | 3 | * Copyright (c) 2003-2012 QLogic Corporation |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 4 | * |
| 5 | * See LICENSE.qla4xxx for copyright and licensing details. |
| 6 | */ |
| 7 | #include <linux/delay.h> |
Jiri Slaby | a6751cc | 2010-09-14 14:12:54 +0200 | [diff] [blame] | 8 | #include <linux/io.h> |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 9 | #include <linux/pci.h> |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 10 | #include <linux/ratelimit.h> |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 11 | #include "ql4_def.h" |
| 12 | #include "ql4_glbl.h" |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 13 | #include "ql4_inline.h" |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 14 | |
Hitoshi Mitake | 797a796 | 2012-02-07 11:45:33 +0900 | [diff] [blame] | 15 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
| 16 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 17 | #define MASK(n) DMA_BIT_MASK(n) |
| 18 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 19 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 20 | #define MS_WIN(addr) (addr & 0x0ffc0000) |
| 21 | #define QLA82XX_PCI_MN_2M (0) |
| 22 | #define QLA82XX_PCI_MS_2M (0x80000) |
| 23 | #define QLA82XX_PCI_OCM0_2M (0xc0000) |
| 24 | #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) |
| 25 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) |
| 26 | |
| 27 | /* CRB window related */ |
| 28 | #define CRB_BLK(off) ((off >> 20) & 0x3f) |
| 29 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) |
| 30 | #define CRB_WINDOW_2M (0x130060) |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 31 | #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 32 | ((off) & 0xf0000)) |
| 33 | #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) |
| 34 | #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) |
| 35 | #define CRB_INDIRECT_2M (0x1e0000UL) |
| 36 | |
| 37 | static inline void __iomem * |
| 38 | qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) |
| 39 | { |
| 40 | if ((off < ha->first_page_group_end) && |
| 41 | (off >= ha->first_page_group_start)) |
| 42 | return (void __iomem *)(ha->nx_pcibase + off); |
| 43 | |
| 44 | return NULL; |
| 45 | } |
| 46 | |
| 47 | #define MAX_CRB_XFORM 60 |
| 48 | static unsigned long crb_addr_xform[MAX_CRB_XFORM]; |
| 49 | static int qla4_8xxx_crb_table_initialized; |
| 50 | |
| 51 | #define qla4_8xxx_crb_addr_transform(name) \ |
| 52 | (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ |
| 53 | QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) |
| 54 | static void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 55 | qla4_82xx_crb_addr_transform_setup(void) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 56 | { |
| 57 | qla4_8xxx_crb_addr_transform(XDMA); |
| 58 | qla4_8xxx_crb_addr_transform(TIMR); |
| 59 | qla4_8xxx_crb_addr_transform(SRE); |
| 60 | qla4_8xxx_crb_addr_transform(SQN3); |
| 61 | qla4_8xxx_crb_addr_transform(SQN2); |
| 62 | qla4_8xxx_crb_addr_transform(SQN1); |
| 63 | qla4_8xxx_crb_addr_transform(SQN0); |
| 64 | qla4_8xxx_crb_addr_transform(SQS3); |
| 65 | qla4_8xxx_crb_addr_transform(SQS2); |
| 66 | qla4_8xxx_crb_addr_transform(SQS1); |
| 67 | qla4_8xxx_crb_addr_transform(SQS0); |
| 68 | qla4_8xxx_crb_addr_transform(RPMX7); |
| 69 | qla4_8xxx_crb_addr_transform(RPMX6); |
| 70 | qla4_8xxx_crb_addr_transform(RPMX5); |
| 71 | qla4_8xxx_crb_addr_transform(RPMX4); |
| 72 | qla4_8xxx_crb_addr_transform(RPMX3); |
| 73 | qla4_8xxx_crb_addr_transform(RPMX2); |
| 74 | qla4_8xxx_crb_addr_transform(RPMX1); |
| 75 | qla4_8xxx_crb_addr_transform(RPMX0); |
| 76 | qla4_8xxx_crb_addr_transform(ROMUSB); |
| 77 | qla4_8xxx_crb_addr_transform(SN); |
| 78 | qla4_8xxx_crb_addr_transform(QMN); |
| 79 | qla4_8xxx_crb_addr_transform(QMS); |
| 80 | qla4_8xxx_crb_addr_transform(PGNI); |
| 81 | qla4_8xxx_crb_addr_transform(PGND); |
| 82 | qla4_8xxx_crb_addr_transform(PGN3); |
| 83 | qla4_8xxx_crb_addr_transform(PGN2); |
| 84 | qla4_8xxx_crb_addr_transform(PGN1); |
| 85 | qla4_8xxx_crb_addr_transform(PGN0); |
| 86 | qla4_8xxx_crb_addr_transform(PGSI); |
| 87 | qla4_8xxx_crb_addr_transform(PGSD); |
| 88 | qla4_8xxx_crb_addr_transform(PGS3); |
| 89 | qla4_8xxx_crb_addr_transform(PGS2); |
| 90 | qla4_8xxx_crb_addr_transform(PGS1); |
| 91 | qla4_8xxx_crb_addr_transform(PGS0); |
| 92 | qla4_8xxx_crb_addr_transform(PS); |
| 93 | qla4_8xxx_crb_addr_transform(PH); |
| 94 | qla4_8xxx_crb_addr_transform(NIU); |
| 95 | qla4_8xxx_crb_addr_transform(I2Q); |
| 96 | qla4_8xxx_crb_addr_transform(EG); |
| 97 | qla4_8xxx_crb_addr_transform(MN); |
| 98 | qla4_8xxx_crb_addr_transform(MS); |
| 99 | qla4_8xxx_crb_addr_transform(CAS2); |
| 100 | qla4_8xxx_crb_addr_transform(CAS1); |
| 101 | qla4_8xxx_crb_addr_transform(CAS0); |
| 102 | qla4_8xxx_crb_addr_transform(CAM); |
| 103 | qla4_8xxx_crb_addr_transform(C2C1); |
| 104 | qla4_8xxx_crb_addr_transform(C2C0); |
| 105 | qla4_8xxx_crb_addr_transform(SMB); |
| 106 | qla4_8xxx_crb_addr_transform(OCM0); |
| 107 | qla4_8xxx_crb_addr_transform(I2C0); |
| 108 | |
| 109 | qla4_8xxx_crb_table_initialized = 1; |
| 110 | } |
| 111 | |
| 112 | static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { |
| 113 | {{{0, 0, 0, 0} } }, /* 0: PCI */ |
| 114 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ |
| 115 | {1, 0x0110000, 0x0120000, 0x130000}, |
| 116 | {1, 0x0120000, 0x0122000, 0x124000}, |
| 117 | {1, 0x0130000, 0x0132000, 0x126000}, |
| 118 | {1, 0x0140000, 0x0142000, 0x128000}, |
| 119 | {1, 0x0150000, 0x0152000, 0x12a000}, |
| 120 | {1, 0x0160000, 0x0170000, 0x110000}, |
| 121 | {1, 0x0170000, 0x0172000, 0x12e000}, |
| 122 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 123 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 124 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 125 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 126 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 127 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 128 | {1, 0x01e0000, 0x01e0800, 0x122000}, |
| 129 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 130 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ |
| 131 | {{{0, 0, 0, 0} } }, /* 3: */ |
| 132 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ |
| 133 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ |
| 134 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ |
| 135 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ |
| 136 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ |
| 137 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 138 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 139 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 140 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 141 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 142 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 143 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 144 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 145 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 146 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 147 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 148 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 149 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 150 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 151 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, |
| 152 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ |
| 153 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 154 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 155 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 156 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 157 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 158 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 159 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 160 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 161 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 162 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 163 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 164 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 165 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 166 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 167 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, |
| 168 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ |
| 169 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 170 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 171 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 172 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 173 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 174 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 175 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 176 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 177 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 178 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 179 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 180 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 181 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 182 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 183 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, |
| 184 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ |
| 185 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 186 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 187 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 188 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 189 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 190 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 191 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 192 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 193 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 194 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 195 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 196 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 197 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 198 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 199 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, |
| 200 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ |
| 201 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ |
| 202 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ |
| 203 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ |
| 204 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ |
| 205 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ |
| 206 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ |
| 207 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ |
| 208 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ |
| 209 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ |
| 210 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ |
| 211 | {{{0, 0, 0, 0} } }, /* 23: */ |
| 212 | {{{0, 0, 0, 0} } }, /* 24: */ |
| 213 | {{{0, 0, 0, 0} } }, /* 25: */ |
| 214 | {{{0, 0, 0, 0} } }, /* 26: */ |
| 215 | {{{0, 0, 0, 0} } }, /* 27: */ |
| 216 | {{{0, 0, 0, 0} } }, /* 28: */ |
| 217 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ |
| 218 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ |
| 219 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ |
| 220 | {{{0} } }, /* 32: PCI */ |
| 221 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ |
| 222 | {1, 0x2110000, 0x2120000, 0x130000}, |
| 223 | {1, 0x2120000, 0x2122000, 0x124000}, |
| 224 | {1, 0x2130000, 0x2132000, 0x126000}, |
| 225 | {1, 0x2140000, 0x2142000, 0x128000}, |
| 226 | {1, 0x2150000, 0x2152000, 0x12a000}, |
| 227 | {1, 0x2160000, 0x2170000, 0x110000}, |
| 228 | {1, 0x2170000, 0x2172000, 0x12e000}, |
| 229 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 230 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 231 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 232 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 233 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 234 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 235 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 236 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 237 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ |
| 238 | {{{0} } }, /* 35: */ |
| 239 | {{{0} } }, /* 36: */ |
| 240 | {{{0} } }, /* 37: */ |
| 241 | {{{0} } }, /* 38: */ |
| 242 | {{{0} } }, /* 39: */ |
| 243 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ |
| 244 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ |
| 245 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ |
| 246 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ |
| 247 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ |
| 248 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ |
| 249 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ |
| 250 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ |
| 251 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ |
| 252 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ |
| 253 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ |
| 254 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ |
| 255 | {{{0} } }, /* 52: */ |
| 256 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ |
| 257 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ |
| 258 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ |
| 259 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ |
| 260 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ |
| 261 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ |
| 262 | {{{0} } }, /* 59: I2C0 */ |
| 263 | {{{0} } }, /* 60: I2C1 */ |
| 264 | {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ |
| 265 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ |
| 266 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ |
| 267 | }; |
| 268 | |
| 269 | /* |
| 270 | * top 12 bits of crb internal address (hub, agent) |
| 271 | */ |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 272 | static unsigned qla4_82xx_crb_hub_agt[64] = { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 273 | 0, |
| 274 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, |
| 275 | QLA82XX_HW_CRB_HUB_AGT_ADR_MN, |
| 276 | QLA82XX_HW_CRB_HUB_AGT_ADR_MS, |
| 277 | 0, |
| 278 | QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, |
| 279 | QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, |
| 280 | QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, |
| 281 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, |
| 282 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, |
| 283 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, |
| 284 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, |
| 285 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, |
| 286 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, |
| 287 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 288 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, |
| 289 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, |
| 290 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, |
| 291 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, |
| 292 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, |
| 293 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, |
| 294 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, |
| 295 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, |
| 296 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, |
| 297 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, |
| 298 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, |
| 299 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, |
| 300 | 0, |
| 301 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, |
| 302 | QLA82XX_HW_CRB_HUB_AGT_ADR_SN, |
| 303 | 0, |
| 304 | QLA82XX_HW_CRB_HUB_AGT_ADR_EG, |
| 305 | 0, |
| 306 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, |
| 307 | QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, |
| 308 | 0, |
| 309 | 0, |
| 310 | 0, |
| 311 | 0, |
| 312 | 0, |
| 313 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, |
| 314 | 0, |
| 315 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, |
| 316 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, |
| 317 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, |
| 318 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, |
| 319 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, |
| 320 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, |
| 321 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, |
| 322 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, |
| 323 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, |
| 324 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 325 | 0, |
| 326 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, |
| 327 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, |
| 328 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, |
| 329 | QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, |
| 330 | 0, |
| 331 | QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, |
| 332 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, |
| 333 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, |
| 334 | 0, |
| 335 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, |
| 336 | 0, |
| 337 | }; |
| 338 | |
| 339 | /* Device states */ |
| 340 | static char *qdev_state[] = { |
| 341 | "Unknown", |
| 342 | "Cold", |
| 343 | "Initializing", |
| 344 | "Ready", |
| 345 | "Need Reset", |
| 346 | "Need Quiescent", |
| 347 | "Failed", |
| 348 | "Quiescent", |
| 349 | }; |
| 350 | |
| 351 | /* |
| 352 | * In: 'off' is offset from CRB space in 128M pci map |
| 353 | * Out: 'off' is 2M pci map addr |
| 354 | * side effect: lock crb window |
| 355 | */ |
| 356 | static void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 357 | qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 358 | { |
| 359 | u32 win_read; |
| 360 | |
| 361 | ha->crb_win = CRB_HI(*off); |
| 362 | writel(ha->crb_win, |
| 363 | (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); |
| 364 | |
| 365 | /* Read back value to make sure write has gone through before trying |
| 366 | * to use it. */ |
| 367 | win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); |
| 368 | if (win_read != ha->crb_win) { |
| 369 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 370 | "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," |
| 371 | " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); |
| 372 | } |
| 373 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; |
| 374 | } |
| 375 | |
| 376 | void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 377 | qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 378 | { |
| 379 | unsigned long flags = 0; |
| 380 | int rv; |
| 381 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 382 | rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 383 | |
| 384 | BUG_ON(rv == -1); |
| 385 | |
| 386 | if (rv == 1) { |
| 387 | write_lock_irqsave(&ha->hw_lock, flags); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 388 | qla4_82xx_crb_win_lock(ha); |
| 389 | qla4_82xx_pci_set_crbwindow_2M(ha, &off); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 390 | } |
| 391 | |
| 392 | writel(data, (void __iomem *)off); |
| 393 | |
| 394 | if (rv == 1) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 395 | qla4_82xx_crb_win_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 396 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 397 | } |
| 398 | } |
| 399 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 400 | uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 401 | { |
| 402 | unsigned long flags = 0; |
| 403 | int rv; |
| 404 | u32 data; |
| 405 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 406 | rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 407 | |
| 408 | BUG_ON(rv == -1); |
| 409 | |
| 410 | if (rv == 1) { |
| 411 | write_lock_irqsave(&ha->hw_lock, flags); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 412 | qla4_82xx_crb_win_lock(ha); |
| 413 | qla4_82xx_pci_set_crbwindow_2M(ha, &off); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 414 | } |
| 415 | data = readl((void __iomem *)off); |
| 416 | |
| 417 | if (rv == 1) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 418 | qla4_82xx_crb_win_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 419 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 420 | } |
| 421 | return data; |
| 422 | } |
| 423 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 424 | /* Minidump related functions */ |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 425 | int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data) |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 426 | { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 427 | uint32_t win_read, off_value; |
| 428 | int rval = QLA_SUCCESS; |
| 429 | |
| 430 | off_value = off & 0xFFFF0000; |
| 431 | writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); |
| 432 | |
| 433 | /* |
| 434 | * Read back value to make sure write has gone through before trying |
| 435 | * to use it. |
| 436 | */ |
| 437 | win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); |
| 438 | if (win_read != off_value) { |
| 439 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 440 | "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", |
| 441 | __func__, off_value, win_read, off)); |
| 442 | rval = QLA_ERROR; |
| 443 | } else { |
| 444 | off_value = off & 0x0000FFFF; |
| 445 | *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + |
| 446 | ha->nx_pcibase)); |
| 447 | } |
| 448 | return rval; |
| 449 | } |
| 450 | |
| 451 | int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data) |
| 452 | { |
| 453 | uint32_t win_read, off_value; |
| 454 | int rval = QLA_SUCCESS; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 455 | |
| 456 | off_value = off & 0xFFFF0000; |
| 457 | writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); |
| 458 | |
| 459 | /* Read back value to make sure write has gone through before trying |
| 460 | * to use it. |
| 461 | */ |
| 462 | win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); |
| 463 | if (win_read != off_value) { |
| 464 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 465 | "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 466 | __func__, off_value, win_read, off)); |
| 467 | rval = QLA_ERROR; |
| 468 | } else { |
| 469 | off_value = off & 0x0000FFFF; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 470 | writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + |
| 471 | ha->nx_pcibase)); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 472 | } |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 473 | return rval; |
| 474 | } |
| 475 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 476 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
| 477 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 478 | int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 479 | { |
| 480 | int i; |
| 481 | int done = 0, timeout = 0; |
| 482 | |
| 483 | while (!done) { |
| 484 | /* acquire semaphore3 from PCI HW block */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 485 | done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 486 | if (done == 1) |
| 487 | break; |
| 488 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) |
| 489 | return -1; |
| 490 | |
| 491 | timeout++; |
| 492 | |
| 493 | /* Yield CPU */ |
| 494 | if (!in_interrupt()) |
| 495 | schedule(); |
| 496 | else { |
| 497 | for (i = 0; i < 20; i++) |
| 498 | cpu_relax(); /*This a nop instr on i386*/ |
| 499 | } |
| 500 | } |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 501 | qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 502 | return 0; |
| 503 | } |
| 504 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 505 | void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 506 | { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 507 | qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 508 | } |
| 509 | |
| 510 | #define IDC_LOCK_TIMEOUT 100000000 |
| 511 | |
| 512 | /** |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 513 | * qla4_82xx_idc_lock - hw_lock |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 514 | * @ha: pointer to adapter structure |
| 515 | * |
| 516 | * General purpose lock used to synchronize access to |
| 517 | * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. |
| 518 | **/ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 519 | int qla4_82xx_idc_lock(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 520 | { |
| 521 | int i; |
| 522 | int done = 0, timeout = 0; |
| 523 | |
| 524 | while (!done) { |
| 525 | /* acquire semaphore5 from PCI HW block */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 526 | done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 527 | if (done == 1) |
| 528 | break; |
| 529 | if (timeout >= IDC_LOCK_TIMEOUT) |
| 530 | return -1; |
| 531 | |
| 532 | timeout++; |
| 533 | |
| 534 | /* Yield CPU */ |
| 535 | if (!in_interrupt()) |
| 536 | schedule(); |
| 537 | else { |
| 538 | for (i = 0; i < 20; i++) |
| 539 | cpu_relax(); /*This a nop instr on i386*/ |
| 540 | } |
| 541 | } |
| 542 | return 0; |
| 543 | } |
| 544 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 545 | void qla4_82xx_idc_unlock(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 546 | { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 547 | qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 548 | } |
| 549 | |
| 550 | int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 551 | qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 552 | { |
| 553 | struct crb_128M_2M_sub_block_map *m; |
| 554 | |
| 555 | if (*off >= QLA82XX_CRB_MAX) |
| 556 | return -1; |
| 557 | |
| 558 | if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { |
| 559 | *off = (*off - QLA82XX_PCI_CAMQM) + |
| 560 | QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; |
| 561 | return 0; |
| 562 | } |
| 563 | |
| 564 | if (*off < QLA82XX_PCI_CRBSPACE) |
| 565 | return -1; |
| 566 | |
| 567 | *off -= QLA82XX_PCI_CRBSPACE; |
| 568 | /* |
| 569 | * Try direct map |
| 570 | */ |
| 571 | |
| 572 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; |
| 573 | |
| 574 | if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { |
| 575 | *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | /* |
| 580 | * Not in direct map, use crb window |
| 581 | */ |
| 582 | return 1; |
| 583 | } |
| 584 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 585 | /* |
| 586 | * check memory access boundary. |
| 587 | * used by test agent. support ddr access only for now |
| 588 | */ |
| 589 | static unsigned long |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 590 | qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 591 | unsigned long long addr, int size) |
| 592 | { |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 593 | if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
| 594 | QLA8XXX_ADDR_DDR_NET_MAX) || |
| 595 | !QLA8XXX_ADDR_IN_RANGE(addr + size - 1, |
| 596 | QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) || |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 597 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { |
| 598 | return 0; |
| 599 | } |
| 600 | return 1; |
| 601 | } |
| 602 | |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 603 | static int qla4_82xx_pci_set_window_warning_count; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 604 | |
| 605 | static unsigned long |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 606 | qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 607 | { |
| 608 | int window; |
| 609 | u32 win_read; |
| 610 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 611 | if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
| 612 | QLA8XXX_ADDR_DDR_NET_MAX)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 613 | /* DDR network side */ |
| 614 | window = MN_WIN(addr); |
| 615 | ha->ddr_mn_window = window; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 616 | qla4_82xx_wr_32(ha, ha->mn_win_crb | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 617 | QLA82XX_PCI_CRBSPACE, window); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 618 | win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 619 | QLA82XX_PCI_CRBSPACE); |
| 620 | if ((win_read << 17) != window) { |
| 621 | ql4_printk(KERN_WARNING, ha, |
| 622 | "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", |
| 623 | __func__, window, win_read); |
| 624 | } |
| 625 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 626 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, |
| 627 | QLA8XXX_ADDR_OCM0_MAX)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 628 | unsigned int temp1; |
| 629 | /* if bits 19:18&17:11 are on */ |
| 630 | if ((addr & 0x00ff800) == 0xff800) { |
| 631 | printk("%s: QM access not handled.\n", __func__); |
| 632 | addr = -1UL; |
| 633 | } |
| 634 | |
| 635 | window = OCM_WIN(addr); |
| 636 | ha->ddr_mn_window = window; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 637 | qla4_82xx_wr_32(ha, ha->mn_win_crb | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 638 | QLA82XX_PCI_CRBSPACE, window); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 639 | win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 640 | QLA82XX_PCI_CRBSPACE); |
| 641 | temp1 = ((window & 0x1FF) << 7) | |
| 642 | ((window & 0x0FFFE0000) >> 17); |
| 643 | if (win_read != temp1) { |
| 644 | printk("%s: Written OCMwin (0x%x) != Read" |
| 645 | " OCMwin (0x%x)\n", __func__, temp1, win_read); |
| 646 | } |
| 647 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; |
| 648 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 649 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 650 | QLA82XX_P3_ADDR_QDR_NET_MAX)) { |
| 651 | /* QDR network side */ |
| 652 | window = MS_WIN(addr); |
| 653 | ha->qdr_sn_window = window; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 654 | qla4_82xx_wr_32(ha, ha->ms_win_crb | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 655 | QLA82XX_PCI_CRBSPACE, window); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 656 | win_read = qla4_82xx_rd_32(ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 657 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); |
| 658 | if (win_read != window) { |
| 659 | printk("%s: Written MSwin (0x%x) != Read " |
| 660 | "MSwin (0x%x)\n", __func__, window, win_read); |
| 661 | } |
| 662 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; |
| 663 | |
| 664 | } else { |
| 665 | /* |
| 666 | * peg gdb frequently accesses memory that doesn't exist, |
| 667 | * this limits the chit chat so debugging isn't slowed down. |
| 668 | */ |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 669 | if ((qla4_82xx_pci_set_window_warning_count++ < 8) || |
| 670 | (qla4_82xx_pci_set_window_warning_count%64 == 0)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 671 | printk("%s: Warning:%s Unknown address range!\n", |
| 672 | __func__, DRIVER_NAME); |
| 673 | } |
| 674 | addr = -1UL; |
| 675 | } |
| 676 | return addr; |
| 677 | } |
| 678 | |
| 679 | /* check if address is in the same windows as the previous access */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 680 | static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 681 | unsigned long long addr) |
| 682 | { |
| 683 | int window; |
| 684 | unsigned long long qdr_max; |
| 685 | |
| 686 | qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; |
| 687 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 688 | if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, |
| 689 | QLA8XXX_ADDR_DDR_NET_MAX)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 690 | /* DDR network side */ |
| 691 | BUG(); /* MN access can not come here */ |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 692 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, |
| 693 | QLA8XXX_ADDR_OCM0_MAX)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 694 | return 1; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 695 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1, |
| 696 | QLA8XXX_ADDR_OCM1_MAX)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 697 | return 1; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 698 | } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 699 | qdr_max)) { |
| 700 | /* QDR network side */ |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 701 | window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 702 | if (ha->qdr_sn_window == window) |
| 703 | return 1; |
| 704 | } |
| 705 | |
| 706 | return 0; |
| 707 | } |
| 708 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 709 | static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 710 | u64 off, void *data, int size) |
| 711 | { |
| 712 | unsigned long flags; |
| 713 | void __iomem *addr; |
| 714 | int ret = 0; |
| 715 | u64 start; |
| 716 | void __iomem *mem_ptr = NULL; |
| 717 | unsigned long mem_base; |
| 718 | unsigned long mem_page; |
| 719 | |
| 720 | write_lock_irqsave(&ha->hw_lock, flags); |
| 721 | |
| 722 | /* |
| 723 | * If attempting to access unknown address or straddle hw windows, |
| 724 | * do not access. |
| 725 | */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 726 | start = qla4_82xx_pci_set_window(ha, off); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 727 | if ((start == -1UL) || |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 728 | (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 729 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 730 | printk(KERN_ERR"%s out of bound pci memory access. " |
| 731 | "offset is 0x%llx\n", DRIVER_NAME, off); |
| 732 | return -1; |
| 733 | } |
| 734 | |
| 735 | addr = qla4_8xxx_pci_base_offsetfset(ha, start); |
| 736 | if (!addr) { |
| 737 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 738 | mem_base = pci_resource_start(ha->pdev, 0); |
| 739 | mem_page = start & PAGE_MASK; |
| 740 | /* Map two pages whenever user tries to access addresses in two |
| 741 | consecutive pages. |
| 742 | */ |
| 743 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 744 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); |
| 745 | else |
| 746 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
| 747 | |
| 748 | if (mem_ptr == NULL) { |
| 749 | *(u8 *)data = 0; |
| 750 | return -1; |
| 751 | } |
| 752 | addr = mem_ptr; |
| 753 | addr += start & (PAGE_SIZE - 1); |
| 754 | write_lock_irqsave(&ha->hw_lock, flags); |
| 755 | } |
| 756 | |
| 757 | switch (size) { |
| 758 | case 1: |
| 759 | *(u8 *)data = readb(addr); |
| 760 | break; |
| 761 | case 2: |
| 762 | *(u16 *)data = readw(addr); |
| 763 | break; |
| 764 | case 4: |
| 765 | *(u32 *)data = readl(addr); |
| 766 | break; |
| 767 | case 8: |
| 768 | *(u64 *)data = readq(addr); |
| 769 | break; |
| 770 | default: |
| 771 | ret = -1; |
| 772 | break; |
| 773 | } |
| 774 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 775 | |
| 776 | if (mem_ptr) |
| 777 | iounmap(mem_ptr); |
| 778 | return ret; |
| 779 | } |
| 780 | |
| 781 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 782 | qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 783 | void *data, int size) |
| 784 | { |
| 785 | unsigned long flags; |
| 786 | void __iomem *addr; |
| 787 | int ret = 0; |
| 788 | u64 start; |
| 789 | void __iomem *mem_ptr = NULL; |
| 790 | unsigned long mem_base; |
| 791 | unsigned long mem_page; |
| 792 | |
| 793 | write_lock_irqsave(&ha->hw_lock, flags); |
| 794 | |
| 795 | /* |
| 796 | * If attempting to access unknown address or straddle hw windows, |
| 797 | * do not access. |
| 798 | */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 799 | start = qla4_82xx_pci_set_window(ha, off); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 800 | if ((start == -1UL) || |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 801 | (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 802 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 803 | printk(KERN_ERR"%s out of bound pci memory access. " |
| 804 | "offset is 0x%llx\n", DRIVER_NAME, off); |
| 805 | return -1; |
| 806 | } |
| 807 | |
| 808 | addr = qla4_8xxx_pci_base_offsetfset(ha, start); |
| 809 | if (!addr) { |
| 810 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 811 | mem_base = pci_resource_start(ha->pdev, 0); |
| 812 | mem_page = start & PAGE_MASK; |
| 813 | /* Map two pages whenever user tries to access addresses in two |
| 814 | consecutive pages. |
| 815 | */ |
| 816 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 817 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); |
| 818 | else |
| 819 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
| 820 | if (mem_ptr == NULL) |
| 821 | return -1; |
| 822 | |
| 823 | addr = mem_ptr; |
| 824 | addr += start & (PAGE_SIZE - 1); |
| 825 | write_lock_irqsave(&ha->hw_lock, flags); |
| 826 | } |
| 827 | |
| 828 | switch (size) { |
| 829 | case 1: |
| 830 | writeb(*(u8 *)data, addr); |
| 831 | break; |
| 832 | case 2: |
| 833 | writew(*(u16 *)data, addr); |
| 834 | break; |
| 835 | case 4: |
| 836 | writel(*(u32 *)data, addr); |
| 837 | break; |
| 838 | case 8: |
| 839 | writeq(*(u64 *)data, addr); |
| 840 | break; |
| 841 | default: |
| 842 | ret = -1; |
| 843 | break; |
| 844 | } |
| 845 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 846 | if (mem_ptr) |
| 847 | iounmap(mem_ptr); |
| 848 | return ret; |
| 849 | } |
| 850 | |
| 851 | #define MTU_FUDGE_FACTOR 100 |
| 852 | |
| 853 | static unsigned long |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 854 | qla4_82xx_decode_crb_addr(unsigned long addr) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 855 | { |
| 856 | int i; |
| 857 | unsigned long base_addr, offset, pci_base; |
| 858 | |
| 859 | if (!qla4_8xxx_crb_table_initialized) |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 860 | qla4_82xx_crb_addr_transform_setup(); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 861 | |
| 862 | pci_base = ADDR_ERROR; |
| 863 | base_addr = addr & 0xfff00000; |
| 864 | offset = addr & 0x000fffff; |
| 865 | |
| 866 | for (i = 0; i < MAX_CRB_XFORM; i++) { |
| 867 | if (crb_addr_xform[i] == base_addr) { |
| 868 | pci_base = i << 20; |
| 869 | break; |
| 870 | } |
| 871 | } |
| 872 | if (pci_base == ADDR_ERROR) |
| 873 | return pci_base; |
| 874 | else |
| 875 | return pci_base + offset; |
| 876 | } |
| 877 | |
| 878 | static long rom_max_timeout = 100; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 879 | static long qla4_82xx_rom_lock_timeout = 100; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 880 | |
| 881 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 882 | qla4_82xx_rom_lock(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 883 | { |
| 884 | int i; |
| 885 | int done = 0, timeout = 0; |
| 886 | |
| 887 | while (!done) { |
| 888 | /* acquire semaphore2 from PCI HW block */ |
| 889 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 890 | done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 891 | if (done == 1) |
| 892 | break; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 893 | if (timeout >= qla4_82xx_rom_lock_timeout) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 894 | return -1; |
| 895 | |
| 896 | timeout++; |
| 897 | |
| 898 | /* Yield CPU */ |
| 899 | if (!in_interrupt()) |
| 900 | schedule(); |
| 901 | else { |
| 902 | for (i = 0; i < 20; i++) |
| 903 | cpu_relax(); /*This a nop instr on i386*/ |
| 904 | } |
| 905 | } |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 906 | qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 907 | return 0; |
| 908 | } |
| 909 | |
| 910 | static void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 911 | qla4_82xx_rom_unlock(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 912 | { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 913 | qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 917 | qla4_82xx_wait_rom_done(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 918 | { |
| 919 | long timeout = 0; |
| 920 | long done = 0 ; |
| 921 | |
| 922 | while (done == 0) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 923 | done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 924 | done &= 2; |
| 925 | timeout++; |
| 926 | if (timeout >= rom_max_timeout) { |
| 927 | printk("%s: Timeout reached waiting for rom done", |
| 928 | DRIVER_NAME); |
| 929 | return -1; |
| 930 | } |
| 931 | } |
| 932 | return 0; |
| 933 | } |
| 934 | |
| 935 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 936 | qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 937 | { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 938 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); |
| 939 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
| 940 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); |
| 941 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); |
| 942 | if (qla4_82xx_wait_rom_done(ha)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 943 | printk("%s: Error waiting for rom done\n", DRIVER_NAME); |
| 944 | return -1; |
| 945 | } |
| 946 | /* reset abyte_cnt and dummy_byte_cnt */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 947 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 948 | udelay(10); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 949 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 950 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 951 | *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 952 | return 0; |
| 953 | } |
| 954 | |
| 955 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 956 | qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 957 | { |
| 958 | int ret, loops = 0; |
| 959 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 960 | while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 961 | udelay(100); |
| 962 | loops++; |
| 963 | } |
| 964 | if (loops >= 50000) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 965 | ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n", |
| 966 | DRIVER_NAME); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 967 | return -1; |
| 968 | } |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 969 | ret = qla4_82xx_do_rom_fast_read(ha, addr, valp); |
| 970 | qla4_82xx_rom_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 971 | return ret; |
| 972 | } |
| 973 | |
| 974 | /** |
| 975 | * This routine does CRB initialize sequence |
| 976 | * to put the ISP into operational state |
| 977 | **/ |
| 978 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 979 | qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 980 | { |
| 981 | int addr, val; |
| 982 | int i ; |
| 983 | struct crb_addr_pair *buf; |
| 984 | unsigned long off; |
| 985 | unsigned offset, n; |
| 986 | |
| 987 | struct crb_addr_pair { |
| 988 | long addr; |
| 989 | long data; |
| 990 | }; |
| 991 | |
| 992 | /* Halt all the indiviual PEGs and other blocks of the ISP */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 993 | qla4_82xx_rom_lock(ha); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 994 | |
Vikas Chaudhary | cb74428 | 2011-05-17 23:17:04 -0700 | [diff] [blame] | 995 | /* disable all I2Q */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 996 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); |
| 997 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); |
| 998 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); |
| 999 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); |
| 1000 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); |
| 1001 | qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); |
Vikas Chaudhary | cb74428 | 2011-05-17 23:17:04 -0700 | [diff] [blame] | 1002 | |
| 1003 | /* disable all niu interrupts */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1004 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 1005 | /* disable xge rx/tx */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1006 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 1007 | /* disable xg1 rx/tx */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1008 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); |
Vikas Chaudhary | cb74428 | 2011-05-17 23:17:04 -0700 | [diff] [blame] | 1009 | /* disable sideband mac */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1010 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); |
Vikas Chaudhary | cb74428 | 2011-05-17 23:17:04 -0700 | [diff] [blame] | 1011 | /* disable ap0 mac */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1012 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); |
Vikas Chaudhary | cb74428 | 2011-05-17 23:17:04 -0700 | [diff] [blame] | 1013 | /* disable ap1 mac */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1014 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 1015 | |
| 1016 | /* halt sre */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1017 | val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); |
| 1018 | qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 1019 | |
| 1020 | /* halt epg */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1021 | qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 1022 | |
| 1023 | /* halt timers */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1024 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); |
| 1025 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); |
| 1026 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); |
| 1027 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); |
| 1028 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); |
| 1029 | qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 1030 | |
| 1031 | /* halt pegs */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1032 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); |
| 1033 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); |
| 1034 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); |
| 1035 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); |
| 1036 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); |
Vikas Chaudhary | cb74428 | 2011-05-17 23:17:04 -0700 | [diff] [blame] | 1037 | msleep(5); |
Swapnil Nagle | a1fc26b | 2010-12-02 22:12:15 -0800 | [diff] [blame] | 1038 | |
| 1039 | /* big hammer */ |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1040 | if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) |
| 1041 | /* don't reset CAM block on reset */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1042 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1043 | else |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1044 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1045 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1046 | qla4_82xx_rom_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1047 | |
| 1048 | /* Read the signature value from the flash. |
| 1049 | * Offset 0: Contain signature (0xcafecafe) |
| 1050 | * Offset 4: Offset and number of addr/value pairs |
| 1051 | * that present in CRB initialize sequence |
| 1052 | */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1053 | if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || |
| 1054 | qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1055 | ql4_printk(KERN_WARNING, ha, |
| 1056 | "[ERROR] Reading crb_init area: n: %08x\n", n); |
| 1057 | return -1; |
| 1058 | } |
| 1059 | |
| 1060 | /* Offset in flash = lower 16 bits |
| 1061 | * Number of enteries = upper 16 bits |
| 1062 | */ |
| 1063 | offset = n & 0xffffU; |
| 1064 | n = (n >> 16) & 0xffffU; |
| 1065 | |
| 1066 | /* number of addr/value pair should not exceed 1024 enteries */ |
| 1067 | if (n >= 1024) { |
| 1068 | ql4_printk(KERN_WARNING, ha, |
| 1069 | "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", |
| 1070 | DRIVER_NAME, __func__, n); |
| 1071 | return -1; |
| 1072 | } |
| 1073 | |
| 1074 | ql4_printk(KERN_INFO, ha, |
| 1075 | "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); |
| 1076 | |
| 1077 | buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); |
| 1078 | if (buf == NULL) { |
| 1079 | ql4_printk(KERN_WARNING, ha, |
| 1080 | "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); |
| 1081 | return -1; |
| 1082 | } |
| 1083 | |
| 1084 | for (i = 0; i < n; i++) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1085 | if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || |
| 1086 | qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1087 | 0) { |
| 1088 | kfree(buf); |
| 1089 | return -1; |
| 1090 | } |
| 1091 | |
| 1092 | buf[i].addr = addr; |
| 1093 | buf[i].data = val; |
| 1094 | } |
| 1095 | |
| 1096 | for (i = 0; i < n; i++) { |
| 1097 | /* Translate internal CRB initialization |
| 1098 | * address to PCI bus address |
| 1099 | */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1100 | off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) + |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1101 | QLA82XX_PCI_CRBSPACE; |
| 1102 | /* Not all CRB addr/value pair to be written, |
| 1103 | * some of them are skipped |
| 1104 | */ |
| 1105 | |
| 1106 | /* skip if LS bit is set*/ |
| 1107 | if (off & 0x1) { |
| 1108 | DEBUG2(ql4_printk(KERN_WARNING, ha, |
| 1109 | "Skip CRB init replay for offset = 0x%lx\n", off)); |
| 1110 | continue; |
| 1111 | } |
| 1112 | |
| 1113 | /* skipping cold reboot MAGIC */ |
| 1114 | if (off == QLA82XX_CAM_RAM(0x1fc)) |
| 1115 | continue; |
| 1116 | |
| 1117 | /* do not reset PCI */ |
| 1118 | if (off == (ROMUSB_GLB + 0xbc)) |
| 1119 | continue; |
| 1120 | |
| 1121 | /* skip core clock, so that firmware can increase the clock */ |
| 1122 | if (off == (ROMUSB_GLB + 0xc8)) |
| 1123 | continue; |
| 1124 | |
| 1125 | /* skip the function enable register */ |
| 1126 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) |
| 1127 | continue; |
| 1128 | |
| 1129 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) |
| 1130 | continue; |
| 1131 | |
| 1132 | if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) |
| 1133 | continue; |
| 1134 | |
| 1135 | if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) |
| 1136 | continue; |
| 1137 | |
| 1138 | if (off == ADDR_ERROR) { |
| 1139 | ql4_printk(KERN_WARNING, ha, |
| 1140 | "%s: [ERROR] Unknown addr: 0x%08lx\n", |
| 1141 | DRIVER_NAME, buf[i].addr); |
| 1142 | continue; |
| 1143 | } |
| 1144 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1145 | qla4_82xx_wr_32(ha, off, buf[i].data); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1146 | |
| 1147 | /* ISP requires much bigger delay to settle down, |
| 1148 | * else crb_window returns 0xffffffff |
| 1149 | */ |
| 1150 | if (off == QLA82XX_ROMUSB_GLB_SW_RESET) |
| 1151 | msleep(1000); |
| 1152 | |
| 1153 | /* ISP requires millisec delay between |
| 1154 | * successive CRB register updation |
| 1155 | */ |
| 1156 | msleep(1); |
| 1157 | } |
| 1158 | |
| 1159 | kfree(buf); |
| 1160 | |
| 1161 | /* Resetting the data and instruction cache */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1162 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); |
| 1163 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); |
| 1164 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1165 | |
| 1166 | /* Clear all protocol processing engines */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1167 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); |
| 1168 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); |
| 1169 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); |
| 1170 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); |
| 1171 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); |
| 1172 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); |
| 1173 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); |
| 1174 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1175 | |
| 1176 | return 0; |
| 1177 | } |
| 1178 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1179 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1180 | qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1181 | { |
Lalit Chandivade | 4cd83cb | 2010-12-02 22:12:40 -0800 | [diff] [blame] | 1182 | int i, rval = 0; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1183 | long size = 0; |
| 1184 | long flashaddr, memaddr; |
| 1185 | u64 data; |
| 1186 | u32 high, low; |
| 1187 | |
| 1188 | flashaddr = memaddr = ha->hw.flt_region_bootload; |
Lalit Chandivade | 4cd83cb | 2010-12-02 22:12:40 -0800 | [diff] [blame] | 1189 | size = (image_start - flashaddr) / 8; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1190 | |
| 1191 | DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", |
| 1192 | ha->host_no, __func__, flashaddr, image_start)); |
| 1193 | |
| 1194 | for (i = 0; i < size; i++) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1195 | if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || |
| 1196 | (qla4_82xx_rom_fast_read(ha, flashaddr + 4, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1197 | (int *)&high))) { |
Lalit Chandivade | 4cd83cb | 2010-12-02 22:12:40 -0800 | [diff] [blame] | 1198 | rval = -1; |
| 1199 | goto exit_load_from_flash; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1200 | } |
| 1201 | data = ((u64)high << 32) | low ; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1202 | rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8); |
Lalit Chandivade | 4cd83cb | 2010-12-02 22:12:40 -0800 | [diff] [blame] | 1203 | if (rval) |
| 1204 | goto exit_load_from_flash; |
| 1205 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1206 | flashaddr += 8; |
| 1207 | memaddr += 8; |
| 1208 | |
Lalit Chandivade | 4cd83cb | 2010-12-02 22:12:40 -0800 | [diff] [blame] | 1209 | if (i % 0x1000 == 0) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1210 | msleep(1); |
| 1211 | |
| 1212 | } |
| 1213 | |
| 1214 | udelay(100); |
| 1215 | |
| 1216 | read_lock(&ha->hw_lock); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1217 | qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); |
| 1218 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1219 | read_unlock(&ha->hw_lock); |
| 1220 | |
Lalit Chandivade | 4cd83cb | 2010-12-02 22:12:40 -0800 | [diff] [blame] | 1221 | exit_load_from_flash: |
| 1222 | return rval; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1223 | } |
| 1224 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1225 | static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1226 | { |
| 1227 | u32 rst; |
| 1228 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1229 | qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); |
| 1230 | if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1231 | printk(KERN_WARNING "%s: Error during CRB Initialization\n", |
| 1232 | __func__); |
| 1233 | return QLA_ERROR; |
| 1234 | } |
| 1235 | |
| 1236 | udelay(500); |
| 1237 | |
| 1238 | /* at this point, QM is in reset. This could be a problem if there are |
| 1239 | * incoming d* transition queue messages. QM/PCIE could wedge. |
| 1240 | * To get around this, QM is brought out of reset. |
| 1241 | */ |
| 1242 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1243 | rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1244 | /* unreset qm */ |
| 1245 | rst &= ~(1 << 28); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1246 | qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1247 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1248 | if (qla4_82xx_load_from_flash(ha, image_start)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1249 | printk("%s: Error trying to load fw from flash!\n", __func__); |
| 1250 | return QLA_ERROR; |
| 1251 | } |
| 1252 | |
| 1253 | return QLA_SUCCESS; |
| 1254 | } |
| 1255 | |
| 1256 | int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1257 | qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1258 | u64 off, void *data, int size) |
| 1259 | { |
| 1260 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1261 | int shift_amount; |
| 1262 | uint32_t temp; |
| 1263 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; |
| 1264 | |
| 1265 | /* |
| 1266 | * If not MN, go check for MS or invalid. |
| 1267 | */ |
| 1268 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1269 | if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1270 | mem_crb = QLA82XX_CRB_QDR_NET; |
| 1271 | else { |
| 1272 | mem_crb = QLA82XX_CRB_DDR_NET; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1273 | if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) |
| 1274 | return qla4_82xx_pci_mem_read_direct(ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1275 | off, data, size); |
| 1276 | } |
| 1277 | |
| 1278 | |
| 1279 | off8 = off & 0xfffffff0; |
| 1280 | off0[0] = off & 0xf; |
| 1281 | sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); |
| 1282 | shift_amount = 4; |
| 1283 | |
| 1284 | loop = ((off0[0] + size - 1) >> shift_amount) + 1; |
| 1285 | off0[1] = 0; |
| 1286 | sz[1] = size - sz[0]; |
| 1287 | |
| 1288 | for (i = 0; i < loop; i++) { |
| 1289 | temp = off8 + (i << shift_amount); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1290 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1291 | temp = 0; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1292 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1293 | temp = MIU_TA_CTL_ENABLE; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1294 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); |
Vikas Chaudhary | c38fa3a | 2012-08-22 07:55:03 -0400 | [diff] [blame] | 1295 | temp = MIU_TA_CTL_START_ENABLE; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1296 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1297 | |
| 1298 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1299 | temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1300 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1301 | break; |
| 1302 | } |
| 1303 | |
| 1304 | if (j >= MAX_CTL_CHECK) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1305 | printk_ratelimited(KERN_ERR |
| 1306 | "%s: failed to read through agent\n", |
| 1307 | __func__); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1308 | break; |
| 1309 | } |
| 1310 | |
| 1311 | start = off0[i] >> 2; |
| 1312 | end = (off0[i] + sz[i] - 1) >> 2; |
| 1313 | for (k = start; k <= end; k++) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1314 | temp = qla4_82xx_rd_32(ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1315 | mem_crb + MIU_TEST_AGT_RDDATA(k)); |
| 1316 | word[i] |= ((uint64_t)temp << (32 * (k & 1))); |
| 1317 | } |
| 1318 | } |
| 1319 | |
| 1320 | if (j >= MAX_CTL_CHECK) |
| 1321 | return -1; |
| 1322 | |
| 1323 | if ((off0[0] & 7) == 0) { |
| 1324 | val = word[0]; |
| 1325 | } else { |
| 1326 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | |
| 1327 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); |
| 1328 | } |
| 1329 | |
| 1330 | switch (size) { |
| 1331 | case 1: |
| 1332 | *(uint8_t *)data = val; |
| 1333 | break; |
| 1334 | case 2: |
| 1335 | *(uint16_t *)data = val; |
| 1336 | break; |
| 1337 | case 4: |
| 1338 | *(uint32_t *)data = val; |
| 1339 | break; |
| 1340 | case 8: |
| 1341 | *(uint64_t *)data = val; |
| 1342 | break; |
| 1343 | } |
| 1344 | return 0; |
| 1345 | } |
| 1346 | |
| 1347 | int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1348 | qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1349 | u64 off, void *data, int size) |
| 1350 | { |
| 1351 | int i, j, ret = 0, loop, sz[2], off0; |
| 1352 | int scale, shift_amount, startword; |
| 1353 | uint32_t temp; |
| 1354 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; |
| 1355 | |
| 1356 | /* |
| 1357 | * If not MN, go check for MS or invalid. |
| 1358 | */ |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1359 | if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1360 | mem_crb = QLA82XX_CRB_QDR_NET; |
| 1361 | else { |
| 1362 | mem_crb = QLA82XX_CRB_DDR_NET; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1363 | if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) |
| 1364 | return qla4_82xx_pci_mem_write_direct(ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1365 | off, data, size); |
| 1366 | } |
| 1367 | |
| 1368 | off0 = off & 0x7; |
| 1369 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1370 | sz[1] = size - sz[0]; |
| 1371 | |
| 1372 | off8 = off & 0xfffffff0; |
| 1373 | loop = (((off & 0xf) + size - 1) >> 4) + 1; |
| 1374 | shift_amount = 4; |
| 1375 | scale = 2; |
| 1376 | startword = (off & 0xf)/8; |
| 1377 | |
| 1378 | for (i = 0; i < loop; i++) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1379 | if (qla4_82xx_pci_mem_read_2M(ha, off8 + |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1380 | (i << shift_amount), &word[i * scale], 8)) |
| 1381 | return -1; |
| 1382 | } |
| 1383 | |
| 1384 | switch (size) { |
| 1385 | case 1: |
| 1386 | tmpw = *((uint8_t *)data); |
| 1387 | break; |
| 1388 | case 2: |
| 1389 | tmpw = *((uint16_t *)data); |
| 1390 | break; |
| 1391 | case 4: |
| 1392 | tmpw = *((uint32_t *)data); |
| 1393 | break; |
| 1394 | case 8: |
| 1395 | default: |
| 1396 | tmpw = *((uint64_t *)data); |
| 1397 | break; |
| 1398 | } |
| 1399 | |
| 1400 | if (sz[0] == 8) |
| 1401 | word[startword] = tmpw; |
| 1402 | else { |
| 1403 | word[startword] &= |
| 1404 | ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); |
| 1405 | word[startword] |= tmpw << (off0 * 8); |
| 1406 | } |
| 1407 | |
| 1408 | if (sz[1] != 0) { |
| 1409 | word[startword+1] &= ~(~0ULL << (sz[1] * 8)); |
| 1410 | word[startword+1] |= tmpw >> (sz[0] * 8); |
| 1411 | } |
| 1412 | |
| 1413 | for (i = 0; i < loop; i++) { |
| 1414 | temp = off8 + (i << shift_amount); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1415 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1416 | temp = 0; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1417 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1418 | temp = word[i * scale] & 0xffffffff; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1419 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1420 | temp = (word[i * scale] >> 32) & 0xffffffff; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1421 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1422 | temp = word[i*scale + 1] & 0xffffffff; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1423 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1424 | temp); |
| 1425 | temp = (word[i*scale + 1] >> 32) & 0xffffffff; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1426 | qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1427 | temp); |
| 1428 | |
Vikas Chaudhary | c38fa3a | 2012-08-22 07:55:03 -0400 | [diff] [blame] | 1429 | temp = MIU_TA_CTL_WRITE_ENABLE; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1430 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); |
Vikas Chaudhary | c38fa3a | 2012-08-22 07:55:03 -0400 | [diff] [blame] | 1431 | temp = MIU_TA_CTL_WRITE_START; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1432 | qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1433 | |
| 1434 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1435 | temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1436 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1437 | break; |
| 1438 | } |
| 1439 | |
| 1440 | if (j >= MAX_CTL_CHECK) { |
| 1441 | if (printk_ratelimit()) |
| 1442 | ql4_printk(KERN_ERR, ha, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1443 | "%s: failed to read through agent\n", |
| 1444 | __func__); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1445 | ret = -1; |
| 1446 | break; |
| 1447 | } |
| 1448 | } |
| 1449 | |
| 1450 | return ret; |
| 1451 | } |
| 1452 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1453 | static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1454 | { |
| 1455 | u32 val = 0; |
| 1456 | int retries = 60; |
| 1457 | |
| 1458 | if (!pegtune_val) { |
| 1459 | do { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1460 | val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1461 | if ((val == PHAN_INITIALIZE_COMPLETE) || |
| 1462 | (val == PHAN_INITIALIZE_ACK)) |
| 1463 | return 0; |
| 1464 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 1465 | schedule_timeout(500); |
| 1466 | |
| 1467 | } while (--retries); |
| 1468 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1469 | if (!retries) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1470 | pegtune_val = qla4_82xx_rd_32(ha, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1471 | QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); |
| 1472 | printk(KERN_WARNING "%s: init failed, " |
| 1473 | "pegtune_val = %x\n", __func__, pegtune_val); |
| 1474 | return -1; |
| 1475 | } |
| 1476 | } |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1480 | static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1481 | { |
| 1482 | uint32_t state = 0; |
| 1483 | int loops = 0; |
| 1484 | |
| 1485 | /* Window 1 call */ |
| 1486 | read_lock(&ha->hw_lock); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1487 | state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1488 | read_unlock(&ha->hw_lock); |
| 1489 | |
| 1490 | while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { |
| 1491 | udelay(100); |
| 1492 | /* Window 1 call */ |
| 1493 | read_lock(&ha->hw_lock); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1494 | state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1495 | read_unlock(&ha->hw_lock); |
| 1496 | |
| 1497 | loops++; |
| 1498 | } |
| 1499 | |
| 1500 | if (loops >= 30000) { |
| 1501 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 1502 | "Receive Peg initialization not complete: 0x%x.\n", state)); |
| 1503 | return QLA_ERROR; |
| 1504 | } |
| 1505 | |
| 1506 | return QLA_SUCCESS; |
| 1507 | } |
| 1508 | |
Andrew Morton | 626115c | 2010-08-19 14:13:42 -0700 | [diff] [blame] | 1509 | void |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1510 | qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) |
| 1511 | { |
| 1512 | uint32_t drv_active; |
| 1513 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1514 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1515 | |
| 1516 | /* |
| 1517 | * For ISP8324, drv_active register has 1 bit per function, |
| 1518 | * shift 1 by func_num to set a bit for the function. |
| 1519 | * For ISP8022, drv_active has 4 bits per function |
| 1520 | */ |
| 1521 | if (is_qla8032(ha)) |
| 1522 | drv_active |= (1 << ha->func_num); |
| 1523 | else |
| 1524 | drv_active |= (1 << (ha->func_num * 4)); |
| 1525 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1526 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", |
| 1527 | __func__, ha->host_no, drv_active); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1528 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1529 | } |
| 1530 | |
| 1531 | void |
| 1532 | qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) |
| 1533 | { |
| 1534 | uint32_t drv_active; |
| 1535 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1536 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1537 | |
| 1538 | /* |
| 1539 | * For ISP8324, drv_active register has 1 bit per function, |
| 1540 | * shift 1 by func_num to set a bit for the function. |
| 1541 | * For ISP8022, drv_active has 4 bits per function |
| 1542 | */ |
| 1543 | if (is_qla8032(ha)) |
| 1544 | drv_active &= ~(1 << (ha->func_num)); |
| 1545 | else |
| 1546 | drv_active &= ~(1 << (ha->func_num * 4)); |
| 1547 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1548 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", |
| 1549 | __func__, ha->host_no, drv_active); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1550 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1551 | } |
| 1552 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1553 | inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1554 | { |
Lalit Chandivade | 2232be0 | 2010-07-30 14:38:47 +0530 | [diff] [blame] | 1555 | uint32_t drv_state, drv_active; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1556 | int rval; |
| 1557 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1558 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
| 1559 | drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1560 | |
| 1561 | /* |
| 1562 | * For ISP8324, drv_active register has 1 bit per function, |
| 1563 | * shift 1 by func_num to set a bit for the function. |
| 1564 | * For ISP8022, drv_active has 4 bits per function |
| 1565 | */ |
| 1566 | if (is_qla8032(ha)) |
| 1567 | rval = drv_state & (1 << ha->func_num); |
| 1568 | else |
| 1569 | rval = drv_state & (1 << (ha->func_num * 4)); |
| 1570 | |
Lalit Chandivade | 2232be0 | 2010-07-30 14:38:47 +0530 | [diff] [blame] | 1571 | if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) |
| 1572 | rval = 1; |
| 1573 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1574 | return rval; |
| 1575 | } |
| 1576 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1577 | void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1578 | { |
| 1579 | uint32_t drv_state; |
| 1580 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1581 | drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1582 | |
| 1583 | /* |
| 1584 | * For ISP8324, drv_active register has 1 bit per function, |
| 1585 | * shift 1 by func_num to set a bit for the function. |
| 1586 | * For ISP8022, drv_active has 4 bits per function |
| 1587 | */ |
| 1588 | if (is_qla8032(ha)) |
| 1589 | drv_state |= (1 << ha->func_num); |
| 1590 | else |
| 1591 | drv_state |= (1 << (ha->func_num * 4)); |
| 1592 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1593 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", |
| 1594 | __func__, ha->host_no, drv_state); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1595 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1596 | } |
| 1597 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1598 | void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1599 | { |
| 1600 | uint32_t drv_state; |
| 1601 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1602 | drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1603 | |
| 1604 | /* |
| 1605 | * For ISP8324, drv_active register has 1 bit per function, |
| 1606 | * shift 1 by func_num to set a bit for the function. |
| 1607 | * For ISP8022, drv_active has 4 bits per function |
| 1608 | */ |
| 1609 | if (is_qla8032(ha)) |
| 1610 | drv_state &= ~(1 << ha->func_num); |
| 1611 | else |
| 1612 | drv_state &= ~(1 << (ha->func_num * 4)); |
| 1613 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1614 | ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", |
| 1615 | __func__, ha->host_no, drv_state); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1616 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1617 | } |
| 1618 | |
| 1619 | static inline void |
| 1620 | qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) |
| 1621 | { |
| 1622 | uint32_t qsnt_state; |
| 1623 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1624 | qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 1625 | |
| 1626 | /* |
| 1627 | * For ISP8324, drv_active register has 1 bit per function, |
| 1628 | * shift 1 by func_num to set a bit for the function. |
| 1629 | * For ISP8022, drv_active has 4 bits per function. |
| 1630 | */ |
| 1631 | if (is_qla8032(ha)) |
| 1632 | qsnt_state |= (1 << ha->func_num); |
| 1633 | else |
| 1634 | qsnt_state |= (2 << (ha->func_num * 4)); |
| 1635 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1636 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1637 | } |
| 1638 | |
| 1639 | |
| 1640 | static int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1641 | qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1642 | { |
| 1643 | int pcie_cap; |
| 1644 | uint16_t lnk; |
| 1645 | |
| 1646 | /* scrub dma mask expansion register */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1647 | qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1648 | |
| 1649 | /* Overwrite stale initialization register values */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1650 | qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); |
| 1651 | qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); |
| 1652 | qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); |
| 1653 | qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1654 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1655 | if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1656 | printk("%s: Error trying to start fw!\n", __func__); |
| 1657 | return QLA_ERROR; |
| 1658 | } |
| 1659 | |
| 1660 | /* Handshake with the card before we register the devices. */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1661 | if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1662 | printk("%s: Error during card handshake!\n", __func__); |
| 1663 | return QLA_ERROR; |
| 1664 | } |
| 1665 | |
| 1666 | /* Negotiated Link width */ |
Jon Mason | 983bfb5 | 2012-07-10 14:57:55 -0700 | [diff] [blame] | 1667 | pcie_cap = pci_pcie_cap(ha->pdev); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1668 | pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); |
| 1669 | ha->link_width = (lnk >> 4) & 0x3f; |
| 1670 | |
| 1671 | /* Synchronize with Receive peg */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1672 | return qla4_82xx_rcvpeg_ready(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1673 | } |
| 1674 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1675 | int qla4_82xx_try_start_fw(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1676 | { |
| 1677 | int rval = QLA_ERROR; |
| 1678 | |
| 1679 | /* |
| 1680 | * FW Load priority: |
| 1681 | * 1) Operational firmware residing in flash. |
| 1682 | * 2) Fail |
| 1683 | */ |
| 1684 | |
| 1685 | ql4_printk(KERN_INFO, ha, |
| 1686 | "FW: Retrieving flash offsets from FLT/FDT ...\n"); |
| 1687 | rval = qla4_8xxx_get_flash_info(ha); |
| 1688 | if (rval != QLA_SUCCESS) |
| 1689 | return rval; |
| 1690 | |
| 1691 | ql4_printk(KERN_INFO, ha, |
| 1692 | "FW: Attempting to load firmware from flash...\n"); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1693 | rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1694 | |
Vikas Chaudhary | f581a3f | 2010-10-06 22:47:48 -0700 | [diff] [blame] | 1695 | if (rval != QLA_SUCCESS) { |
| 1696 | ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" |
| 1697 | " FAILED...\n"); |
| 1698 | return rval; |
| 1699 | } |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 1700 | |
| 1701 | return rval; |
| 1702 | } |
| 1703 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1704 | void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 1705 | { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1706 | if (qla4_82xx_rom_lock(ha)) { |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 1707 | /* Someone else is holding the lock. */ |
| 1708 | dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); |
| 1709 | } |
| 1710 | |
| 1711 | /* |
| 1712 | * Either we got the lock, or someone |
| 1713 | * else died while holding it. |
| 1714 | * In either case, unlock. |
| 1715 | */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 1716 | qla4_82xx_rom_unlock(ha); |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 1717 | } |
| 1718 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1719 | static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1720 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1721 | uint32_t **d_ptr) |
| 1722 | { |
| 1723 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1724 | struct qla8xxx_minidump_entry_crb *crb_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1725 | uint32_t *data_ptr = *d_ptr; |
| 1726 | |
| 1727 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1728 | crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1729 | r_addr = crb_hdr->addr; |
| 1730 | r_stride = crb_hdr->crb_strd.addr_stride; |
| 1731 | loop_cnt = crb_hdr->op_count; |
| 1732 | |
| 1733 | for (i = 0; i < loop_cnt; i++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1734 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1735 | *data_ptr++ = cpu_to_le32(r_addr); |
| 1736 | *data_ptr++ = cpu_to_le32(r_value); |
| 1737 | r_addr += r_stride; |
| 1738 | } |
| 1739 | *d_ptr = data_ptr; |
| 1740 | } |
| 1741 | |
| 1742 | static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1743 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1744 | uint32_t **d_ptr) |
| 1745 | { |
| 1746 | uint32_t addr, r_addr, c_addr, t_r_addr; |
| 1747 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; |
| 1748 | unsigned long p_wait, w_time, p_mask; |
| 1749 | uint32_t c_value_w, c_value_r; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1750 | struct qla8xxx_minidump_entry_cache *cache_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1751 | int rval = QLA_ERROR; |
| 1752 | uint32_t *data_ptr = *d_ptr; |
| 1753 | |
| 1754 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1755 | cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1756 | |
| 1757 | loop_count = cache_hdr->op_count; |
| 1758 | r_addr = cache_hdr->read_addr; |
| 1759 | c_addr = cache_hdr->control_addr; |
| 1760 | c_value_w = cache_hdr->cache_ctrl.write_value; |
| 1761 | |
| 1762 | t_r_addr = cache_hdr->tag_reg_addr; |
| 1763 | t_value = cache_hdr->addr_ctrl.init_tag_value; |
| 1764 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; |
| 1765 | p_wait = cache_hdr->cache_ctrl.poll_wait; |
| 1766 | p_mask = cache_hdr->cache_ctrl.poll_mask; |
| 1767 | |
| 1768 | for (i = 0; i < loop_count; i++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1769 | ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1770 | |
| 1771 | if (c_value_w) |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1772 | ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1773 | |
| 1774 | if (p_mask) { |
| 1775 | w_time = jiffies + p_wait; |
| 1776 | do { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1777 | ha->isp_ops->rd_reg_indirect(ha, c_addr, |
| 1778 | &c_value_r); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1779 | if ((c_value_r & p_mask) == 0) { |
| 1780 | break; |
| 1781 | } else if (time_after_eq(jiffies, w_time)) { |
| 1782 | /* capturing dump failed */ |
| 1783 | return rval; |
| 1784 | } |
| 1785 | } while (1); |
| 1786 | } |
| 1787 | |
| 1788 | addr = r_addr; |
| 1789 | for (k = 0; k < r_cnt; k++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1790 | ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1791 | *data_ptr++ = cpu_to_le32(r_value); |
| 1792 | addr += cache_hdr->read_ctrl.read_addr_stride; |
| 1793 | } |
| 1794 | |
| 1795 | t_value += cache_hdr->addr_ctrl.tag_value_stride; |
| 1796 | } |
| 1797 | *d_ptr = data_ptr; |
| 1798 | return QLA_SUCCESS; |
| 1799 | } |
| 1800 | |
| 1801 | static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1802 | struct qla8xxx_minidump_entry_hdr *entry_hdr) |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1803 | { |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1804 | struct qla8xxx_minidump_entry_crb *crb_entry; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1805 | uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; |
| 1806 | uint32_t crb_addr; |
| 1807 | unsigned long wtime; |
| 1808 | struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; |
| 1809 | int i; |
| 1810 | |
| 1811 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
| 1812 | tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) |
| 1813 | ha->fw_dump_tmplt_hdr; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1814 | crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1815 | |
| 1816 | crb_addr = crb_entry->addr; |
| 1817 | for (i = 0; i < crb_entry->op_count; i++) { |
| 1818 | opcode = crb_entry->crb_ctrl.opcode; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1819 | if (opcode & QLA8XXX_DBG_OPCODE_WR) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1820 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, |
| 1821 | crb_entry->value_1); |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1822 | opcode &= ~QLA8XXX_DBG_OPCODE_WR; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1823 | } |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1824 | if (opcode & QLA8XXX_DBG_OPCODE_RW) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1825 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
| 1826 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1827 | opcode &= ~QLA8XXX_DBG_OPCODE_RW; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1828 | } |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1829 | if (opcode & QLA8XXX_DBG_OPCODE_AND) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1830 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1831 | read_value &= crb_entry->value_2; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1832 | opcode &= ~QLA8XXX_DBG_OPCODE_AND; |
| 1833 | if (opcode & QLA8XXX_DBG_OPCODE_OR) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1834 | read_value |= crb_entry->value_3; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1835 | opcode &= ~QLA8XXX_DBG_OPCODE_OR; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1836 | } |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1837 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1838 | } |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1839 | if (opcode & QLA8XXX_DBG_OPCODE_OR) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1840 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1841 | read_value |= crb_entry->value_3; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1842 | ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1843 | opcode &= ~QLA8XXX_DBG_OPCODE_OR; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1844 | } |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1845 | if (opcode & QLA8XXX_DBG_OPCODE_POLL) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1846 | poll_time = crb_entry->crb_strd.poll_timeout; |
| 1847 | wtime = jiffies + poll_time; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1848 | ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1849 | |
| 1850 | do { |
| 1851 | if ((read_value & crb_entry->value_2) == |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1852 | crb_entry->value_1) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1853 | break; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1854 | } else if (time_after_eq(jiffies, wtime)) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1855 | /* capturing dump failed */ |
| 1856 | rval = QLA_ERROR; |
| 1857 | break; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1858 | } else { |
| 1859 | ha->isp_ops->rd_reg_indirect(ha, |
| 1860 | crb_addr, &read_value); |
| 1861 | } |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1862 | } while (1); |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1863 | opcode &= ~QLA8XXX_DBG_OPCODE_POLL; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1864 | } |
| 1865 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1866 | if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1867 | if (crb_entry->crb_strd.state_index_a) { |
| 1868 | index = crb_entry->crb_strd.state_index_a; |
| 1869 | addr = tmplt_hdr->saved_state_array[index]; |
| 1870 | } else { |
| 1871 | addr = crb_addr; |
| 1872 | } |
| 1873 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1874 | ha->isp_ops->rd_reg_indirect(ha, addr, &read_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1875 | index = crb_entry->crb_ctrl.state_index_v; |
| 1876 | tmplt_hdr->saved_state_array[index] = read_value; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1877 | opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1878 | } |
| 1879 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1880 | if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1881 | if (crb_entry->crb_strd.state_index_a) { |
| 1882 | index = crb_entry->crb_strd.state_index_a; |
| 1883 | addr = tmplt_hdr->saved_state_array[index]; |
| 1884 | } else { |
| 1885 | addr = crb_addr; |
| 1886 | } |
| 1887 | |
| 1888 | if (crb_entry->crb_ctrl.state_index_v) { |
| 1889 | index = crb_entry->crb_ctrl.state_index_v; |
| 1890 | read_value = |
| 1891 | tmplt_hdr->saved_state_array[index]; |
| 1892 | } else { |
| 1893 | read_value = crb_entry->value_1; |
| 1894 | } |
| 1895 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1896 | ha->isp_ops->wr_reg_indirect(ha, addr, read_value); |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1897 | opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1898 | } |
| 1899 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1900 | if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1901 | index = crb_entry->crb_ctrl.state_index_v; |
| 1902 | read_value = tmplt_hdr->saved_state_array[index]; |
| 1903 | read_value <<= crb_entry->crb_ctrl.shl; |
| 1904 | read_value >>= crb_entry->crb_ctrl.shr; |
| 1905 | if (crb_entry->value_2) |
| 1906 | read_value &= crb_entry->value_2; |
| 1907 | read_value |= crb_entry->value_3; |
| 1908 | read_value += crb_entry->value_1; |
| 1909 | tmplt_hdr->saved_state_array[index] = read_value; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 1910 | opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1911 | } |
| 1912 | crb_addr += crb_entry->crb_strd.addr_stride; |
| 1913 | } |
| 1914 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); |
| 1915 | return rval; |
| 1916 | } |
| 1917 | |
| 1918 | static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1919 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1920 | uint32_t **d_ptr) |
| 1921 | { |
| 1922 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1923 | struct qla8xxx_minidump_entry_rdocm *ocm_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1924 | uint32_t *data_ptr = *d_ptr; |
| 1925 | |
| 1926 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1927 | ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1928 | r_addr = ocm_hdr->read_addr; |
| 1929 | r_stride = ocm_hdr->read_addr_stride; |
| 1930 | loop_cnt = ocm_hdr->op_count; |
| 1931 | |
| 1932 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 1933 | "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", |
| 1934 | __func__, r_addr, r_stride, loop_cnt)); |
| 1935 | |
| 1936 | for (i = 0; i < loop_cnt; i++) { |
| 1937 | r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); |
| 1938 | *data_ptr++ = cpu_to_le32(r_value); |
| 1939 | r_addr += r_stride; |
| 1940 | } |
| 1941 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", |
Vikas Chaudhary | 26fdf92 | 2012-08-07 07:57:14 -0400 | [diff] [blame] | 1942 | __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1943 | *d_ptr = data_ptr; |
| 1944 | } |
| 1945 | |
| 1946 | static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1947 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1948 | uint32_t **d_ptr) |
| 1949 | { |
| 1950 | uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1951 | struct qla8xxx_minidump_entry_mux *mux_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1952 | uint32_t *data_ptr = *d_ptr; |
| 1953 | |
| 1954 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1955 | mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1956 | r_addr = mux_hdr->read_addr; |
| 1957 | s_addr = mux_hdr->select_addr; |
| 1958 | s_stride = mux_hdr->select_value_stride; |
| 1959 | s_value = mux_hdr->select_value; |
| 1960 | loop_cnt = mux_hdr->op_count; |
| 1961 | |
| 1962 | for (i = 0; i < loop_cnt; i++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1963 | ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); |
| 1964 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1965 | *data_ptr++ = cpu_to_le32(s_value); |
| 1966 | *data_ptr++ = cpu_to_le32(r_value); |
| 1967 | s_value += s_stride; |
| 1968 | } |
| 1969 | *d_ptr = data_ptr; |
| 1970 | } |
| 1971 | |
| 1972 | static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1973 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1974 | uint32_t **d_ptr) |
| 1975 | { |
| 1976 | uint32_t addr, r_addr, c_addr, t_r_addr; |
| 1977 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; |
| 1978 | uint32_t c_value_w; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1979 | struct qla8xxx_minidump_entry_cache *cache_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1980 | uint32_t *data_ptr = *d_ptr; |
| 1981 | |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 1982 | cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1983 | loop_count = cache_hdr->op_count; |
| 1984 | r_addr = cache_hdr->read_addr; |
| 1985 | c_addr = cache_hdr->control_addr; |
| 1986 | c_value_w = cache_hdr->cache_ctrl.write_value; |
| 1987 | |
| 1988 | t_r_addr = cache_hdr->tag_reg_addr; |
| 1989 | t_value = cache_hdr->addr_ctrl.init_tag_value; |
| 1990 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; |
| 1991 | |
| 1992 | for (i = 0; i < loop_count; i++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1993 | ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); |
| 1994 | ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1995 | addr = r_addr; |
| 1996 | for (k = 0; k < r_cnt; k++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 1997 | ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 1998 | *data_ptr++ = cpu_to_le32(r_value); |
| 1999 | addr += cache_hdr->read_ctrl.read_addr_stride; |
| 2000 | } |
| 2001 | t_value += cache_hdr->addr_ctrl.tag_value_stride; |
| 2002 | } |
| 2003 | *d_ptr = data_ptr; |
| 2004 | } |
| 2005 | |
| 2006 | static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2007 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2008 | uint32_t **d_ptr) |
| 2009 | { |
| 2010 | uint32_t s_addr, r_addr; |
| 2011 | uint32_t r_stride, r_value, r_cnt, qid = 0; |
| 2012 | uint32_t i, k, loop_cnt; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2013 | struct qla8xxx_minidump_entry_queue *q_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2014 | uint32_t *data_ptr = *d_ptr; |
| 2015 | |
| 2016 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2017 | q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2018 | s_addr = q_hdr->select_addr; |
| 2019 | r_cnt = q_hdr->rd_strd.read_addr_cnt; |
| 2020 | r_stride = q_hdr->rd_strd.read_addr_stride; |
| 2021 | loop_cnt = q_hdr->op_count; |
| 2022 | |
| 2023 | for (i = 0; i < loop_cnt; i++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2024 | ha->isp_ops->wr_reg_indirect(ha, s_addr, qid); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2025 | r_addr = q_hdr->read_addr; |
| 2026 | for (k = 0; k < r_cnt; k++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2027 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2028 | *data_ptr++ = cpu_to_le32(r_value); |
| 2029 | r_addr += r_stride; |
| 2030 | } |
| 2031 | qid += q_hdr->q_strd.queue_id_stride; |
| 2032 | } |
| 2033 | *d_ptr = data_ptr; |
| 2034 | } |
| 2035 | |
| 2036 | #define MD_DIRECT_ROM_WINDOW 0x42110030 |
| 2037 | #define MD_DIRECT_ROM_READ_BASE 0x42150000 |
| 2038 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2039 | static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2040 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2041 | uint32_t **d_ptr) |
| 2042 | { |
| 2043 | uint32_t r_addr, r_value; |
| 2044 | uint32_t i, loop_cnt; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2045 | struct qla8xxx_minidump_entry_rdrom *rom_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2046 | uint32_t *data_ptr = *d_ptr; |
| 2047 | |
| 2048 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2049 | rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2050 | r_addr = rom_hdr->read_addr; |
| 2051 | loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); |
| 2052 | |
| 2053 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2054 | "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", |
| 2055 | __func__, r_addr, loop_cnt)); |
| 2056 | |
| 2057 | for (i = 0; i < loop_cnt; i++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2058 | ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW, |
| 2059 | (r_addr & 0xFFFF0000)); |
| 2060 | ha->isp_ops->rd_reg_indirect(ha, |
| 2061 | MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF), |
| 2062 | &r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2063 | *data_ptr++ = cpu_to_le32(r_value); |
| 2064 | r_addr += sizeof(uint32_t); |
| 2065 | } |
| 2066 | *d_ptr = data_ptr; |
| 2067 | } |
| 2068 | |
| 2069 | #define MD_MIU_TEST_AGT_CTRL 0x41000090 |
| 2070 | #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 |
| 2071 | #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 |
| 2072 | |
| 2073 | static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2074 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2075 | uint32_t **d_ptr) |
| 2076 | { |
| 2077 | uint32_t r_addr, r_value, r_data; |
| 2078 | uint32_t i, j, loop_cnt; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2079 | struct qla8xxx_minidump_entry_rdmem *m_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2080 | unsigned long flags; |
| 2081 | uint32_t *data_ptr = *d_ptr; |
| 2082 | |
| 2083 | DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2084 | m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2085 | r_addr = m_hdr->read_addr; |
| 2086 | loop_cnt = m_hdr->read_data_size/16; |
| 2087 | |
| 2088 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2089 | "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", |
| 2090 | __func__, r_addr, m_hdr->read_data_size)); |
| 2091 | |
| 2092 | if (r_addr & 0xf) { |
| 2093 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2094 | "[%s]: Read addr 0x%x not 16 bytes alligned\n", |
| 2095 | __func__, r_addr)); |
| 2096 | return QLA_ERROR; |
| 2097 | } |
| 2098 | |
| 2099 | if (m_hdr->read_data_size % 16) { |
| 2100 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2101 | "[%s]: Read data[0x%x] not multiple of 16 bytes\n", |
| 2102 | __func__, m_hdr->read_data_size)); |
| 2103 | return QLA_ERROR; |
| 2104 | } |
| 2105 | |
| 2106 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2107 | "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", |
| 2108 | __func__, r_addr, m_hdr->read_data_size, loop_cnt)); |
| 2109 | |
| 2110 | write_lock_irqsave(&ha->hw_lock, flags); |
| 2111 | for (i = 0; i < loop_cnt; i++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2112 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, |
| 2113 | r_addr); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2114 | r_value = 0; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2115 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, |
| 2116 | r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2117 | r_value = MIU_TA_CTL_ENABLE; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2118 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); |
Vikas Chaudhary | c38fa3a | 2012-08-22 07:55:03 -0400 | [diff] [blame] | 2119 | r_value = MIU_TA_CTL_START_ENABLE; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2120 | ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2121 | |
| 2122 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2123 | ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, |
| 2124 | &r_value); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2125 | if ((r_value & MIU_TA_CTL_BUSY) == 0) |
| 2126 | break; |
| 2127 | } |
| 2128 | |
| 2129 | if (j >= MAX_CTL_CHECK) { |
| 2130 | printk_ratelimited(KERN_ERR |
| 2131 | "%s: failed to read through agent\n", |
| 2132 | __func__); |
| 2133 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 2134 | return QLA_SUCCESS; |
| 2135 | } |
| 2136 | |
| 2137 | for (j = 0; j < 4; j++) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2138 | ha->isp_ops->rd_reg_indirect(ha, |
| 2139 | MD_MIU_TEST_AGT_RDDATA[j], |
| 2140 | &r_data); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2141 | *data_ptr++ = cpu_to_le32(r_data); |
| 2142 | } |
| 2143 | |
| 2144 | r_addr += 16; |
| 2145 | } |
| 2146 | write_unlock_irqrestore(&ha->hw_lock, flags); |
| 2147 | |
| 2148 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", |
| 2149 | __func__, (loop_cnt * 16))); |
| 2150 | |
| 2151 | *d_ptr = data_ptr; |
| 2152 | return QLA_SUCCESS; |
| 2153 | } |
| 2154 | |
Vikas Chaudhary | 5e9bcec | 2012-08-22 07:55:01 -0400 | [diff] [blame] | 2155 | static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2156 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2157 | int index) |
| 2158 | { |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2159 | entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2160 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2161 | "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", |
| 2162 | ha->host_no, index, entry_hdr->entry_type, |
| 2163 | entry_hdr->d_ctrl.entry_capture_mask)); |
| 2164 | } |
| 2165 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2166 | /* ISP83xx functions to process new minidump entries... */ |
| 2167 | static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha, |
| 2168 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
| 2169 | uint32_t **d_ptr) |
| 2170 | { |
| 2171 | uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; |
| 2172 | uint16_t s_stride, i; |
| 2173 | uint32_t *data_ptr = *d_ptr; |
| 2174 | uint32_t rval = QLA_SUCCESS; |
| 2175 | struct qla83xx_minidump_entry_pollrd *pollrd_hdr; |
| 2176 | |
| 2177 | pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr; |
| 2178 | s_addr = le32_to_cpu(pollrd_hdr->select_addr); |
| 2179 | r_addr = le32_to_cpu(pollrd_hdr->read_addr); |
| 2180 | s_value = le32_to_cpu(pollrd_hdr->select_value); |
| 2181 | s_stride = le32_to_cpu(pollrd_hdr->select_value_stride); |
| 2182 | |
| 2183 | poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); |
| 2184 | poll_mask = le32_to_cpu(pollrd_hdr->poll_mask); |
| 2185 | |
| 2186 | for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) { |
| 2187 | ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); |
| 2188 | poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); |
| 2189 | while (1) { |
| 2190 | ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value); |
| 2191 | |
| 2192 | if ((r_value & poll_mask) != 0) { |
| 2193 | break; |
| 2194 | } else { |
| 2195 | msleep(1); |
| 2196 | if (--poll_wait == 0) { |
| 2197 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", |
| 2198 | __func__); |
| 2199 | rval = QLA_ERROR; |
| 2200 | goto exit_process_pollrd; |
| 2201 | } |
| 2202 | } |
| 2203 | } |
| 2204 | ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); |
| 2205 | *data_ptr++ = cpu_to_le32(s_value); |
| 2206 | *data_ptr++ = cpu_to_le32(r_value); |
| 2207 | s_value += s_stride; |
| 2208 | } |
| 2209 | |
| 2210 | *d_ptr = data_ptr; |
| 2211 | |
| 2212 | exit_process_pollrd: |
| 2213 | return rval; |
| 2214 | } |
| 2215 | |
| 2216 | static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha, |
| 2217 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
| 2218 | uint32_t **d_ptr) |
| 2219 | { |
| 2220 | uint32_t sel_val1, sel_val2, t_sel_val, data, i; |
| 2221 | uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; |
| 2222 | struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr; |
| 2223 | uint32_t *data_ptr = *d_ptr; |
| 2224 | |
| 2225 | rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr; |
| 2226 | sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1); |
| 2227 | sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2); |
| 2228 | sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1); |
| 2229 | sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2); |
| 2230 | sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask); |
| 2231 | read_addr = le32_to_cpu(rdmux2_hdr->read_addr); |
| 2232 | |
| 2233 | for (i = 0; i < rdmux2_hdr->op_count; i++) { |
| 2234 | ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1); |
| 2235 | t_sel_val = sel_val1 & sel_val_mask; |
| 2236 | *data_ptr++ = cpu_to_le32(t_sel_val); |
| 2237 | |
| 2238 | ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); |
| 2239 | ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); |
| 2240 | |
| 2241 | *data_ptr++ = cpu_to_le32(data); |
| 2242 | |
| 2243 | ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2); |
| 2244 | t_sel_val = sel_val2 & sel_val_mask; |
| 2245 | *data_ptr++ = cpu_to_le32(t_sel_val); |
| 2246 | |
| 2247 | ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); |
| 2248 | ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); |
| 2249 | |
| 2250 | *data_ptr++ = cpu_to_le32(data); |
| 2251 | |
| 2252 | sel_val1 += rdmux2_hdr->select_value_stride; |
| 2253 | sel_val2 += rdmux2_hdr->select_value_stride; |
| 2254 | } |
| 2255 | |
| 2256 | *d_ptr = data_ptr; |
| 2257 | } |
| 2258 | |
| 2259 | static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha, |
| 2260 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
| 2261 | uint32_t **d_ptr) |
| 2262 | { |
| 2263 | uint32_t poll_wait, poll_mask, r_value, data; |
| 2264 | uint32_t addr_1, addr_2, value_1, value_2; |
| 2265 | uint32_t *data_ptr = *d_ptr; |
| 2266 | uint32_t rval = QLA_SUCCESS; |
| 2267 | struct qla83xx_minidump_entry_pollrdmwr *poll_hdr; |
| 2268 | |
| 2269 | poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr; |
| 2270 | addr_1 = le32_to_cpu(poll_hdr->addr_1); |
| 2271 | addr_2 = le32_to_cpu(poll_hdr->addr_2); |
| 2272 | value_1 = le32_to_cpu(poll_hdr->value_1); |
| 2273 | value_2 = le32_to_cpu(poll_hdr->value_2); |
| 2274 | poll_mask = le32_to_cpu(poll_hdr->poll_mask); |
| 2275 | |
| 2276 | ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1); |
| 2277 | |
| 2278 | poll_wait = le32_to_cpu(poll_hdr->poll_wait); |
| 2279 | while (1) { |
| 2280 | ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); |
| 2281 | |
| 2282 | if ((r_value & poll_mask) != 0) { |
| 2283 | break; |
| 2284 | } else { |
| 2285 | msleep(1); |
| 2286 | if (--poll_wait == 0) { |
| 2287 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n", |
| 2288 | __func__); |
| 2289 | rval = QLA_ERROR; |
| 2290 | goto exit_process_pollrdmwr; |
| 2291 | } |
| 2292 | } |
| 2293 | } |
| 2294 | |
| 2295 | ha->isp_ops->rd_reg_indirect(ha, addr_2, &data); |
| 2296 | data &= le32_to_cpu(poll_hdr->modify_mask); |
| 2297 | ha->isp_ops->wr_reg_indirect(ha, addr_2, data); |
| 2298 | ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2); |
| 2299 | |
| 2300 | poll_wait = le32_to_cpu(poll_hdr->poll_wait); |
| 2301 | while (1) { |
| 2302 | ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); |
| 2303 | |
| 2304 | if ((r_value & poll_mask) != 0) { |
| 2305 | break; |
| 2306 | } else { |
| 2307 | msleep(1); |
| 2308 | if (--poll_wait == 0) { |
| 2309 | ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n", |
| 2310 | __func__); |
| 2311 | rval = QLA_ERROR; |
| 2312 | goto exit_process_pollrdmwr; |
| 2313 | } |
| 2314 | } |
| 2315 | } |
| 2316 | |
| 2317 | *data_ptr++ = cpu_to_le32(addr_2); |
| 2318 | *data_ptr++ = cpu_to_le32(data); |
| 2319 | *d_ptr = data_ptr; |
| 2320 | |
| 2321 | exit_process_pollrdmwr: |
| 2322 | return rval; |
| 2323 | } |
| 2324 | |
| 2325 | static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha, |
| 2326 | struct qla8xxx_minidump_entry_hdr *entry_hdr, |
| 2327 | uint32_t **d_ptr) |
| 2328 | { |
| 2329 | uint32_t fl_addr, u32_count, rval; |
| 2330 | struct qla8xxx_minidump_entry_rdrom *rom_hdr; |
| 2331 | uint32_t *data_ptr = *d_ptr; |
| 2332 | |
| 2333 | rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; |
| 2334 | fl_addr = le32_to_cpu(rom_hdr->read_addr); |
| 2335 | u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t); |
| 2336 | |
| 2337 | DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n", |
| 2338 | __func__, fl_addr, u32_count)); |
| 2339 | |
| 2340 | rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr, |
| 2341 | (u8 *)(data_ptr), u32_count); |
| 2342 | |
| 2343 | if (rval == QLA_ERROR) { |
| 2344 | ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n", |
| 2345 | __func__, u32_count); |
| 2346 | goto exit_process_rdrom; |
| 2347 | } |
| 2348 | |
| 2349 | data_ptr += u32_count; |
| 2350 | *d_ptr = data_ptr; |
| 2351 | |
| 2352 | exit_process_rdrom: |
| 2353 | return rval; |
| 2354 | } |
| 2355 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2356 | /** |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2357 | * qla4_8xxx_collect_md_data - Retrieve firmware minidump data. |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2358 | * @ha: pointer to adapter structure |
| 2359 | **/ |
| 2360 | static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) |
| 2361 | { |
| 2362 | int num_entry_hdr = 0; |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2363 | struct qla8xxx_minidump_entry_hdr *entry_hdr; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2364 | struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; |
| 2365 | uint32_t *data_ptr; |
| 2366 | uint32_t data_collected = 0; |
| 2367 | int i, rval = QLA_ERROR; |
| 2368 | uint64_t now; |
| 2369 | uint32_t timestamp; |
| 2370 | |
| 2371 | if (!ha->fw_dump) { |
| 2372 | ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", |
| 2373 | __func__, ha->host_no); |
| 2374 | return rval; |
| 2375 | } |
| 2376 | |
| 2377 | tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) |
| 2378 | ha->fw_dump_tmplt_hdr; |
| 2379 | data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + |
| 2380 | ha->fw_dump_tmplt_size); |
| 2381 | data_collected += ha->fw_dump_tmplt_size; |
| 2382 | |
| 2383 | num_entry_hdr = tmplt_hdr->num_of_entries; |
| 2384 | ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", |
| 2385 | __func__, data_ptr); |
| 2386 | ql4_printk(KERN_INFO, ha, |
| 2387 | "[%s]: no of entry headers in Template: 0x%x\n", |
| 2388 | __func__, num_entry_hdr); |
| 2389 | ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", |
| 2390 | __func__, ha->fw_dump_capture_mask); |
| 2391 | ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", |
| 2392 | __func__, ha->fw_dump_size, ha->fw_dump_size); |
| 2393 | |
| 2394 | /* Update current timestamp before taking dump */ |
| 2395 | now = get_jiffies_64(); |
| 2396 | timestamp = (u32)(jiffies_to_msecs(now) / 1000); |
| 2397 | tmplt_hdr->driver_timestamp = timestamp; |
| 2398 | |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2399 | entry_hdr = (struct qla8xxx_minidump_entry_hdr *) |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2400 | (((uint8_t *)ha->fw_dump_tmplt_hdr) + |
| 2401 | tmplt_hdr->first_entry_offset); |
| 2402 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2403 | if (is_qla8032(ha)) |
| 2404 | tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] = |
| 2405 | tmplt_hdr->ocm_window_reg[ha->func_num]; |
| 2406 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2407 | /* Walk through the entry headers - validate/perform required action */ |
| 2408 | for (i = 0; i < num_entry_hdr; i++) { |
| 2409 | if (data_collected >= ha->fw_dump_size) { |
| 2410 | ql4_printk(KERN_INFO, ha, |
| 2411 | "Data collected: [0x%x], Total Dump size: [0x%x]\n", |
| 2412 | data_collected, ha->fw_dump_size); |
| 2413 | return rval; |
| 2414 | } |
| 2415 | |
| 2416 | if (!(entry_hdr->d_ctrl.entry_capture_mask & |
| 2417 | ha->fw_dump_capture_mask)) { |
| 2418 | entry_hdr->d_ctrl.driver_flags |= |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2419 | QLA8XXX_DBG_SKIPPED_FLAG; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2420 | goto skip_nxt_entry; |
| 2421 | } |
| 2422 | |
| 2423 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2424 | "Data collected: [0x%x], Dump size left:[0x%x]\n", |
| 2425 | data_collected, |
| 2426 | (ha->fw_dump_size - data_collected))); |
| 2427 | |
| 2428 | /* Decode the entry type and take required action to capture |
| 2429 | * debug data |
| 2430 | */ |
| 2431 | switch (entry_hdr->entry_type) { |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2432 | case QLA8XXX_RDEND: |
Vikas Chaudhary | 5e9bcec | 2012-08-22 07:55:01 -0400 | [diff] [blame] | 2433 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2434 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2435 | case QLA8XXX_CNTRL: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2436 | rval = qla4_8xxx_minidump_process_control(ha, |
| 2437 | entry_hdr); |
| 2438 | if (rval != QLA_SUCCESS) { |
Vikas Chaudhary | 5e9bcec | 2012-08-22 07:55:01 -0400 | [diff] [blame] | 2439 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2440 | goto md_failed; |
| 2441 | } |
| 2442 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2443 | case QLA8XXX_RDCRB: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2444 | qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, |
| 2445 | &data_ptr); |
| 2446 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2447 | case QLA8XXX_RDMEM: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2448 | rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, |
| 2449 | &data_ptr); |
| 2450 | if (rval != QLA_SUCCESS) { |
Vikas Chaudhary | 5e9bcec | 2012-08-22 07:55:01 -0400 | [diff] [blame] | 2451 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2452 | goto md_failed; |
| 2453 | } |
| 2454 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2455 | case QLA8XXX_BOARD: |
| 2456 | case QLA8XXX_RDROM: |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2457 | if (is_qla8022(ha)) { |
| 2458 | qla4_82xx_minidump_process_rdrom(ha, entry_hdr, |
| 2459 | &data_ptr); |
| 2460 | } else if (is_qla8032(ha)) { |
| 2461 | rval = qla4_83xx_minidump_process_rdrom(ha, |
| 2462 | entry_hdr, |
| 2463 | &data_ptr); |
| 2464 | if (rval != QLA_SUCCESS) |
| 2465 | qla4_8xxx_mark_entry_skipped(ha, |
| 2466 | entry_hdr, |
| 2467 | i); |
| 2468 | } |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2469 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2470 | case QLA8XXX_L2DTG: |
| 2471 | case QLA8XXX_L2ITG: |
| 2472 | case QLA8XXX_L2DAT: |
| 2473 | case QLA8XXX_L2INS: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2474 | rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, |
| 2475 | &data_ptr); |
| 2476 | if (rval != QLA_SUCCESS) { |
Vikas Chaudhary | 5e9bcec | 2012-08-22 07:55:01 -0400 | [diff] [blame] | 2477 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2478 | goto md_failed; |
| 2479 | } |
| 2480 | break; |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2481 | case QLA8XXX_L1DTG: |
| 2482 | case QLA8XXX_L1ITG: |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2483 | case QLA8XXX_L1DAT: |
| 2484 | case QLA8XXX_L1INS: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2485 | qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, |
| 2486 | &data_ptr); |
| 2487 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2488 | case QLA8XXX_RDOCM: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2489 | qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, |
| 2490 | &data_ptr); |
| 2491 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2492 | case QLA8XXX_RDMUX: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2493 | qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, |
| 2494 | &data_ptr); |
| 2495 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2496 | case QLA8XXX_QUEUE: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2497 | qla4_8xxx_minidump_process_queue(ha, entry_hdr, |
| 2498 | &data_ptr); |
| 2499 | break; |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2500 | case QLA83XX_POLLRD: |
| 2501 | if (!is_qla8032(ha)) { |
| 2502 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
| 2503 | break; |
| 2504 | } |
| 2505 | rval = qla83xx_minidump_process_pollrd(ha, entry_hdr, |
| 2506 | &data_ptr); |
| 2507 | if (rval != QLA_SUCCESS) |
| 2508 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
| 2509 | break; |
| 2510 | case QLA83XX_RDMUX2: |
| 2511 | if (!is_qla8032(ha)) { |
| 2512 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
| 2513 | break; |
| 2514 | } |
| 2515 | qla83xx_minidump_process_rdmux2(ha, entry_hdr, |
| 2516 | &data_ptr); |
| 2517 | break; |
| 2518 | case QLA83XX_POLLRDMWR: |
| 2519 | if (!is_qla8032(ha)) { |
| 2520 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
| 2521 | break; |
| 2522 | } |
| 2523 | rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr, |
| 2524 | &data_ptr); |
| 2525 | if (rval != QLA_SUCCESS) |
| 2526 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
| 2527 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2528 | case QLA8XXX_RDNOP: |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2529 | default: |
Vikas Chaudhary | 5e9bcec | 2012-08-22 07:55:01 -0400 | [diff] [blame] | 2530 | qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2531 | break; |
| 2532 | } |
| 2533 | |
| 2534 | data_collected = (uint8_t *)data_ptr - |
| 2535 | ((uint8_t *)((uint8_t *)ha->fw_dump + |
| 2536 | ha->fw_dump_tmplt_size)); |
| 2537 | skip_nxt_entry: |
| 2538 | /* next entry in the template */ |
Vikas Chaudhary | 7664a1f | 2012-08-22 07:55:00 -0400 | [diff] [blame] | 2539 | entry_hdr = (struct qla8xxx_minidump_entry_hdr *) |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2540 | (((uint8_t *)entry_hdr) + |
| 2541 | entry_hdr->entry_size); |
| 2542 | } |
| 2543 | |
| 2544 | if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) { |
| 2545 | ql4_printk(KERN_INFO, ha, |
| 2546 | "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", |
| 2547 | data_collected, ha->fw_dump_size); |
| 2548 | goto md_failed; |
| 2549 | } |
| 2550 | |
| 2551 | DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", |
| 2552 | __func__, i)); |
| 2553 | md_failed: |
| 2554 | return rval; |
| 2555 | } |
| 2556 | |
| 2557 | /** |
| 2558 | * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. |
| 2559 | * @ha: pointer to adapter structure |
| 2560 | **/ |
| 2561 | static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) |
| 2562 | { |
| 2563 | char event_string[40]; |
| 2564 | char *envp[] = { event_string, NULL }; |
| 2565 | |
| 2566 | switch (code) { |
| 2567 | case QL4_UEVENT_CODE_FW_DUMP: |
| 2568 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", |
| 2569 | ha->host_no); |
| 2570 | break; |
| 2571 | default: |
| 2572 | /*do nothing*/ |
| 2573 | break; |
| 2574 | } |
| 2575 | |
| 2576 | kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); |
| 2577 | } |
| 2578 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2579 | void qla4_8xxx_get_minidump(struct scsi_qla_host *ha) |
Vikas Chaudhary | aec07ca | 2012-08-22 07:55:07 -0400 | [diff] [blame] | 2580 | { |
| 2581 | if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && |
| 2582 | !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) { |
| 2583 | if (!qla4_8xxx_collect_md_data(ha)) { |
| 2584 | qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); |
| 2585 | set_bit(AF_82XX_FW_DUMPED, &ha->flags); |
| 2586 | } else { |
| 2587 | ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n", |
| 2588 | __func__); |
| 2589 | } |
| 2590 | } |
| 2591 | } |
| 2592 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2593 | /** |
| 2594 | * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw |
| 2595 | * @ha: pointer to adapter structure |
| 2596 | * |
| 2597 | * Note: IDC lock must be held upon entry |
| 2598 | **/ |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2599 | int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2600 | { |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2601 | int rval = QLA_ERROR; |
| 2602 | int i, timeout; |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2603 | uint32_t old_count, count, idc_ctrl; |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2604 | int need_reset = 0, peg_stuck = 1; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2605 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2606 | need_reset = ha->isp_ops->need_reset(ha); |
| 2607 | old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2608 | |
| 2609 | for (i = 0; i < 10; i++) { |
| 2610 | timeout = msleep_interruptible(200); |
| 2611 | if (timeout) { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2612 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, |
| 2613 | QLA8XXX_DEV_FAILED); |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2614 | return rval; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2615 | } |
| 2616 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2617 | count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2618 | if (count != old_count) |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2619 | peg_stuck = 0; |
| 2620 | } |
| 2621 | |
| 2622 | if (need_reset) { |
| 2623 | /* We are trying to perform a recovery here. */ |
| 2624 | if (peg_stuck) |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2625 | ha->isp_ops->rom_lock_recovery(ha); |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2626 | goto dev_initialize; |
| 2627 | } else { |
| 2628 | /* Start of day for this ha context. */ |
| 2629 | if (peg_stuck) { |
| 2630 | /* Either we are the first or recovery in progress. */ |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2631 | ha->isp_ops->rom_lock_recovery(ha); |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2632 | goto dev_initialize; |
| 2633 | } else { |
| 2634 | /* Firmware already running. */ |
| 2635 | rval = QLA_SUCCESS; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2636 | goto dev_ready; |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2637 | } |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2638 | } |
| 2639 | |
| 2640 | dev_initialize: |
| 2641 | /* set to DEV_INITIALIZING */ |
| 2642 | ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2643 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, |
| 2644 | QLA8XXX_DEV_INITIALIZING); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2645 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2646 | /* |
| 2647 | * For ISP8324, if IDC_CTRL GRACEFUL_RESET_BIT1 is set, reset it after |
| 2648 | * device goes to INIT state. |
| 2649 | */ |
| 2650 | if (is_qla8032(ha)) { |
| 2651 | idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL); |
| 2652 | if (idc_ctrl & GRACEFUL_RESET_BIT1) { |
| 2653 | qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, |
| 2654 | (idc_ctrl & ~GRACEFUL_RESET_BIT1)); |
| 2655 | set_bit(AF_83XX_NO_FW_DUMP, &ha->flags); |
| 2656 | } |
| 2657 | } |
| 2658 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2659 | ha->isp_ops->idc_unlock(ha); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2660 | |
| 2661 | if (is_qla8022(ha)) |
| 2662 | qla4_8xxx_get_minidump(ha); |
| 2663 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2664 | rval = ha->isp_ops->restart_firmware(ha); |
| 2665 | ha->isp_ops->idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2666 | |
| 2667 | if (rval != QLA_SUCCESS) { |
| 2668 | ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); |
| 2669 | qla4_8xxx_clear_drv_active(ha); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2670 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, |
| 2671 | QLA8XXX_DEV_FAILED); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2672 | return rval; |
| 2673 | } |
| 2674 | |
| 2675 | dev_ready: |
| 2676 | ql4_printk(KERN_INFO, ha, "HW State: READY\n"); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2677 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2678 | |
Shyam Sundar | b25ee66 | 2010-10-06 22:50:51 -0700 | [diff] [blame] | 2679 | return rval; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2680 | } |
| 2681 | |
| 2682 | /** |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2683 | * qla4_82xx_need_reset_handler - Code to start reset sequence |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2684 | * @ha: pointer to adapter structure |
| 2685 | * |
| 2686 | * Note: IDC lock must be held upon entry |
| 2687 | **/ |
| 2688 | static void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2689 | qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2690 | { |
| 2691 | uint32_t dev_state, drv_state, drv_active; |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2692 | uint32_t active_mask = 0xFFFFFFFF; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2693 | unsigned long reset_timeout; |
| 2694 | |
| 2695 | ql4_printk(KERN_INFO, ha, |
| 2696 | "Performing ISP error recovery\n"); |
| 2697 | |
| 2698 | if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2699 | qla4_82xx_idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2700 | ha->isp_ops->disable_intrs(ha); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2701 | qla4_82xx_idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2702 | } |
| 2703 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2704 | if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2705 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 2706 | "%s(%ld): reset acknowledged\n", |
| 2707 | __func__, ha->host_no)); |
| 2708 | qla4_8xxx_set_rst_ready(ha); |
| 2709 | } else { |
| 2710 | active_mask = (~(1 << (ha->func_num * 4))); |
| 2711 | } |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2712 | |
| 2713 | /* wait for 10 seconds for reset ack from all functions */ |
| 2714 | reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); |
| 2715 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2716 | drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); |
| 2717 | drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2718 | |
| 2719 | ql4_printk(KERN_INFO, ha, |
| 2720 | "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", |
| 2721 | __func__, ha->host_no, drv_state, drv_active); |
| 2722 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2723 | while (drv_state != (drv_active & active_mask)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2724 | if (time_after_eq(jiffies, reset_timeout)) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2725 | ql4_printk(KERN_INFO, ha, |
| 2726 | "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", |
| 2727 | DRIVER_NAME, drv_state, drv_active); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2728 | break; |
| 2729 | } |
| 2730 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2731 | /* |
| 2732 | * When reset_owner times out, check which functions |
| 2733 | * acked/did not ack |
| 2734 | */ |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2735 | if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2736 | ql4_printk(KERN_INFO, ha, |
| 2737 | "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", |
| 2738 | __func__, ha->host_no, drv_state, |
| 2739 | drv_active); |
| 2740 | } |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2741 | qla4_82xx_idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2742 | msleep(1000); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2743 | qla4_82xx_idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2744 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2745 | drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); |
| 2746 | drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2747 | } |
| 2748 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2749 | /* Clear RESET OWNER as we are not going to use it any further */ |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2750 | clear_bit(AF_8XXX_RST_OWNER, &ha->flags); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2751 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 2752 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2753 | ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, |
| 2754 | dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2755 | |
| 2756 | /* Force to DEV_COLD unless someone else is starting a reset */ |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2757 | if (dev_state != QLA8XXX_DEV_INITIALIZING) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2758 | ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2759 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2760 | qla4_8xxx_set_rst_ready(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2761 | } |
| 2762 | } |
| 2763 | |
| 2764 | /** |
| 2765 | * qla4_8xxx_need_qsnt_handler - Code to start qsnt |
| 2766 | * @ha: pointer to adapter structure |
| 2767 | **/ |
| 2768 | void |
| 2769 | qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) |
| 2770 | { |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2771 | ha->isp_ops->idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2772 | qla4_8xxx_set_qsnt_ready(ha); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2773 | ha->isp_ops->idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2774 | } |
| 2775 | |
Vikas Chaudhary | 83dbdf6 | 2012-08-22 07:55:06 -0400 | [diff] [blame] | 2776 | static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha) |
| 2777 | { |
| 2778 | int idc_ver; |
| 2779 | uint32_t drv_active; |
| 2780 | |
| 2781 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
| 2782 | if (drv_active == (1 << (ha->func_num * 4))) { |
| 2783 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, |
| 2784 | QLA82XX_IDC_VERSION); |
| 2785 | ql4_printk(KERN_INFO, ha, |
| 2786 | "%s: IDC version updated to %d\n", __func__, |
| 2787 | QLA82XX_IDC_VERSION); |
| 2788 | } else { |
| 2789 | idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); |
| 2790 | if (QLA82XX_IDC_VERSION != idc_ver) { |
| 2791 | ql4_printk(KERN_INFO, ha, |
| 2792 | "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", |
| 2793 | __func__, QLA82XX_IDC_VERSION, idc_ver); |
| 2794 | } |
| 2795 | } |
| 2796 | } |
| 2797 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2798 | static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha) |
Vikas Chaudhary | 83dbdf6 | 2012-08-22 07:55:06 -0400 | [diff] [blame] | 2799 | { |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2800 | int idc_ver; |
| 2801 | uint32_t drv_active; |
| 2802 | int rval = QLA_SUCCESS; |
| 2803 | |
| 2804 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
| 2805 | if (drv_active == (1 << ha->func_num)) { |
| 2806 | idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); |
| 2807 | idc_ver &= (~0xFF); |
| 2808 | idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE; |
| 2809 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver); |
| 2810 | ql4_printk(KERN_INFO, ha, |
| 2811 | "%s: IDC version updated to %d\n", __func__, |
Vikas Chaudhary | ecca512 | 2012-09-20 07:35:02 -0400 | [diff] [blame] | 2812 | idc_ver); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2813 | } else { |
| 2814 | idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); |
| 2815 | idc_ver &= 0xFF; |
| 2816 | if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) { |
| 2817 | ql4_printk(KERN_INFO, ha, |
| 2818 | "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", |
| 2819 | __func__, QLA83XX_IDC_VER_MAJ_VALUE, |
| 2820 | idc_ver); |
| 2821 | rval = QLA_ERROR; |
| 2822 | goto exit_set_idc_ver; |
| 2823 | } |
Vikas Chaudhary | 83dbdf6 | 2012-08-22 07:55:06 -0400 | [diff] [blame] | 2824 | } |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2825 | |
| 2826 | /* Update IDC_MINOR_VERSION */ |
| 2827 | idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR); |
| 2828 | idc_ver &= ~(0x03 << (ha->func_num * 2)); |
| 2829 | idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2)); |
| 2830 | qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver); |
| 2831 | |
| 2832 | exit_set_idc_ver: |
| 2833 | return rval; |
| 2834 | } |
| 2835 | |
Vikas Chaudhary | 39c9582 | 2012-09-20 07:35:05 -0400 | [diff] [blame^] | 2836 | int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha) |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2837 | { |
| 2838 | uint32_t drv_active; |
| 2839 | int rval = QLA_SUCCESS; |
| 2840 | |
| 2841 | if (test_bit(AF_INIT_DONE, &ha->flags)) |
| 2842 | goto exit_update_idc_reg; |
| 2843 | |
| 2844 | ha->isp_ops->idc_lock(ha); |
| 2845 | qla4_8xxx_set_drv_active(ha); |
| 2846 | |
| 2847 | /* |
| 2848 | * If we are the first driver to load and |
| 2849 | * ql4xdontresethba is not set, clear IDC_CTRL BIT0. |
| 2850 | */ |
| 2851 | if (is_qla8032(ha)) { |
| 2852 | drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); |
| 2853 | if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba) |
| 2854 | qla4_83xx_clear_idc_dontreset(ha); |
| 2855 | } |
| 2856 | |
| 2857 | if (is_qla8022(ha)) { |
| 2858 | qla4_82xx_set_idc_ver(ha); |
| 2859 | } else if (is_qla8032(ha)) { |
| 2860 | rval = qla4_83xx_set_idc_ver(ha); |
| 2861 | if (rval == QLA_ERROR) |
| 2862 | qla4_8xxx_clear_drv_active(ha); |
| 2863 | } |
| 2864 | |
| 2865 | ha->isp_ops->idc_unlock(ha); |
| 2866 | |
| 2867 | exit_update_idc_reg: |
| 2868 | return rval; |
Vikas Chaudhary | 83dbdf6 | 2012-08-22 07:55:06 -0400 | [diff] [blame] | 2869 | } |
| 2870 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2871 | /** |
| 2872 | * qla4_8xxx_device_state_handler - Adapter state machine |
| 2873 | * @ha: pointer to host adapter structure. |
| 2874 | * |
| 2875 | * Note: IDC lock must be UNLOCKED upon entry |
| 2876 | **/ |
| 2877 | int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) |
| 2878 | { |
| 2879 | uint32_t dev_state; |
| 2880 | int rval = QLA_SUCCESS; |
| 2881 | unsigned long dev_init_timeout; |
| 2882 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2883 | rval = qla4_8xxx_update_idc_reg(ha); |
| 2884 | if (rval == QLA_ERROR) |
| 2885 | goto exit_state_handler; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2886 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2887 | dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2888 | DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", |
| 2889 | dev_state, dev_state < MAX_STATES ? |
| 2890 | qdev_state[dev_state] : "Unknown")); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2891 | |
| 2892 | /* wait for 30 seconds for device to go ready */ |
| 2893 | dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); |
| 2894 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2895 | ha->isp_ops->idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2896 | while (1) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2897 | |
| 2898 | if (time_after_eq(jiffies, dev_init_timeout)) { |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2899 | ql4_printk(KERN_WARNING, ha, |
| 2900 | "%s: Device Init Failed 0x%x = %s\n", |
| 2901 | DRIVER_NAME, |
| 2902 | dev_state, dev_state < MAX_STATES ? |
| 2903 | qdev_state[dev_state] : "Unknown"); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2904 | qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, |
| 2905 | QLA8XXX_DEV_FAILED); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2906 | } |
| 2907 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2908 | dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 2909 | ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", |
| 2910 | dev_state, dev_state < MAX_STATES ? |
| 2911 | qdev_state[dev_state] : "Unknown"); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2912 | |
| 2913 | /* NOTE: Make sure idc unlocked upon exit of switch statement */ |
| 2914 | switch (dev_state) { |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2915 | case QLA8XXX_DEV_READY: |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2916 | goto exit; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2917 | case QLA8XXX_DEV_COLD: |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2918 | rval = qla4_8xxx_device_bootstrap(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2919 | goto exit; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2920 | case QLA8XXX_DEV_INITIALIZING: |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2921 | ha->isp_ops->idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2922 | msleep(1000); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2923 | ha->isp_ops->idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2924 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2925 | case QLA8XXX_DEV_NEED_RESET: |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2926 | /* |
| 2927 | * For ISP8324, if NEED_RESET is set by any driver, |
| 2928 | * it should be honored, irrespective of IDC_CTRL |
| 2929 | * DONTRESET_BIT0 |
| 2930 | */ |
| 2931 | if (is_qla8032(ha)) { |
| 2932 | qla4_83xx_need_reset_handler(ha); |
| 2933 | } else if (is_qla8022(ha)) { |
| 2934 | if (!ql4xdontresethba) { |
| 2935 | qla4_82xx_need_reset_handler(ha); |
| 2936 | /* Update timeout value after need |
| 2937 | * reset handler */ |
| 2938 | dev_init_timeout = jiffies + |
| 2939 | (ha->nx_dev_init_timeout * HZ); |
| 2940 | } else { |
| 2941 | ha->isp_ops->idc_unlock(ha); |
| 2942 | msleep(1000); |
| 2943 | ha->isp_ops->idc_lock(ha); |
| 2944 | } |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2945 | } |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2946 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2947 | case QLA8XXX_DEV_NEED_QUIESCENT: |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2948 | /* idc locked/unlocked in handler */ |
| 2949 | qla4_8xxx_need_qsnt_handler(ha); |
Nilesh Javali | e3f37d1 | 2011-12-01 22:42:11 -0800 | [diff] [blame] | 2950 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2951 | case QLA8XXX_DEV_QUIESCENT: |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2952 | ha->isp_ops->idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2953 | msleep(1000); |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2954 | ha->isp_ops->idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2955 | break; |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 2956 | case QLA8XXX_DEV_FAILED: |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2957 | ha->isp_ops->idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2958 | qla4xxx_dead_adapter_cleanup(ha); |
| 2959 | rval = QLA_ERROR; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2960 | ha->isp_ops->idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2961 | goto exit; |
| 2962 | default: |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2963 | ha->isp_ops->idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2964 | qla4xxx_dead_adapter_cleanup(ha); |
| 2965 | rval = QLA_ERROR; |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2966 | ha->isp_ops->idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2967 | goto exit; |
| 2968 | } |
| 2969 | } |
| 2970 | exit: |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 2971 | ha->isp_ops->idc_unlock(ha); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2972 | exit_state_handler: |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2973 | return rval; |
| 2974 | } |
| 2975 | |
| 2976 | int qla4_8xxx_load_risc(struct scsi_qla_host *ha) |
| 2977 | { |
| 2978 | int retval; |
Sarang Radke | 7876499 | 2012-01-11 02:44:18 -0800 | [diff] [blame] | 2979 | |
| 2980 | /* clear the interrupt */ |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 2981 | if (is_qla8032(ha)) { |
| 2982 | writel(0, &ha->qla4_83xx_reg->risc_intr); |
| 2983 | readl(&ha->qla4_83xx_reg->risc_intr); |
| 2984 | } else if (is_qla8022(ha)) { |
| 2985 | writel(0, &ha->qla4_82xx_reg->host_int); |
| 2986 | readl(&ha->qla4_82xx_reg->host_int); |
| 2987 | } |
Sarang Radke | 7876499 | 2012-01-11 02:44:18 -0800 | [diff] [blame] | 2988 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2989 | retval = qla4_8xxx_device_state_handler(ha); |
| 2990 | |
Vikas Chaudhary | f581a3f | 2010-10-06 22:47:48 -0700 | [diff] [blame] | 2991 | if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags)) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2992 | retval = qla4xxx_request_irqs(ha); |
Vikas Chaudhary | f581a3f | 2010-10-06 22:47:48 -0700 | [diff] [blame] | 2993 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 2994 | return retval; |
| 2995 | } |
| 2996 | |
| 2997 | /*****************************************************************************/ |
| 2998 | /* Flash Manipulation Routines */ |
| 2999 | /*****************************************************************************/ |
| 3000 | |
| 3001 | #define OPTROM_BURST_SIZE 0x1000 |
| 3002 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) |
| 3003 | |
| 3004 | #define FARX_DATA_FLAG BIT_31 |
| 3005 | #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 |
| 3006 | #define FARX_ACCESS_FLASH_DATA 0x7FF00000 |
| 3007 | |
| 3008 | static inline uint32_t |
| 3009 | flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) |
| 3010 | { |
| 3011 | return hw->flash_conf_off | faddr; |
| 3012 | } |
| 3013 | |
| 3014 | static inline uint32_t |
| 3015 | flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) |
| 3016 | { |
| 3017 | return hw->flash_data_off | faddr; |
| 3018 | } |
| 3019 | |
| 3020 | static uint32_t * |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3021 | qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3022 | uint32_t faddr, uint32_t length) |
| 3023 | { |
| 3024 | uint32_t i; |
| 3025 | uint32_t val; |
| 3026 | int loops = 0; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3027 | while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3028 | udelay(100); |
| 3029 | cond_resched(); |
| 3030 | loops++; |
| 3031 | } |
| 3032 | if (loops >= 50000) { |
| 3033 | ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); |
| 3034 | return dwptr; |
| 3035 | } |
| 3036 | |
| 3037 | /* Dword reads to flash. */ |
| 3038 | for (i = 0; i < length/4; i++, faddr += 4) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3039 | if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3040 | ql4_printk(KERN_WARNING, ha, |
| 3041 | "Do ROM fast read failed\n"); |
| 3042 | goto done_read; |
| 3043 | } |
| 3044 | dwptr[i] = __constant_cpu_to_le32(val); |
| 3045 | } |
| 3046 | |
| 3047 | done_read: |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3048 | qla4_82xx_rom_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3049 | return dwptr; |
| 3050 | } |
| 3051 | |
| 3052 | /** |
| 3053 | * Address and length are byte address |
| 3054 | **/ |
| 3055 | static uint8_t * |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3056 | qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3057 | uint32_t offset, uint32_t length) |
| 3058 | { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3059 | qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3060 | return buf; |
| 3061 | } |
| 3062 | |
| 3063 | static int |
| 3064 | qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) |
| 3065 | { |
| 3066 | const char *loc, *locations[] = { "DEF", "PCI" }; |
| 3067 | |
| 3068 | /* |
| 3069 | * FLT-location structure resides after the last PCI region. |
| 3070 | */ |
| 3071 | |
| 3072 | /* Begin with sane defaults. */ |
| 3073 | loc = locations[0]; |
| 3074 | *start = FA_FLASH_LAYOUT_ADDR_82; |
| 3075 | |
| 3076 | DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); |
| 3077 | return QLA_SUCCESS; |
| 3078 | } |
| 3079 | |
| 3080 | static void |
| 3081 | qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) |
| 3082 | { |
| 3083 | const char *loc, *locations[] = { "DEF", "FLT" }; |
| 3084 | uint16_t *wptr; |
| 3085 | uint16_t cnt, chksum; |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 3086 | uint32_t start, status; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3087 | struct qla_flt_header *flt; |
| 3088 | struct qla_flt_region *region; |
| 3089 | struct ql82xx_hw_data *hw = &ha->hw; |
| 3090 | |
| 3091 | hw->flt_region_flt = flt_addr; |
| 3092 | wptr = (uint16_t *)ha->request_ring; |
| 3093 | flt = (struct qla_flt_header *)ha->request_ring; |
| 3094 | region = (struct qla_flt_region *)&flt[1]; |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 3095 | |
| 3096 | if (is_qla8022(ha)) { |
| 3097 | qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, |
| 3098 | flt_addr << 2, OPTROM_BURST_SIZE); |
| 3099 | } else if (is_qla8032(ha)) { |
| 3100 | status = qla4_83xx_flash_read_u32(ha, flt_addr << 2, |
| 3101 | (uint8_t *)ha->request_ring, |
| 3102 | 0x400); |
| 3103 | if (status != QLA_SUCCESS) |
| 3104 | goto no_flash_data; |
| 3105 | } |
| 3106 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3107 | if (*wptr == __constant_cpu_to_le16(0xffff)) |
| 3108 | goto no_flash_data; |
| 3109 | if (flt->version != __constant_cpu_to_le16(1)) { |
| 3110 | DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " |
| 3111 | "version=0x%x length=0x%x checksum=0x%x.\n", |
| 3112 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), |
| 3113 | le16_to_cpu(flt->checksum))); |
| 3114 | goto no_flash_data; |
| 3115 | } |
| 3116 | |
| 3117 | cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; |
| 3118 | for (chksum = 0; cnt; cnt--) |
| 3119 | chksum += le16_to_cpu(*wptr++); |
| 3120 | if (chksum) { |
| 3121 | DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " |
| 3122 | "version=0x%x length=0x%x checksum=0x%x.\n", |
| 3123 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), |
| 3124 | chksum)); |
| 3125 | goto no_flash_data; |
| 3126 | } |
| 3127 | |
| 3128 | loc = locations[1]; |
| 3129 | cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); |
| 3130 | for ( ; cnt; cnt--, region++) { |
| 3131 | /* Store addresses as DWORD offsets. */ |
| 3132 | start = le32_to_cpu(region->start) >> 2; |
| 3133 | |
| 3134 | DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " |
| 3135 | "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, |
| 3136 | le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); |
| 3137 | |
| 3138 | switch (le32_to_cpu(region->code) & 0xff) { |
| 3139 | case FLT_REG_FDT: |
| 3140 | hw->flt_region_fdt = start; |
| 3141 | break; |
| 3142 | case FLT_REG_BOOT_CODE_82: |
| 3143 | hw->flt_region_boot = start; |
| 3144 | break; |
| 3145 | case FLT_REG_FW_82: |
Nilesh Javali | 9382395 | 2011-10-07 16:55:39 -0700 | [diff] [blame] | 3146 | case FLT_REG_FW_82_1: |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3147 | hw->flt_region_fw = start; |
| 3148 | break; |
| 3149 | case FLT_REG_BOOTLOAD_82: |
| 3150 | hw->flt_region_bootload = start; |
| 3151 | break; |
Manish Rangankar | 2a991c2 | 2011-07-25 13:48:55 -0500 | [diff] [blame] | 3152 | case FLT_REG_ISCSI_PARAM: |
| 3153 | hw->flt_iscsi_param = start; |
| 3154 | break; |
Lalit Chandivade | 4549415 | 2011-10-07 16:55:42 -0700 | [diff] [blame] | 3155 | case FLT_REG_ISCSI_CHAP: |
| 3156 | hw->flt_region_chap = start; |
| 3157 | hw->flt_chap_size = le32_to_cpu(region->size); |
| 3158 | break; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3159 | } |
| 3160 | } |
| 3161 | goto done; |
| 3162 | |
| 3163 | no_flash_data: |
| 3164 | /* Use hardcoded defaults. */ |
| 3165 | loc = locations[0]; |
| 3166 | |
| 3167 | hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; |
| 3168 | hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; |
| 3169 | hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; |
| 3170 | hw->flt_region_fw = FA_RISC_CODE_ADDR_82; |
Lalit Chandivade | 4549415 | 2011-10-07 16:55:42 -0700 | [diff] [blame] | 3171 | hw->flt_region_chap = FA_FLASH_ISCSI_CHAP; |
| 3172 | hw->flt_chap_size = FA_FLASH_CHAP_SIZE; |
| 3173 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3174 | done: |
| 3175 | DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x " |
| 3176 | "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt, |
| 3177 | hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload, |
| 3178 | hw->flt_region_fw)); |
| 3179 | } |
| 3180 | |
| 3181 | static void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3182 | qla4_82xx_get_fdt_info(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3183 | { |
| 3184 | #define FLASH_BLK_SIZE_4K 0x1000 |
| 3185 | #define FLASH_BLK_SIZE_32K 0x8000 |
| 3186 | #define FLASH_BLK_SIZE_64K 0x10000 |
| 3187 | const char *loc, *locations[] = { "MID", "FDT" }; |
| 3188 | uint16_t cnt, chksum; |
| 3189 | uint16_t *wptr; |
| 3190 | struct qla_fdt_layout *fdt; |
Vikas Chaudhary | 3c3e210 | 2010-08-09 05:14:07 -0700 | [diff] [blame] | 3191 | uint16_t mid = 0; |
| 3192 | uint16_t fid = 0; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3193 | struct ql82xx_hw_data *hw = &ha->hw; |
| 3194 | |
| 3195 | hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
| 3196 | hw->flash_data_off = FARX_ACCESS_FLASH_DATA; |
| 3197 | |
| 3198 | wptr = (uint16_t *)ha->request_ring; |
| 3199 | fdt = (struct qla_fdt_layout *)ha->request_ring; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3200 | qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3201 | hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); |
| 3202 | |
| 3203 | if (*wptr == __constant_cpu_to_le16(0xffff)) |
| 3204 | goto no_flash_data; |
| 3205 | |
| 3206 | if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || |
| 3207 | fdt->sig[3] != 'D') |
| 3208 | goto no_flash_data; |
| 3209 | |
| 3210 | for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; |
| 3211 | cnt++) |
| 3212 | chksum += le16_to_cpu(*wptr++); |
| 3213 | |
| 3214 | if (chksum) { |
| 3215 | DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " |
| 3216 | "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], |
| 3217 | le16_to_cpu(fdt->version))); |
| 3218 | goto no_flash_data; |
| 3219 | } |
| 3220 | |
| 3221 | loc = locations[1]; |
| 3222 | mid = le16_to_cpu(fdt->man_id); |
| 3223 | fid = le16_to_cpu(fdt->id); |
| 3224 | hw->fdt_wrt_disable = fdt->wrt_disable_bits; |
| 3225 | hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); |
| 3226 | hw->fdt_block_size = le32_to_cpu(fdt->block_size); |
| 3227 | |
| 3228 | if (fdt->unprotect_sec_cmd) { |
| 3229 | hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | |
| 3230 | fdt->unprotect_sec_cmd); |
| 3231 | hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? |
| 3232 | flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : |
| 3233 | flash_conf_addr(hw, 0x0336); |
| 3234 | } |
| 3235 | goto done; |
| 3236 | |
| 3237 | no_flash_data: |
| 3238 | loc = locations[0]; |
| 3239 | hw->fdt_block_size = FLASH_BLK_SIZE_64K; |
| 3240 | done: |
| 3241 | DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " |
| 3242 | "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, |
| 3243 | hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, |
| 3244 | hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, |
| 3245 | hw->fdt_block_size)); |
| 3246 | } |
| 3247 | |
| 3248 | static void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3249 | qla4_82xx_get_idc_param(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3250 | { |
| 3251 | #define QLA82XX_IDC_PARAM_ADDR 0x003e885c |
| 3252 | uint32_t *wptr; |
| 3253 | |
| 3254 | if (!is_qla8022(ha)) |
| 3255 | return; |
| 3256 | wptr = (uint32_t *)ha->request_ring; |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3257 | qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3258 | QLA82XX_IDC_PARAM_ADDR , 8); |
| 3259 | |
| 3260 | if (*wptr == __constant_cpu_to_le32(0xffffffff)) { |
| 3261 | ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; |
| 3262 | ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; |
| 3263 | } else { |
| 3264 | ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); |
| 3265 | ha->nx_reset_timeout = le32_to_cpu(*wptr); |
| 3266 | } |
| 3267 | |
| 3268 | DEBUG2(ql4_printk(KERN_DEBUG, ha, |
| 3269 | "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); |
| 3270 | DEBUG2(ql4_printk(KERN_DEBUG, ha, |
| 3271 | "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); |
| 3272 | return; |
| 3273 | } |
| 3274 | |
Vikas Chaudhary | 33693c7 | 2012-08-22 07:55:04 -0400 | [diff] [blame] | 3275 | void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, |
| 3276 | int in_count) |
| 3277 | { |
| 3278 | int i; |
| 3279 | |
| 3280 | /* Load all mailbox registers, except mailbox 0. */ |
| 3281 | for (i = 1; i < in_count; i++) |
| 3282 | writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]); |
| 3283 | |
| 3284 | /* Wakeup firmware */ |
| 3285 | writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]); |
| 3286 | readl(&ha->qla4_82xx_reg->mailbox_in[0]); |
| 3287 | writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint); |
| 3288 | readl(&ha->qla4_82xx_reg->hint); |
| 3289 | } |
| 3290 | |
| 3291 | void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count) |
| 3292 | { |
| 3293 | int intr_status; |
| 3294 | |
| 3295 | intr_status = readl(&ha->qla4_82xx_reg->host_int); |
| 3296 | if (intr_status & ISRX_82XX_RISC_INT) { |
| 3297 | ha->mbox_status_count = out_count; |
| 3298 | intr_status = readl(&ha->qla4_82xx_reg->host_status); |
| 3299 | ha->isp_ops->interrupt_service_routine(ha, intr_status); |
| 3300 | |
| 3301 | if (test_bit(AF_INTERRUPTS_ON, &ha->flags) && |
| 3302 | test_bit(AF_INTx_ENABLED, &ha->flags)) |
| 3303 | qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, |
| 3304 | 0xfbff); |
| 3305 | } |
| 3306 | } |
| 3307 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3308 | int |
| 3309 | qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) |
| 3310 | { |
| 3311 | int ret; |
| 3312 | uint32_t flt_addr; |
| 3313 | |
| 3314 | ret = qla4_8xxx_find_flt_start(ha, &flt_addr); |
| 3315 | if (ret != QLA_SUCCESS) |
| 3316 | return ret; |
| 3317 | |
| 3318 | qla4_8xxx_get_flt_info(ha, flt_addr); |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 3319 | if (is_qla8022(ha)) { |
| 3320 | qla4_82xx_get_fdt_info(ha); |
| 3321 | qla4_82xx_get_idc_param(ha); |
| 3322 | } else if (is_qla8032(ha)) { |
| 3323 | qla4_83xx_get_idc_param(ha); |
| 3324 | } |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3325 | |
| 3326 | return QLA_SUCCESS; |
| 3327 | } |
| 3328 | |
| 3329 | /** |
| 3330 | * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance |
| 3331 | * @ha: pointer to host adapter structure. |
| 3332 | * |
| 3333 | * Remarks: |
| 3334 | * For iSCSI, throws away all I/O and AENs into bit bucket, so they will |
| 3335 | * not be available after successful return. Driver must cleanup potential |
| 3336 | * outstanding I/O's after calling this funcion. |
| 3337 | **/ |
| 3338 | int |
| 3339 | qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) |
| 3340 | { |
| 3341 | int status; |
| 3342 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
| 3343 | uint32_t mbox_sts[MBOX_REG_COUNT]; |
| 3344 | |
| 3345 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
| 3346 | memset(&mbox_sts, 0, sizeof(mbox_sts)); |
| 3347 | |
| 3348 | mbox_cmd[0] = MBOX_CMD_STOP_FW; |
| 3349 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, |
| 3350 | &mbox_cmd[0], &mbox_sts[0]); |
| 3351 | |
| 3352 | DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, |
| 3353 | __func__, status)); |
| 3354 | return status; |
| 3355 | } |
| 3356 | |
| 3357 | /** |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3358 | * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands. |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3359 | * @ha: pointer to host adapter structure. |
| 3360 | **/ |
| 3361 | int |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3362 | qla4_82xx_isp_reset(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3363 | { |
| 3364 | int rval; |
| 3365 | uint32_t dev_state; |
| 3366 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3367 | qla4_82xx_idc_lock(ha); |
| 3368 | dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3369 | |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 3370 | if (dev_state == QLA8XXX_DEV_READY) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3371 | ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3372 | qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
Vikas Chaudhary | de8c72d | 2012-08-22 09:14:24 -0400 | [diff] [blame] | 3373 | QLA8XXX_DEV_NEED_RESET); |
| 3374 | set_bit(AF_8XXX_RST_OWNER, &ha->flags); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3375 | } else |
| 3376 | ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); |
| 3377 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3378 | qla4_82xx_idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3379 | |
| 3380 | rval = qla4_8xxx_device_state_handler(ha); |
| 3381 | |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3382 | qla4_82xx_idc_lock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3383 | qla4_8xxx_clear_rst_ready(ha); |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3384 | qla4_82xx_idc_unlock(ha); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3385 | |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 3386 | if (rval == QLA_SUCCESS) { |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3387 | ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n"); |
Nilesh Javali | 2103363 | 2010-07-30 14:28:07 +0530 | [diff] [blame] | 3388 | clear_bit(AF_FW_RECOVERY, &ha->flags); |
Tej Parkash | 068237c8 | 2012-05-18 04:41:44 -0400 | [diff] [blame] | 3389 | } |
Nilesh Javali | 2103363 | 2010-07-30 14:28:07 +0530 | [diff] [blame] | 3390 | |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3391 | return rval; |
| 3392 | } |
| 3393 | |
| 3394 | /** |
| 3395 | * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number |
| 3396 | * @ha: pointer to host adapter structure. |
| 3397 | * |
| 3398 | **/ |
| 3399 | int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) |
| 3400 | { |
| 3401 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
| 3402 | uint32_t mbox_sts[MBOX_REG_COUNT]; |
| 3403 | struct mbx_sys_info *sys_info; |
| 3404 | dma_addr_t sys_info_dma; |
| 3405 | int status = QLA_ERROR; |
| 3406 | |
| 3407 | sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), |
| 3408 | &sys_info_dma, GFP_KERNEL); |
| 3409 | if (sys_info == NULL) { |
| 3410 | DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", |
| 3411 | ha->host_no, __func__)); |
| 3412 | return status; |
| 3413 | } |
| 3414 | |
| 3415 | memset(sys_info, 0, sizeof(*sys_info)); |
| 3416 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
| 3417 | memset(&mbox_sts, 0, sizeof(mbox_sts)); |
| 3418 | |
| 3419 | mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; |
| 3420 | mbox_cmd[1] = LSDW(sys_info_dma); |
| 3421 | mbox_cmd[2] = MSDW(sys_info_dma); |
| 3422 | mbox_cmd[4] = sizeof(*sys_info); |
| 3423 | |
| 3424 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], |
| 3425 | &mbox_sts[0]) != QLA_SUCCESS) { |
| 3426 | DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", |
| 3427 | ha->host_no, __func__)); |
| 3428 | goto exit_validate_mac82; |
| 3429 | } |
| 3430 | |
Vikas Chaudhary | 2ccdf0d | 2010-07-30 14:27:45 +0530 | [diff] [blame] | 3431 | /* Make sure we receive the minimum required data to cache internally */ |
| 3432 | if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) { |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3433 | DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" |
| 3434 | " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); |
| 3435 | goto exit_validate_mac82; |
| 3436 | |
| 3437 | } |
| 3438 | |
| 3439 | /* Save M.A.C. address & serial_number */ |
Manish Rangankar | 2a991c2 | 2011-07-25 13:48:55 -0500 | [diff] [blame] | 3440 | ha->port_num = sys_info->port_num; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3441 | memcpy(ha->my_mac, &sys_info->mac_addr[0], |
| 3442 | min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); |
| 3443 | memcpy(ha->serial_number, &sys_info->serial_number, |
| 3444 | min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); |
Vikas Chaudhary | 91ec7ce | 2011-08-01 03:26:17 -0700 | [diff] [blame] | 3445 | memcpy(ha->model_name, &sys_info->board_id_str, |
| 3446 | min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); |
| 3447 | ha->phy_port_cnt = sys_info->phys_port_cnt; |
| 3448 | ha->phy_port_num = sys_info->port_num; |
| 3449 | ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3450 | |
| 3451 | DEBUG2(printk("scsi%ld: %s: " |
| 3452 | "mac %02x:%02x:%02x:%02x:%02x:%02x " |
| 3453 | "serial %s\n", ha->host_no, __func__, |
| 3454 | ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], |
| 3455 | ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], |
| 3456 | ha->serial_number)); |
| 3457 | |
| 3458 | status = QLA_SUCCESS; |
| 3459 | |
| 3460 | exit_validate_mac82: |
| 3461 | dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, |
| 3462 | sys_info_dma); |
| 3463 | return status; |
| 3464 | } |
| 3465 | |
| 3466 | /* Interrupt handling helpers. */ |
| 3467 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 3468 | int qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3469 | { |
| 3470 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
| 3471 | uint32_t mbox_sts[MBOX_REG_COUNT]; |
| 3472 | |
| 3473 | DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); |
| 3474 | |
| 3475 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
| 3476 | memset(&mbox_sts, 0, sizeof(mbox_sts)); |
| 3477 | mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; |
| 3478 | mbox_cmd[1] = INTR_ENABLE; |
| 3479 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], |
| 3480 | &mbox_sts[0]) != QLA_SUCCESS) { |
| 3481 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 3482 | "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", |
| 3483 | __func__, mbox_sts[0])); |
| 3484 | return QLA_ERROR; |
| 3485 | } |
| 3486 | return QLA_SUCCESS; |
| 3487 | } |
| 3488 | |
Vikas Chaudhary | 6e7b429 | 2012-08-22 07:55:08 -0400 | [diff] [blame] | 3489 | int qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3490 | { |
| 3491 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
| 3492 | uint32_t mbox_sts[MBOX_REG_COUNT]; |
| 3493 | |
| 3494 | DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); |
| 3495 | |
| 3496 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
| 3497 | memset(&mbox_sts, 0, sizeof(mbox_sts)); |
| 3498 | mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; |
| 3499 | mbox_cmd[1] = INTR_DISABLE; |
| 3500 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], |
| 3501 | &mbox_sts[0]) != QLA_SUCCESS) { |
| 3502 | DEBUG2(ql4_printk(KERN_INFO, ha, |
| 3503 | "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", |
| 3504 | __func__, mbox_sts[0])); |
| 3505 | return QLA_ERROR; |
| 3506 | } |
| 3507 | |
| 3508 | return QLA_SUCCESS; |
| 3509 | } |
| 3510 | |
| 3511 | void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3512 | qla4_82xx_enable_intrs(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3513 | { |
| 3514 | qla4_8xxx_mbx_intr_enable(ha); |
| 3515 | |
| 3516 | spin_lock_irq(&ha->hardware_lock); |
| 3517 | /* BIT 10 - reset */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3518 | qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3519 | spin_unlock_irq(&ha->hardware_lock); |
| 3520 | set_bit(AF_INTERRUPTS_ON, &ha->flags); |
| 3521 | } |
| 3522 | |
| 3523 | void |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3524 | qla4_82xx_disable_intrs(struct scsi_qla_host *ha) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3525 | { |
Sarang Radke | 5fa8b57 | 2011-03-23 08:07:33 -0700 | [diff] [blame] | 3526 | if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3527 | qla4_8xxx_mbx_intr_disable(ha); |
| 3528 | |
| 3529 | spin_lock_irq(&ha->hardware_lock); |
| 3530 | /* BIT 10 - set */ |
Vikas Chaudhary | f8086f4 | 2012-08-22 07:54:59 -0400 | [diff] [blame] | 3531 | qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3532 | spin_unlock_irq(&ha->hardware_lock); |
Vikas Chaudhary | f4f5df23 | 2010-07-28 15:53:44 +0530 | [diff] [blame] | 3533 | } |
| 3534 | |
| 3535 | struct ql4_init_msix_entry { |
| 3536 | uint16_t entry; |
| 3537 | uint16_t index; |
| 3538 | const char *name; |
| 3539 | irq_handler_t handler; |
| 3540 | }; |
| 3541 | |
| 3542 | static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { |
| 3543 | { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, |
| 3544 | "qla4xxx (default)", |
| 3545 | (irq_handler_t)qla4_8xxx_default_intr_handler }, |
| 3546 | { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, |
| 3547 | "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, |
| 3548 | }; |
| 3549 | |
| 3550 | void |
| 3551 | qla4_8xxx_disable_msix(struct scsi_qla_host *ha) |
| 3552 | { |
| 3553 | int i; |
| 3554 | struct ql4_msix_entry *qentry; |
| 3555 | |
| 3556 | for (i = 0; i < QLA_MSIX_ENTRIES; i++) { |
| 3557 | qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; |
| 3558 | if (qentry->have_irq) { |
| 3559 | free_irq(qentry->msix_vector, ha); |
| 3560 | DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", |
| 3561 | __func__, qla4_8xxx_msix_entries[i].name)); |
| 3562 | } |
| 3563 | } |
| 3564 | pci_disable_msix(ha->pdev); |
| 3565 | clear_bit(AF_MSIX_ENABLED, &ha->flags); |
| 3566 | } |
| 3567 | |
| 3568 | int |
| 3569 | qla4_8xxx_enable_msix(struct scsi_qla_host *ha) |
| 3570 | { |
| 3571 | int i, ret; |
| 3572 | struct msix_entry entries[QLA_MSIX_ENTRIES]; |
| 3573 | struct ql4_msix_entry *qentry; |
| 3574 | |
| 3575 | for (i = 0; i < QLA_MSIX_ENTRIES; i++) |
| 3576 | entries[i].entry = qla4_8xxx_msix_entries[i].entry; |
| 3577 | |
| 3578 | ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries)); |
| 3579 | if (ret) { |
| 3580 | ql4_printk(KERN_WARNING, ha, |
| 3581 | "MSI-X: Failed to enable support -- %d/%d\n", |
| 3582 | QLA_MSIX_ENTRIES, ret); |
| 3583 | goto msix_out; |
| 3584 | } |
| 3585 | set_bit(AF_MSIX_ENABLED, &ha->flags); |
| 3586 | |
| 3587 | for (i = 0; i < QLA_MSIX_ENTRIES; i++) { |
| 3588 | qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; |
| 3589 | qentry->msix_vector = entries[i].vector; |
| 3590 | qentry->msix_entry = entries[i].entry; |
| 3591 | qentry->have_irq = 0; |
| 3592 | ret = request_irq(qentry->msix_vector, |
| 3593 | qla4_8xxx_msix_entries[i].handler, 0, |
| 3594 | qla4_8xxx_msix_entries[i].name, ha); |
| 3595 | if (ret) { |
| 3596 | ql4_printk(KERN_WARNING, ha, |
| 3597 | "MSI-X: Unable to register handler -- %x/%d.\n", |
| 3598 | qla4_8xxx_msix_entries[i].index, ret); |
| 3599 | qla4_8xxx_disable_msix(ha); |
| 3600 | goto msix_out; |
| 3601 | } |
| 3602 | qentry->have_irq = 1; |
| 3603 | DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", |
| 3604 | __func__, qla4_8xxx_msix_entries[i].name)); |
| 3605 | } |
| 3606 | msix_out: |
| 3607 | return ret; |
| 3608 | } |