edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 1 | /* Driver for Realtek RTS51xx USB card reader |
| 2 | * Header file |
| 3 | * |
| 4 | * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2, or (at your option) any |
| 9 | * later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but |
| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | * |
| 19 | * Author: |
| 20 | * wwang (wei_wang@realsil.com.cn) |
| 21 | * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China |
| 22 | * Maintainer: |
| 23 | * Edwin Rong (edwin_rong@realsil.com.cn) |
| 24 | * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China |
| 25 | */ |
| 26 | |
| 27 | #ifndef __RTS51X_CHIP_H |
| 28 | #define __RTS51X_CHIP_H |
| 29 | |
| 30 | #include <linux/usb.h> |
| 31 | #include <linux/usb_usual.h> |
| 32 | #include <linux/blkdev.h> |
| 33 | #include <linux/completion.h> |
| 34 | #include <linux/mutex.h> |
| 35 | #include <scsi/scsi_host.h> |
| 36 | |
| 37 | #include "trace.h" |
| 38 | |
| 39 | #define SUPPORT_CPRM |
| 40 | #define SUPPORT_MAGIC_GATE |
| 41 | #define SUPPORT_MSXC |
Oleksij Rempel | 63bb174 | 2012-05-04 17:14:34 +0200 | [diff] [blame] | 42 | #define USING_POLLING_CYCLE_DELINK |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 43 | |
| 44 | #ifdef SUPPORT_MAGIC_GA |
| 45 | /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICVTE */ |
| 46 | #define MG_SET_ICV_SLOW |
| 47 | #endif |
| 48 | |
| 49 | #ifdef SUPPORT_MSXC |
| 50 | #define XC_POWERCLASS |
| 51 | #define SUPPORT_PCGL_1P18 |
| 52 | #endif |
| 53 | |
| 54 | #define GET_CARD_STATUS_USING_EPC |
| 55 | |
| 56 | #define CLOSE_SSC_POWER |
| 57 | |
| 58 | #define SUPPORT_OCP |
| 59 | |
| 60 | #define MS_SPEEDUP |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 61 | |
| 62 | #define SD_XD_IO_FOLLOW_PWR |
| 63 | |
| 64 | #define SD_NR 2 |
| 65 | #define MS_NR 3 |
| 66 | #define XD_NR 4 |
| 67 | #define SD_CARD (1 << SD_NR) |
| 68 | #define MS_CARD (1 << MS_NR) |
| 69 | #define XD_CARD (1 << XD_NR) |
| 70 | |
| 71 | #define SD_CD 0x01 |
| 72 | #define MS_CD 0x02 |
| 73 | #define XD_CD 0x04 |
| 74 | #define SD_WP 0x08 |
| 75 | |
| 76 | #define MAX_ALLOWED_LUN_CNT 8 |
| 77 | #define CMD_BUF_LEN 1024 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 78 | #define POLLING_INTERVAL 50 /* 50ms */ |
| 79 | |
| 80 | #define XD_FREE_TABLE_CNT 1200 |
| 81 | #define MS_FREE_TABLE_CNT 512 |
| 82 | |
| 83 | /* Bit Operation */ |
| 84 | #define SET_BIT(data, idx) ((data) |= 1 << (idx)) |
| 85 | #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx))) |
| 86 | #define CHK_BIT(data, idx) ((data) & (1 << (idx))) |
| 87 | |
| 88 | /* Command type */ |
| 89 | #define READ_REG_CMD 0 |
| 90 | #define WRITE_REG_CMD 1 |
| 91 | #define CHECK_REG_CMD 2 |
| 92 | |
| 93 | #define PACKET_TYPE 4 |
| 94 | #define CNT_H 5 |
| 95 | #define CNT_L 6 |
| 96 | #define STAGE_FLAG 7 |
| 97 | #define CMD_OFFSET 8 |
| 98 | |
| 99 | /* Packet type */ |
| 100 | #define BATCH_CMD 0 |
| 101 | #define SEQ_READ 1 |
| 102 | #define SEQ_WRITE 2 |
| 103 | |
| 104 | /* Stage flag */ |
| 105 | #define STAGE_R 0x01 |
| 106 | #define STAGE_DI 0x02 |
| 107 | #define STAGE_DO 0x04 |
| 108 | /* Return MS_TRANS_CFG, GET_INT */ |
| 109 | #define STAGE_MS_STATUS 0x08 |
| 110 | /* Return XD_CFG, XD_CTL, XD_PAGE_STATUS */ |
| 111 | #define STAGE_XD_STATUS 0x10 |
| 112 | /* Command stage mode */ |
| 113 | #define MODE_C 0x00 |
| 114 | #define MODE_CR (STAGE_R) |
| 115 | #define MODE_CDIR (STAGE_R | STAGE_DI) |
| 116 | #define MODE_CDOR (STAGE_R | STAGE_DO) |
| 117 | |
| 118 | /* Function return code */ |
| 119 | #ifndef STATUS_SUCCESS |
| 120 | #define STATUS_SUCCESS 0 |
| 121 | #endif |
| 122 | |
| 123 | #define STATUS_FAIL 1 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 124 | #define STATUS_TIMEDOUT 4 |
| 125 | #define STATUS_NOMEM 5 |
| 126 | #define STATUS_TRANS_SHORT 6 |
| 127 | #define STATUS_TRANS_LONG 7 |
| 128 | #define STATUS_STALLED 8 |
| 129 | #define STATUS_ERROR 10 |
| 130 | |
| 131 | #define IDLE_MAX_COUNT 10 |
| 132 | #define POLLING_WAIT_CNT 1 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 133 | #define LED_GPIO 0 |
| 134 | |
| 135 | /* package */ |
| 136 | #define QFN24 0 |
| 137 | #define LQFP48 1 |
| 138 | |
| 139 | #define USB_11 0 |
| 140 | #define USB_20 1 |
| 141 | |
| 142 | /* |
| 143 | * Transport return codes |
| 144 | */ |
| 145 | /* Transport good, command good */ |
| 146 | #define TRANSPORT_GOOD 0 |
| 147 | /* Transport good, command failed */ |
| 148 | #define TRANSPORT_FAILED 1 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 149 | /* Transport bad (i.e. device dead) */ |
| 150 | #define TRANSPORT_ERROR 3 |
| 151 | |
| 152 | /* Supported Clock */ |
| 153 | enum card_clock { CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, CLK_80, CLK_100 }; |
| 154 | |
| 155 | #ifdef _MSG_TRACE |
| 156 | |
| 157 | #define TRACE_ITEM_CNT 64 |
| 158 | |
| 159 | struct trace_msg_t { |
| 160 | u16 line; |
| 161 | #define MSG_FUNC_LEN 64 |
| 162 | char func[MSG_FUNC_LEN]; |
| 163 | #define MSG_FILE_LEN 32 |
| 164 | char file[MSG_FILE_LEN]; |
| 165 | #define TIME_VAL_LEN 16 |
| 166 | u8 timeval_buf[TIME_VAL_LEN]; |
| 167 | u8 valid; |
| 168 | }; |
| 169 | |
| 170 | #endif /* _MSG_TRACE */ |
| 171 | |
| 172 | /* Size of the autosense data buffer */ |
| 173 | #define SENSE_SIZE 18 |
| 174 | |
| 175 | /* Sense type */ |
| 176 | #define SENSE_TYPE_NO_SENSE 0 |
| 177 | #define SENSE_TYPE_MEDIA_CHANGE 1 |
| 178 | #define SENSE_TYPE_MEDIA_NOT_PRESENT 2 |
| 179 | #define SENSE_TYPE_MEDIA_LBA_OVER_RANGE 3 |
| 180 | #define SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT 4 |
| 181 | #define SENSE_TYPE_MEDIA_WRITE_PROTECT 5 |
| 182 | #define SENSE_TYPE_MEDIA_INVALID_CMD_FIELD 6 |
| 183 | #define SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR 7 |
| 184 | #define SENSE_TYPE_MEDIA_WRITE_ERR 8 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 185 | #define SENSE_TYPE_FORMAT_CMD_FAILED 10 |
| 186 | #ifdef SUPPORT_MAGIC_GATE |
| 187 | /* COPY PROTECTION KEY EXCHANGE FAILURE - KEY NOT ESTABLISHED */ |
| 188 | #define SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB 0x0b |
| 189 | /* COPY PROTECTION KEY EXCHANGE FAILURE - AUTHENTICATION FAILURE */ |
| 190 | #define SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN 0x0c |
| 191 | /* INCOMPATIBLE MEDIUM INSTALLED */ |
| 192 | #define SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM 0x0d |
| 193 | /* WRITE ERROR */ |
| 194 | #define SENSE_TYPE_MG_WRITE_ERR 0x0e |
| 195 | #endif |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 196 | |
| 197 | /*---- sense key ----*/ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 198 | #define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 199 | |
| 200 | /*----------------------------------- |
| 201 | SENSE_DATA |
| 202 | -----------------------------------*/ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 203 | |
| 204 | /*---- error code ----*/ |
| 205 | #define CUR_ERR 0x70 /* current error */ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 206 | |
Oleksij Rempel | 39d6573 | 2012-05-10 09:59:38 +0200 | [diff] [blame^] | 207 | /*---- sense key Infomation ----*/ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 208 | |
| 209 | #define SKSV 0x80 |
| 210 | #define CDB_ILLEGAL 0x40 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 211 | |
| 212 | /*---- ASC ----*/ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 213 | #define ASC_INVLD_CDB 0x24 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 214 | |
| 215 | /*---- ASQC ----*/ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 216 | #define ASCQ_INVLD_CDB 0x00 |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 217 | |
| 218 | struct sense_data_t { |
| 219 | unsigned char err_code; /* error code */ |
| 220 | /* bit7 : valid */ |
| 221 | /* (1 : SCSI2) */ |
| 222 | /* (0 : Vendor specific) */ |
| 223 | /* bit6-0 : error code */ |
| 224 | /* (0x70 : current error) */ |
| 225 | /* (0x71 : specific command error) */ |
| 226 | unsigned char seg_no; /* segment No. */ |
| 227 | unsigned char sense_key; /* byte5 : ILI */ |
| 228 | /* bit3-0 : sense key */ |
Masanari Iida | feb5680 | 2012-05-09 03:06:46 +0900 | [diff] [blame] | 229 | unsigned char info[4]; /* information */ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 230 | unsigned char ad_sense_len; /* additional sense data length */ |
Masanari Iida | feb5680 | 2012-05-09 03:06:46 +0900 | [diff] [blame] | 231 | unsigned char cmd_info[4]; /* command specific information */ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 232 | unsigned char asc; /* ASC */ |
| 233 | unsigned char ascq; /* ASCQ */ |
| 234 | unsigned char rfu; /* FRU */ |
Masanari Iida | feb5680 | 2012-05-09 03:06:46 +0900 | [diff] [blame] | 235 | unsigned char sns_key_info[3]; /* sense key specific information */ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 236 | }; |
| 237 | |
| 238 | /* sd_ctl bit map */ |
| 239 | /* SD push point control, bit 0, 1 */ |
| 240 | #define SD_PUSH_POINT_CTL_MASK 0x03 |
| 241 | #define SD_PUSH_POINT_DELAY 0x01 |
| 242 | #define SD_PUSH_POINT_AUTO 0x02 |
| 243 | /* SD sample point control, bit 2, 3 */ |
| 244 | #define SD_SAMPLE_POINT_CTL_MASK 0x0C |
| 245 | #define SD_SAMPLE_POINT_DELAY 0x04 |
| 246 | #define SD_SAMPLE_POINT_AUTO 0x08 |
| 247 | /* SD DDR Tx phase set by user, bit 4 */ |
| 248 | #define SD_DDR_TX_PHASE_SET_BY_USER 0x10 |
| 249 | /* MMC DDR Tx phase set by user, bit 5 */ |
| 250 | #define MMC_DDR_TX_PHASE_SET_BY_USER 0x20 |
| 251 | /* Support MMC DDR mode, bit 6 */ |
| 252 | /*#define SUPPORT_MMC_DDR_MODE 0x40 */ |
| 253 | #define SUPPORT_UHS50_MMC44 0x40 |
| 254 | |
| 255 | struct rts51x_option { |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 256 | int mspro_formatter_enable; |
| 257 | |
| 258 | /* card clock expected by user for fpga platform */ |
| 259 | int fpga_sd_sdr104_clk; |
| 260 | int fpga_sd_ddr50_clk; |
| 261 | int fpga_sd_sdr50_clk; |
| 262 | int fpga_sd_hs_clk; |
| 263 | int fpga_mmc_52m_clk; |
| 264 | int fpga_ms_hg_clk; |
| 265 | int fpga_ms_4bit_clk; |
| 266 | |
| 267 | /* card clock expected by user for asic platform */ |
| 268 | int asic_sd_sdr104_clk; |
| 269 | int asic_sd_ddr50_clk; |
| 270 | int asic_sd_sdr50_clk; |
| 271 | int asic_sd_hs_clk; |
| 272 | int asic_mmc_52m_clk; |
| 273 | int asic_ms_hg_clk; |
| 274 | int asic_ms_4bit_clk; |
| 275 | |
| 276 | u8 ssc_depth_sd_sdr104; /* sw */ |
| 277 | u8 ssc_depth_sd_ddr50; /* sw */ |
| 278 | u8 ssc_depth_sd_sdr50; /* sw */ |
| 279 | u8 ssc_depth_sd_hs; /* sw */ |
| 280 | u8 ssc_depth_mmc_52m; /* sw */ |
| 281 | u8 ssc_depth_ms_hg; /* sw */ |
| 282 | u8 ssc_depth_ms_4bit; /* sw */ |
| 283 | u8 ssc_depth_low_speed; /* sw */ |
| 284 | |
| 285 | /* SD/MMC Tx phase */ |
| 286 | int sd_ddr_tx_phase; /* Enabled by bit 4 of sd_ctl */ |
| 287 | int mmc_ddr_tx_phase; /* Enabled by bit 5 of sd_ctl */ |
| 288 | |
| 289 | /* priority of choosing sd speed funciton */ |
| 290 | u32 sd_speed_prior; |
| 291 | |
| 292 | /* sd card control */ |
| 293 | u32 sd_ctl; |
| 294 | |
| 295 | /* Enable Selective Suspend */ |
| 296 | int ss_en; |
| 297 | /* Interval to enter SS from IDLE state (second) */ |
| 298 | int ss_delay; |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 299 | u8 ww_enable; /* sangdy2010-08-03:add for remote wakeup */ |
| 300 | |
| 301 | /* Enable SSC clock */ |
| 302 | int ssc_en; |
| 303 | |
| 304 | int auto_delink_en; |
| 305 | |
| 306 | /* sangdy2010-07-13:add FT2 fast mode */ |
| 307 | int FT2_fast_mode; |
| 308 | /* sangdy2010-07-15: |
| 309 | * add for config delay between 1/4 PMOS and 3/4 PMOS */ |
| 310 | int pwr_delay; |
| 311 | |
| 312 | int xd_rw_step; /* add to tune xd tRP */ |
| 313 | int D3318_off_delay; /* add to tune D3318 off delay time */ |
| 314 | int delink_delay; /* add to tune delink delay time */ |
| 315 | /* add for rts5129 to enable/disable D3318 off */ |
| 316 | u8 rts5129_D3318_off_enable; |
| 317 | u8 sd20_pad_drive; /* add to config SD20 PAD drive */ |
| 318 | u8 sd30_pad_drive; /* add to config SD30 pad drive */ |
| 319 | /*if reset or rw fail,then set SD20 pad drive again */ |
| 320 | u8 reset_or_rw_fail_set_pad_drive; |
| 321 | |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 322 | u8 debounce_num; /* debounce number */ |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 323 | u8 led_toggle_interval; /* used to control led toggle speed */ |
| 324 | int xd_rwn_step; |
| 325 | u8 sd_send_status_en; |
| 326 | /* used to store default phase which is |
| 327 | * used when phase tune all pass. */ |
| 328 | u8 ddr50_tx_phase; |
| 329 | u8 ddr50_rx_phase; |
| 330 | u8 sdr50_tx_phase; |
| 331 | u8 sdr50_rx_phase; |
| 332 | /* used to enable select sdr50 tx phase according to proportion. */ |
| 333 | u8 sdr50_phase_sel; |
| 334 | u8 ms_errreg_fix; |
| 335 | u8 reset_mmc_first; |
| 336 | u8 speed_mmc; /* when set, then try CMD55 only twice */ |
| 337 | u8 led_always_on; /* if set, then led always on when card exist */ |
| 338 | u8 dv18_voltage; /* add to tune dv18 voltage */ |
| 339 | }; |
| 340 | |
| 341 | #define MS_FORMATTER_ENABLED(chip) ((chip)->option.mspro_formatter_enable) |
| 342 | |
| 343 | struct rts51x_chip; |
| 344 | |
| 345 | typedef int (*card_rw_func) (struct scsi_cmnd *srb, struct rts51x_chip *chip, |
| 346 | u32 sec_addr, u16 sec_cnt); |
| 347 | |
| 348 | /* For MS Card */ |
| 349 | #define MAX_DEFECTIVE_BLOCK 10 |
| 350 | |
| 351 | struct zone_entry { |
| 352 | u16 *l2p_table; |
| 353 | u16 *free_table; |
| 354 | u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */ |
| 355 | int set_index; |
| 356 | int get_index; |
| 357 | int unused_blk_cnt; |
| 358 | int disable_count; |
| 359 | /* To indicate whether the L2P table of this zone has been built. */ |
| 360 | int build_flag; |
| 361 | }; |
| 362 | |
| 363 | struct xd_delay_write_tag { |
| 364 | u32 old_phyblock; |
| 365 | u32 new_phyblock; |
| 366 | u32 logblock; |
| 367 | u8 pageoff; |
| 368 | u8 delay_write_flag; |
| 369 | }; |
| 370 | |
| 371 | struct xd_info { |
| 372 | u8 maker_code; |
| 373 | u8 device_code; |
| 374 | u8 block_shift; |
| 375 | u8 page_off; |
| 376 | u8 addr_cycle; |
| 377 | u16 cis_block; |
| 378 | u8 multi_flag; |
| 379 | u8 err_code; |
| 380 | u32 capacity; |
| 381 | |
| 382 | struct zone_entry *zone; |
| 383 | int zone_cnt; |
| 384 | |
| 385 | struct xd_delay_write_tag delay_write; |
| 386 | |
| 387 | int counter; |
| 388 | |
| 389 | int xd_clock; |
| 390 | }; |
| 391 | |
| 392 | #define TYPE_SD 0x0000 |
| 393 | #define TYPE_MMC 0x0001 |
| 394 | |
| 395 | /* TYPE_SD */ |
| 396 | #define SD_HS 0x0100 |
| 397 | #define SD_SDR50 0x0200 |
| 398 | #define SD_DDR50 0x0400 |
| 399 | #define SD_SDR104 0x0800 |
| 400 | #define SD_HCXC 0x1000 |
| 401 | |
| 402 | /* TYPE_MMC */ |
| 403 | #define MMC_26M 0x0100 |
| 404 | #define MMC_52M 0x0200 |
| 405 | #define MMC_4BIT 0x0400 |
| 406 | #define MMC_8BIT 0x0800 |
| 407 | #define MMC_SECTOR_MODE 0x1000 |
| 408 | #define MMC_DDR52 0x2000 |
| 409 | |
| 410 | /* SD card */ |
| 411 | #define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD) |
| 412 | #define CHK_SD_HS(sd_card) \ |
| 413 | (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS)) |
| 414 | #define CHK_SD_SDR50(sd_card) \ |
| 415 | (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50)) |
| 416 | #define CHK_SD_DDR50(sd_card) \ |
| 417 | (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50)) |
| 418 | #define CHK_SD_SDR104(sd_card) \ |
| 419 | (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104)) |
| 420 | #define CHK_SD_HCXC(sd_card) \ |
| 421 | (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC)) |
| 422 | #define CHK_SD30_SPEED(sd_card) \ |
| 423 | (CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) ||\ |
| 424 | CHK_SD_SDR104(sd_card)) |
| 425 | |
| 426 | #define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD) |
| 427 | #define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS) |
| 428 | #define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50) |
| 429 | #define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50) |
| 430 | #define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104) |
| 431 | #define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC) |
| 432 | |
| 433 | #define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS) |
| 434 | #define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50) |
| 435 | #define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50) |
| 436 | #define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104) |
| 437 | #define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC) |
| 438 | #define CLR_SD30_SPEED(sd_card) \ |
| 439 | ((sd_card)->sd_type &= ~(SD_SDR50|SD_DDR50|SD_SDR104)) |
| 440 | |
| 441 | /* MMC card */ |
| 442 | #define CHK_MMC(sd_card) \ |
| 443 | (((sd_card)->sd_type & 0xFF) == TYPE_MMC) |
| 444 | #define CHK_MMC_26M(sd_card) \ |
| 445 | (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M)) |
| 446 | #define CHK_MMC_52M(sd_card) \ |
| 447 | (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M)) |
| 448 | #define CHK_MMC_4BIT(sd_card) \ |
| 449 | (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT)) |
| 450 | #define CHK_MMC_8BIT(sd_card) \ |
| 451 | (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT)) |
| 452 | #define CHK_MMC_SECTOR_MODE(sd_card)\ |
| 453 | (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE)) |
| 454 | #define CHK_MMC_DDR52(sd_card) \ |
| 455 | (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52)) |
| 456 | |
| 457 | #define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC) |
| 458 | #define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M) |
| 459 | #define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M) |
| 460 | #define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT) |
| 461 | #define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT) |
| 462 | #define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE) |
| 463 | #define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52) |
| 464 | |
| 465 | #define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M) |
| 466 | #define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M) |
| 467 | #define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT) |
| 468 | #define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT) |
| 469 | #define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE) |
| 470 | #define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52) |
| 471 | |
| 472 | #define CHK_MMC_HS(sd_card) \ |
| 473 | (CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card)) |
| 474 | #define CLR_MMC_HS(sd_card) \ |
| 475 | do { \ |
| 476 | CLR_MMC_DDR52(sd_card); \ |
| 477 | CLR_MMC_52M(sd_card); \ |
| 478 | CLR_MMC_26M(sd_card); \ |
| 479 | } while (0) |
| 480 | |
| 481 | #define SD_SUPPORT_CLASS_TEN 0x01 |
| 482 | #define SD_SUPPORT_1V8 0x02 |
| 483 | |
| 484 | #define SD_SET_CLASS_TEN(sd_card) \ |
| 485 | ((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN) |
| 486 | #define SD_CHK_CLASS_TEN(sd_card) \ |
| 487 | ((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN) |
| 488 | #define SD_CLR_CLASS_TEN(sd_card) \ |
| 489 | ((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN) |
| 490 | #define SD_SET_1V8(sd_card) \ |
| 491 | ((sd_card)->sd_setting |= SD_SUPPORT_1V8) |
| 492 | #define SD_CHK_1V8(sd_card) \ |
| 493 | ((sd_card)->sd_setting & SD_SUPPORT_1V8) |
| 494 | #define SD_CLR_1V8(sd_card) \ |
| 495 | ((sd_card)->sd_setting &= ~SD_SUPPORT_1V8) |
| 496 | #define CLR_RETRY_SD20_MODE(sd_card) \ |
| 497 | ((sd_card)->retry_SD20_mode = 0) |
| 498 | #define SET_RETRY_SD20_MODE(sd_card) \ |
| 499 | ((sd_card)->retry_SD20_mode = 1) |
| 500 | #define CHK_RETRY_SD20_MODE(sd_card) \ |
| 501 | ((sd_card)->retry_SD20_mode == 1) |
| 502 | |
| 503 | struct sd_info { |
| 504 | u16 sd_type; |
| 505 | u8 err_code; |
| 506 | u8 sd_data_buf_ready; |
| 507 | u32 sd_addr; |
| 508 | u32 capacity; |
| 509 | |
| 510 | u8 raw_csd[16]; |
| 511 | u8 raw_scr[8]; |
| 512 | |
| 513 | /* Sequential RW */ |
| 514 | int seq_mode; |
| 515 | enum dma_data_direction pre_dir; |
| 516 | u32 pre_sec_addr; |
| 517 | u16 pre_sec_cnt; |
| 518 | |
| 519 | int counter; |
| 520 | |
| 521 | int sd_clock; |
| 522 | |
| 523 | #ifdef SUPPORT_CPRM |
| 524 | int sd_pass_thru_en; |
| 525 | int pre_cmd_err; |
| 526 | u8 last_rsp_type; |
| 527 | u8 rsp[17]; |
| 528 | #endif |
| 529 | |
| 530 | u8 func_group1_mask; |
| 531 | u8 func_group2_mask; |
| 532 | u8 func_group3_mask; |
| 533 | u8 func_group4_mask; |
| 534 | |
| 535 | u8 sd_switch_fail; |
| 536 | u8 sd_read_phase; |
| 537 | u8 retry_SD20_mode; /* sangdy2010-06-10 */ |
| 538 | u8 sd_reset_fail; /* sangdy2010-07-01 */ |
| 539 | u8 sd_send_status_en; |
| 540 | |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 541 | }; |
| 542 | |
| 543 | #define MODE_512_SEQ 0x01 |
| 544 | #define MODE_2K_SEQ 0x02 |
| 545 | |
| 546 | #define TYPE_MS 0x0000 |
| 547 | #define TYPE_MSPRO 0x0001 |
| 548 | |
| 549 | #define MS_4BIT 0x0100 |
| 550 | #define MS_8BIT 0x0200 |
| 551 | #define MS_HG 0x0400 |
| 552 | #define MS_XC 0x0800 |
| 553 | |
| 554 | #define HG8BIT (MS_HG | MS_8BIT) |
| 555 | |
| 556 | #define CHK_MSPRO(ms_card) \ |
| 557 | (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO) |
| 558 | #define CHK_HG8BIT(ms_card) \ |
| 559 | (CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT)) |
| 560 | #define CHK_MSXC(ms_card) \ |
| 561 | (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC)) |
| 562 | #define CHK_MSHG(ms_card) \ |
| 563 | (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG)) |
| 564 | |
| 565 | #define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT)) |
| 566 | #define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT)) |
| 567 | |
| 568 | struct ms_delay_write_tag { |
| 569 | u16 old_phyblock; |
| 570 | u16 new_phyblock; |
| 571 | u16 logblock; |
| 572 | u8 pageoff; |
| 573 | u8 delay_write_flag; |
| 574 | }; |
| 575 | |
| 576 | struct ms_info { |
| 577 | u16 ms_type; |
| 578 | u8 block_shift; |
| 579 | u8 page_off; |
| 580 | u16 total_block; |
| 581 | u16 boot_block; |
| 582 | u32 capacity; |
| 583 | |
| 584 | u8 check_ms_flow; |
| 585 | u8 switch_8bit_fail; |
| 586 | u8 err_code; |
| 587 | |
| 588 | struct zone_entry *segment; |
| 589 | int segment_cnt; |
| 590 | |
| 591 | int pro_under_formatting; |
| 592 | int format_status; |
| 593 | u16 progress; |
| 594 | u8 raw_sys_info[96]; |
| 595 | #ifdef SUPPORT_PCGL_1P18 |
| 596 | u8 raw_model_name[48]; |
| 597 | #endif |
| 598 | |
| 599 | u8 multi_flag; |
| 600 | |
| 601 | /* Sequential RW */ |
| 602 | u8 seq_mode; |
| 603 | enum dma_data_direction pre_dir; |
| 604 | u32 pre_sec_addr; |
| 605 | u16 pre_sec_cnt; |
| 606 | u32 total_sec_cnt; |
| 607 | u8 last_rw_int; |
| 608 | |
| 609 | struct ms_delay_write_tag delay_write; |
| 610 | |
| 611 | int counter; |
| 612 | |
| 613 | int ms_clock; |
| 614 | |
| 615 | #ifdef SUPPORT_MAGIC_GATE |
| 616 | u8 magic_gate_id[16]; |
| 617 | u8 mg_entry_num; |
| 618 | int mg_auth; /* flag to indicate authentication process */ |
| 619 | #endif |
| 620 | }; |
| 621 | |
| 622 | #define PRO_UNDER_FORMATTING(ms_card) \ |
| 623 | ((ms_card)->pro_under_formatting) |
| 624 | #define SET_FORMAT_STATUS(ms_card, status) \ |
| 625 | ((ms_card)->format_status = (status)) |
| 626 | #define CHK_FORMAT_STATUS(ms_card, status) \ |
| 627 | ((ms_card)->format_status == (status)) |
| 628 | |
| 629 | struct scsi_cmnd; |
| 630 | |
| 631 | enum CHIP_STAT { STAT_INIT, STAT_IDLE, STAT_RUN, STAT_SS_PRE, STAT_SS, |
| 632 | STAT_SUSPEND }; |
| 633 | |
| 634 | struct rts51x_chip { |
| 635 | u16 vendor_id; |
| 636 | u16 product_id; |
| 637 | char max_lun; |
| 638 | |
| 639 | struct scsi_cmnd *srb; |
| 640 | struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT]; |
| 641 | |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 642 | int led_toggle_counter; |
Oleksij Rempel | 3d2b3aa | 2012-05-04 17:14:29 +0200 | [diff] [blame] | 643 | |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 644 | int ss_counter; |
| 645 | int idle_counter; |
| 646 | int auto_delink_counter; |
| 647 | enum CHIP_STAT chip_stat; |
| 648 | |
| 649 | int resume_from_scsi; |
| 650 | |
| 651 | /* Card information */ |
| 652 | struct xd_info xd_card; |
| 653 | struct sd_info sd_card; |
| 654 | struct ms_info ms_card; |
| 655 | |
| 656 | int cur_clk; /* current card clock */ |
| 657 | int cur_card; /* Current card module */ |
| 658 | |
| 659 | u8 card_exist; /* card exist bit map (physical exist) */ |
| 660 | u8 card_ready; /* card ready bit map (reset successfully) */ |
| 661 | u8 card_fail; /* card reset fail bit map */ |
| 662 | u8 card_ejected; /* card ejected bit map */ |
| 663 | u8 card_wp; /* card write protected bit map */ |
| 664 | |
| 665 | u8 fake_card_ready; |
| 666 | /* flag to indicate whether to answer MediaChange */ |
| 667 | unsigned long lun_mc; |
| 668 | |
| 669 | /* card bus width */ |
| 670 | u8 card_bus_width[MAX_ALLOWED_LUN_CNT]; |
| 671 | /* card capacity */ |
| 672 | u32 capacity[MAX_ALLOWED_LUN_CNT]; |
| 673 | |
| 674 | /* read/write card function pointer */ |
| 675 | card_rw_func rw_card[MAX_ALLOWED_LUN_CNT]; |
| 676 | /* read/write capacity, used for GPIO Toggle */ |
| 677 | u32 rw_cap[MAX_ALLOWED_LUN_CNT]; |
| 678 | /* card to lun mapping table */ |
| 679 | u8 card2lun[32]; |
| 680 | /* lun to card mapping table */ |
| 681 | u8 lun2card[MAX_ALLOWED_LUN_CNT]; |
| 682 | |
| 683 | #ifdef _MSG_TRACE |
| 684 | struct trace_msg_t trace_msg[TRACE_ITEM_CNT]; |
| 685 | int msg_idx; |
| 686 | #endif |
| 687 | |
| 688 | int rw_need_retry; |
| 689 | |
| 690 | /* ASIC or FPGA */ |
| 691 | int asic_code; |
| 692 | |
| 693 | /* QFN24 or LQFP48 */ |
| 694 | int package; |
| 695 | |
| 696 | /* Full Speed or High Speed */ |
| 697 | int usb_speed; |
| 698 | |
| 699 | /*sangdy:enable or disable UHS50 and MMC4.4 */ |
| 700 | int uhs50_mmc44_en; |
| 701 | |
| 702 | u8 ic_version; |
| 703 | |
| 704 | /* Command buffer */ |
| 705 | u8 *cmd_buf; |
| 706 | unsigned int cmd_idx; |
| 707 | /* Response buffer */ |
| 708 | u8 *rsp_buf; |
| 709 | |
| 710 | u16 card_status; |
| 711 | |
| 712 | #ifdef SUPPORT_OCP |
| 713 | u16 ocp_stat; |
| 714 | #endif |
| 715 | |
| 716 | struct rts51x_option option; |
| 717 | struct rts51x_usb *usb; |
| 718 | |
| 719 | u8 rcc_read_response; |
| 720 | int reset_need_retry; |
| 721 | u8 rts5179; |
| 722 | }; |
| 723 | |
| 724 | #define UHS50_EN 0x0001 |
| 725 | #define UHS50_DIS 0x0000 |
| 726 | #define SET_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_EN) |
| 727 | #define CLEAR_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_DIS) |
| 728 | #define CHECK_UHS50(chip) (((chip)->uhs50_mmc44_en&0xff) == UHS50_EN) |
| 729 | |
| 730 | #define RTS51X_GET_VID(chip) ((chip)->vendor_id) |
| 731 | #define RTS51X_GET_PID(chip) ((chip)->product_id) |
| 732 | |
| 733 | #define RTS51X_SET_STAT(chip, stat) \ |
| 734 | do { \ |
| 735 | if ((stat) != STAT_IDLE) { \ |
| 736 | (chip)->idle_counter = 0; \ |
| 737 | } \ |
| 738 | (chip)->chip_stat = (enum CHIP_STAT)(stat); \ |
| 739 | } while (0) |
| 740 | #define RTS51X_CHK_STAT(chip, stat) ((chip)->chip_stat == (stat)) |
| 741 | #define RTS51X_GET_STAT(chip) ((chip)->chip_stat) |
| 742 | |
| 743 | #define CHECK_PID(chip, pid) (RTS51X_GET_PID(chip) == (pid)) |
| 744 | #define CHECK_PKG(chip, pkg) ((chip)->package == (pkg)) |
| 745 | #define CHECK_USB(chip, speed) ((chip)->usb_speed == (speed)) |
| 746 | |
| 747 | int rts51x_reset_chip(struct rts51x_chip *chip); |
| 748 | int rts51x_init_chip(struct rts51x_chip *chip); |
| 749 | int rts51x_release_chip(struct rts51x_chip *chip); |
| 750 | void rts51x_polling_func(struct rts51x_chip *chip); |
| 751 | |
| 752 | static inline void rts51x_init_cmd(struct rts51x_chip *chip) |
| 753 | { |
| 754 | chip->cmd_idx = 0; |
| 755 | chip->cmd_buf[0] = 'R'; |
| 756 | chip->cmd_buf[1] = 'T'; |
| 757 | chip->cmd_buf[2] = 'C'; |
| 758 | chip->cmd_buf[3] = 'R'; |
| 759 | chip->cmd_buf[PACKET_TYPE] = BATCH_CMD; |
| 760 | } |
| 761 | |
| 762 | void rts51x_add_cmd(struct rts51x_chip *chip, |
| 763 | u8 cmd_type, u16 reg_addr, u8 mask, u8 data); |
| 764 | int rts51x_send_cmd(struct rts51x_chip *chip, u8 flag, int timeout); |
| 765 | int rts51x_get_rsp(struct rts51x_chip *chip, int rsp_len, int timeout); |
| 766 | |
| 767 | static inline void rts51x_read_rsp_buf(struct rts51x_chip *chip, int offset, |
| 768 | u8 *buf, int buf_len) |
| 769 | { |
| 770 | memcpy(buf, chip->rsp_buf + offset, buf_len); |
| 771 | } |
| 772 | |
| 773 | static inline u8 *rts51x_get_rsp_data(struct rts51x_chip *chip) |
| 774 | { |
| 775 | return chip->rsp_buf; |
| 776 | } |
| 777 | |
Márton Németh | aa2f92a | 2012-01-22 22:47:15 +0100 | [diff] [blame] | 778 | int rts51x_get_card_status(struct rts51x_chip *chip, u16 *status); |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 779 | int rts51x_write_register(struct rts51x_chip *chip, u16 addr, u8 mask, u8 data); |
Márton Németh | aa2f92a | 2012-01-22 22:47:15 +0100 | [diff] [blame] | 780 | int rts51x_read_register(struct rts51x_chip *chip, u16 addr, u8 *data); |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 781 | int rts51x_ep0_write_register(struct rts51x_chip *chip, u16 addr, u8 mask, |
| 782 | u8 data); |
Márton Németh | aa2f92a | 2012-01-22 22:47:15 +0100 | [diff] [blame] | 783 | int rts51x_ep0_read_register(struct rts51x_chip *chip, u16 addr, u8 *data); |
edwin_rong | 1dac418 | 2011-07-19 17:10:35 +0800 | [diff] [blame] | 784 | int rts51x_seq_write_register(struct rts51x_chip *chip, u16 addr, u16 len, |
| 785 | u8 *data); |
| 786 | int rts51x_seq_read_register(struct rts51x_chip *chip, u16 addr, u16 len, |
| 787 | u8 *data); |
| 788 | int rts51x_read_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len); |
| 789 | int rts51x_write_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len); |
| 790 | int rts51x_write_phy_register(struct rts51x_chip *chip, u8 addr, u8 val); |
| 791 | int rts51x_read_phy_register(struct rts51x_chip *chip, u8 addr, u8 *val); |
| 792 | void rts51x_do_before_power_down(struct rts51x_chip *chip); |
| 793 | void rts51x_clear_hw_error(struct rts51x_chip *chip); |
| 794 | void rts51x_prepare_run(struct rts51x_chip *chip); |
| 795 | void rts51x_trace_msg(struct rts51x_chip *chip, unsigned char *buf, int clear); |
| 796 | void rts51x_pp_status(struct rts51x_chip *chip, unsigned int lun, u8 *status, |
| 797 | u8 status_len); |
| 798 | void rts51x_read_status(struct rts51x_chip *chip, unsigned int lun, |
| 799 | u8 *rts51x_status, u8 status_len); |
| 800 | int rts51x_transfer_data_rcc(struct rts51x_chip *chip, unsigned int pipe, |
| 801 | void *buf, unsigned int len, int use_sg, |
| 802 | unsigned int *act_len, int timeout, u8 stage_flag); |
| 803 | |
| 804 | #define RTS51X_WRITE_REG(chip, addr, mask, data) \ |
| 805 | do { \ |
| 806 | int _retval = rts51x_write_register((chip), \ |
| 807 | (addr), (mask), (data)); \ |
| 808 | if (_retval != STATUS_SUCCESS) { \ |
| 809 | TRACE_RET((chip), _retval); \ |
| 810 | } \ |
| 811 | } while (0) |
| 812 | |
| 813 | #define RTS51X_READ_REG(chip, addr, data) \ |
| 814 | do { \ |
| 815 | int _retval = rts51x_read_register((chip), \ |
| 816 | (addr), (data)); \ |
| 817 | if (_retval != STATUS_SUCCESS) { \ |
| 818 | TRACE_RET((chip), _retval); \ |
| 819 | } \ |
| 820 | } while (0) |
| 821 | |
| 822 | #endif /* __RTS51X_CHIP_H */ |