| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * SNI specific definitions |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU General Public |
| 5 | * License. See the file "COPYING" in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Copyright (C) 1997, 1998 by Ralf Baechle |
| 9 | */ |
| 10 | #ifndef __ASM_SNI_H |
| 11 | #define __ASM_SNI_H |
| 12 | |
| 13 | #define SNI_PORT_BASE 0xb4000000 |
| 14 | |
| 15 | /* |
| 16 | * ASIC PCI registers for little endian configuration. |
| 17 | */ |
| 18 | #ifndef __MIPSEL__ |
| 19 | #error "Fix me for big endian" |
| 20 | #endif |
| 21 | #define PCIMT_UCONF 0xbfff0000 |
| 22 | #define PCIMT_IOADTIMEOUT2 0xbfff0008 |
| 23 | #define PCIMT_IOMEMCONF 0xbfff0010 |
| 24 | #define PCIMT_IOMMU 0xbfff0018 |
| 25 | #define PCIMT_IOADTIMEOUT1 0xbfff0020 |
| 26 | #define PCIMT_DMAACCESS 0xbfff0028 |
| 27 | #define PCIMT_DMAHIT 0xbfff0030 |
| 28 | #define PCIMT_ERRSTATUS 0xbfff0038 |
| 29 | #define PCIMT_ERRADDR 0xbfff0040 |
| 30 | #define PCIMT_SYNDROME 0xbfff0048 |
| 31 | #define PCIMT_ITPEND 0xbfff0050 |
| 32 | #define IT_INT2 0x01 |
| 33 | #define IT_INTD 0x02 |
| 34 | #define IT_INTC 0x04 |
| 35 | #define IT_INTB 0x08 |
| 36 | #define IT_INTA 0x10 |
| 37 | #define IT_EISA 0x20 |
| 38 | #define IT_SCSI 0x40 |
| 39 | #define IT_ETH 0x80 |
| 40 | #define PCIMT_IRQSEL 0xbfff0058 |
| 41 | #define PCIMT_TESTMEM 0xbfff0060 |
| 42 | #define PCIMT_ECCREG 0xbfff0068 |
| 43 | #define PCIMT_CONFIG_ADDRESS 0xbfff0070 |
| 44 | #define PCIMT_ASIC_ID 0xbfff0078 /* read */ |
| 45 | #define PCIMT_SOFT_RESET 0xbfff0078 /* write */ |
| 46 | #define PCIMT_PIA_OE 0xbfff0080 |
| 47 | #define PCIMT_PIA_DATAOUT 0xbfff0088 |
| 48 | #define PCIMT_PIA_DATAIN 0xbfff0090 |
| 49 | #define PCIMT_CACHECONF 0xbfff0098 |
| 50 | #define PCIMT_INVSPACE 0xbfff00a0 |
| 51 | #define PCIMT_PCI_CONF 0xbfff0100 |
| 52 | |
| 53 | /* |
| 54 | * Data port for the PCI bus. |
| 55 | */ |
| 56 | #define PCIMT_CONFIG_DATA 0xb4000cfc |
| 57 | |
| 58 | /* |
| 59 | * Board specific registers |
| 60 | */ |
| 61 | #define PCIMT_CSMSR 0xbfd00000 |
| 62 | #define PCIMT_CSSWITCH 0xbfd10000 |
| 63 | #define PCIMT_CSITPEND 0xbfd20000 |
| 64 | #define PCIMT_AUTO_PO_EN 0xbfd30000 |
| 65 | #define PCIMT_CLR_TEMP 0xbfd40000 |
| 66 | #define PCIMT_AUTO_PO_DIS 0xbfd50000 |
| 67 | #define PCIMT_EXMSR 0xbfd60000 |
| 68 | #define PCIMT_UNUSED1 0xbfd70000 |
| 69 | #define PCIMT_CSWCSM 0xbfd80000 |
| 70 | #define PCIMT_UNUSED2 0xbfd90000 |
| 71 | #define PCIMT_CSLED 0xbfda0000 |
| 72 | #define PCIMT_CSMAPISA 0xbfdb0000 |
| 73 | #define PCIMT_CSRSTBP 0xbfdc0000 |
| 74 | #define PCIMT_CLRPOFF 0xbfdd0000 |
| 75 | #define PCIMT_CSTIMER 0xbfde0000 |
| 76 | #define PCIMT_PWDN 0xbfdf0000 |
| 77 | |
| 78 | /* |
| 79 | * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned |
| 80 | * to the other interrupts generated by ASIC PCI. |
| 81 | * |
| 82 | * INT2 is a wired-or of the push button interrupt, high temperature interrupt |
| 83 | * ASIC PCI interrupt. |
| 84 | */ |
| 85 | #define PCIMT_KEYBOARD_IRQ 1 |
| 86 | #define PCIMT_IRQ_INT2 16 |
| 87 | #define PCIMT_IRQ_INTD 17 |
| 88 | #define PCIMT_IRQ_INTC 18 |
| 89 | #define PCIMT_IRQ_INTB 19 |
| 90 | #define PCIMT_IRQ_INTA 20 |
| 91 | #define PCIMT_IRQ_EISA 21 |
| 92 | #define PCIMT_IRQ_SCSI 22 |
| 93 | #define PCIMT_IRQ_ETHERNET 23 |
| 94 | #define PCIMT_IRQ_TEMPERATURE 24 |
| 95 | #define PCIMT_IRQ_EISA_NMI 25 |
| 96 | #define PCIMT_IRQ_POWER_OFF 26 |
| 97 | #define PCIMT_IRQ_BUTTON 27 |
| 98 | |
| 99 | /* |
| 100 | * Base address for the mapped 16mb EISA bus segment. |
| 101 | */ |
| 102 | #define PCIMT_EISA_BASE 0xb0000000 |
| 103 | |
| 104 | /* PCI EISA Interrupt acknowledge */ |
| 105 | #define PCIMT_INT_ACKNOWLEDGE 0xba000000 |
| 106 | |
| 107 | #endif /* __ASM_SNI_H */ |