Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 1 | /* |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 2 | * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "mdp5_kms.h" |
| 20 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 21 | struct mdp5_plane { |
| 22 | struct drm_plane base; |
| 23 | const char *name; |
| 24 | |
| 25 | enum mdp5_pipe pipe; |
| 26 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 27 | spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */ |
| 28 | uint32_t reg_offset; |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 29 | uint32_t caps; |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 30 | |
| 31 | uint32_t flush_mask; /* used to commit pipe registers */ |
| 32 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 33 | uint32_t nformats; |
| 34 | uint32_t formats[32]; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 35 | }; |
| 36 | #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) |
| 37 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 38 | static int mdp5_plane_mode_set(struct drm_plane *plane, |
| 39 | struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 40 | int crtc_x, int crtc_y, |
| 41 | unsigned int crtc_w, unsigned int crtc_h, |
| 42 | uint32_t src_x, uint32_t src_y, |
| 43 | uint32_t src_w, uint32_t src_h); |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 44 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 45 | static void set_scanout_locked(struct drm_plane *plane, |
| 46 | struct drm_framebuffer *fb); |
| 47 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 48 | static struct mdp5_kms *get_kms(struct drm_plane *plane) |
| 49 | { |
| 50 | struct msm_drm_private *priv = plane->dev->dev_private; |
| 51 | return to_mdp5_kms(to_mdp_kms(priv->kms)); |
| 52 | } |
| 53 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 54 | static bool plane_enabled(struct drm_plane_state *state) |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 55 | { |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 56 | return state->fb && state->crtc; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 57 | } |
| 58 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 59 | static void mdp5_plane_destroy(struct drm_plane *plane) |
| 60 | { |
| 61 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 62 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 63 | drm_plane_helper_disable(plane); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 64 | drm_plane_cleanup(plane); |
| 65 | |
| 66 | kfree(mdp5_plane); |
| 67 | } |
| 68 | |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 69 | static void mdp5_plane_install_rotation_property(struct drm_device *dev, |
| 70 | struct drm_plane *plane) |
| 71 | { |
| 72 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 73 | |
| 74 | if (!(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP) && |
| 75 | !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) |
| 76 | return; |
| 77 | |
| 78 | if (!dev->mode_config.rotation_property) |
| 79 | dev->mode_config.rotation_property = |
| 80 | drm_mode_create_rotation_property(dev, |
Ville Syrjälä | 1d42a3f | 2016-07-22 16:43:09 +0300 | [diff] [blame] | 81 | DRM_ROTATE_0 | DRM_REFLECT_X | DRM_REFLECT_Y); |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 82 | |
| 83 | if (dev->mode_config.rotation_property) |
| 84 | drm_object_attach_property(&plane->base, |
| 85 | dev->mode_config.rotation_property, |
Ville Syrjälä | 1d42a3f | 2016-07-22 16:43:09 +0300 | [diff] [blame] | 86 | DRM_ROTATE_0); |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 87 | } |
| 88 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 89 | /* helper to install properties which are common to planes and crtcs */ |
Rob Clark | 4ff696e | 2015-07-28 11:05:03 -0400 | [diff] [blame] | 90 | static void mdp5_plane_install_properties(struct drm_plane *plane, |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 91 | struct drm_mode_object *obj) |
| 92 | { |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 93 | struct drm_device *dev = plane->dev; |
| 94 | struct msm_drm_private *dev_priv = dev->dev_private; |
| 95 | struct drm_property *prop; |
| 96 | |
| 97 | #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \ |
| 98 | prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \ |
| 99 | if (!prop) { \ |
| 100 | prop = drm_property_##fnc(dev, 0, #name, \ |
| 101 | ##__VA_ARGS__); \ |
| 102 | if (!prop) { \ |
| 103 | dev_warn(dev->dev, \ |
| 104 | "Create property %s failed\n", \ |
| 105 | #name); \ |
| 106 | return; \ |
| 107 | } \ |
| 108 | dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \ |
| 109 | } \ |
| 110 | drm_object_attach_property(&plane->base, prop, init_val); \ |
| 111 | } while (0) |
| 112 | |
| 113 | #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \ |
| 114 | INSTALL_PROPERTY(name, NAME, init_val, \ |
| 115 | create_range, min, max) |
| 116 | |
| 117 | #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \ |
| 118 | INSTALL_PROPERTY(name, NAME, init_val, \ |
| 119 | create_enum, name##_prop_enum_list, \ |
| 120 | ARRAY_SIZE(name##_prop_enum_list)) |
| 121 | |
| 122 | INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1); |
| 123 | |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 124 | mdp5_plane_install_rotation_property(dev, plane); |
| 125 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 126 | #undef INSTALL_RANGE_PROPERTY |
| 127 | #undef INSTALL_ENUM_PROPERTY |
| 128 | #undef INSTALL_PROPERTY |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 129 | } |
| 130 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 131 | static int mdp5_plane_atomic_set_property(struct drm_plane *plane, |
| 132 | struct drm_plane_state *state, struct drm_property *property, |
| 133 | uint64_t val) |
| 134 | { |
| 135 | struct drm_device *dev = plane->dev; |
| 136 | struct mdp5_plane_state *pstate; |
| 137 | struct msm_drm_private *dev_priv = dev->dev_private; |
| 138 | int ret = 0; |
| 139 | |
| 140 | pstate = to_mdp5_plane_state(state); |
| 141 | |
| 142 | #define SET_PROPERTY(name, NAME, type) do { \ |
| 143 | if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ |
| 144 | pstate->name = (type)val; \ |
| 145 | DBG("Set property %s %d", #name, (type)val); \ |
| 146 | goto done; \ |
| 147 | } \ |
| 148 | } while (0) |
| 149 | |
| 150 | SET_PROPERTY(zpos, ZPOS, uint8_t); |
| 151 | |
| 152 | dev_err(dev->dev, "Invalid property\n"); |
| 153 | ret = -EINVAL; |
| 154 | done: |
| 155 | return ret; |
| 156 | #undef SET_PROPERTY |
| 157 | } |
| 158 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 159 | static int mdp5_plane_atomic_get_property(struct drm_plane *plane, |
| 160 | const struct drm_plane_state *state, |
| 161 | struct drm_property *property, uint64_t *val) |
| 162 | { |
| 163 | struct drm_device *dev = plane->dev; |
| 164 | struct mdp5_plane_state *pstate; |
| 165 | struct msm_drm_private *dev_priv = dev->dev_private; |
| 166 | int ret = 0; |
| 167 | |
| 168 | pstate = to_mdp5_plane_state(state); |
| 169 | |
| 170 | #define GET_PROPERTY(name, NAME, type) do { \ |
| 171 | if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ |
| 172 | *val = pstate->name; \ |
| 173 | DBG("Get property %s %lld", #name, *val); \ |
| 174 | goto done; \ |
| 175 | } \ |
| 176 | } while (0) |
| 177 | |
| 178 | GET_PROPERTY(zpos, ZPOS, uint8_t); |
| 179 | |
| 180 | dev_err(dev->dev, "Invalid property\n"); |
| 181 | ret = -EINVAL; |
| 182 | done: |
| 183 | return ret; |
| 184 | #undef SET_PROPERTY |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 185 | } |
| 186 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 187 | static void mdp5_plane_reset(struct drm_plane *plane) |
| 188 | { |
| 189 | struct mdp5_plane_state *mdp5_state; |
| 190 | |
| 191 | if (plane->state && plane->state->fb) |
| 192 | drm_framebuffer_unreference(plane->state->fb); |
| 193 | |
| 194 | kfree(to_mdp5_plane_state(plane->state)); |
| 195 | mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); |
| 196 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 197 | /* assign default blend parameters */ |
| 198 | mdp5_state->alpha = 255; |
| 199 | mdp5_state->premultiplied = 0; |
| 200 | |
| 201 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
| 202 | mdp5_state->zpos = STAGE_BASE; |
| 203 | else |
| 204 | mdp5_state->zpos = STAGE0 + drm_plane_index(plane); |
| 205 | |
Daniel Vetter | 07cc0ef | 2014-11-27 15:49:39 +0100 | [diff] [blame] | 206 | mdp5_state->base.plane = plane; |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 207 | |
| 208 | plane->state = &mdp5_state->base; |
| 209 | } |
| 210 | |
| 211 | static struct drm_plane_state * |
| 212 | mdp5_plane_duplicate_state(struct drm_plane *plane) |
| 213 | { |
| 214 | struct mdp5_plane_state *mdp5_state; |
| 215 | |
| 216 | if (WARN_ON(!plane->state)) |
| 217 | return NULL; |
| 218 | |
| 219 | mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), |
| 220 | sizeof(*mdp5_state), GFP_KERNEL); |
Rob Clark | 7eed46b1 | 2017-05-03 10:04:48 -0400 | [diff] [blame] | 221 | if (!mdp5_state) |
| 222 | return NULL; |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 223 | |
Rob Clark | 7eed46b1 | 2017-05-03 10:04:48 -0400 | [diff] [blame] | 224 | __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 225 | |
| 226 | mdp5_state->mode_changed = false; |
| 227 | mdp5_state->pending = false; |
| 228 | |
| 229 | return &mdp5_state->base; |
| 230 | } |
| 231 | |
| 232 | static void mdp5_plane_destroy_state(struct drm_plane *plane, |
| 233 | struct drm_plane_state *state) |
| 234 | { |
| 235 | if (state->fb) |
| 236 | drm_framebuffer_unreference(state->fb); |
| 237 | |
| 238 | kfree(to_mdp5_plane_state(state)); |
| 239 | } |
| 240 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 241 | static const struct drm_plane_funcs mdp5_plane_funcs = { |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 242 | .update_plane = drm_atomic_helper_update_plane, |
| 243 | .disable_plane = drm_atomic_helper_disable_plane, |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 244 | .destroy = mdp5_plane_destroy, |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 245 | .set_property = drm_atomic_helper_plane_set_property, |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 246 | .atomic_set_property = mdp5_plane_atomic_set_property, |
| 247 | .atomic_get_property = mdp5_plane_atomic_get_property, |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 248 | .reset = mdp5_plane_reset, |
| 249 | .atomic_duplicate_state = mdp5_plane_duplicate_state, |
| 250 | .atomic_destroy_state = mdp5_plane_destroy_state, |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 251 | }; |
| 252 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 253 | static int mdp5_plane_prepare_fb(struct drm_plane *plane, |
Chris Wilson | 1832040 | 2016-08-18 19:00:16 +0100 | [diff] [blame] | 254 | struct drm_plane_state *new_state) |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 255 | { |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 256 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 257 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
Maarten Lankhorst | 844f911 | 2015-09-02 10:42:40 +0200 | [diff] [blame] | 258 | struct drm_framebuffer *fb = new_state->fb; |
| 259 | |
| 260 | if (!new_state->fb) |
| 261 | return 0; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 262 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 263 | DBG("%s: prepare: FB[%u]", mdp5_plane->name, fb->base.id); |
| 264 | return msm_framebuffer_prepare(fb, mdp5_kms->id); |
| 265 | } |
| 266 | |
| 267 | static void mdp5_plane_cleanup_fb(struct drm_plane *plane, |
Chris Wilson | 1832040 | 2016-08-18 19:00:16 +0100 | [diff] [blame] | 268 | struct drm_plane_state *old_state) |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 269 | { |
| 270 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 271 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
Maarten Lankhorst | 844f911 | 2015-09-02 10:42:40 +0200 | [diff] [blame] | 272 | struct drm_framebuffer *fb = old_state->fb; |
| 273 | |
| 274 | if (!fb) |
| 275 | return; |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 276 | |
| 277 | DBG("%s: cleanup: FB[%u]", mdp5_plane->name, fb->base.id); |
| 278 | msm_framebuffer_cleanup(fb, mdp5_kms->id); |
| 279 | } |
| 280 | |
| 281 | static int mdp5_plane_atomic_check(struct drm_plane *plane, |
| 282 | struct drm_plane_state *state) |
| 283 | { |
| 284 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 285 | struct drm_plane_state *old_state = plane->state; |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 286 | const struct mdp_format *format; |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 287 | bool vflip, hflip; |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 288 | |
| 289 | DBG("%s: check (%d -> %d)", mdp5_plane->name, |
| 290 | plane_enabled(old_state), plane_enabled(state)); |
| 291 | |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 292 | if (plane_enabled(state)) { |
| 293 | format = to_mdp_format(msm_framebuffer_format(state->fb)); |
| 294 | if (MDP_FORMAT_IS_YUV(format) && |
| 295 | !pipe_supports_yuv(mdp5_plane->caps)) { |
Rob Clark | 07cd2e3 | 2016-10-17 12:00:21 -0400 | [diff] [blame] | 296 | DBG("Pipe doesn't support YUV\n"); |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 297 | |
| 298 | return -EINVAL; |
| 299 | } |
| 300 | |
| 301 | if (!(mdp5_plane->caps & MDP_PIPE_CAP_SCALE) && |
| 302 | (((state->src_w >> 16) != state->crtc_w) || |
| 303 | ((state->src_h >> 16) != state->crtc_h))) { |
Rob Clark | 07cd2e3 | 2016-10-17 12:00:21 -0400 | [diff] [blame] | 304 | DBG("Pipe doesn't support scaling (%dx%d -> %dx%d)\n", |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 305 | state->src_w >> 16, state->src_h >> 16, |
| 306 | state->crtc_w, state->crtc_h); |
| 307 | |
| 308 | return -EINVAL; |
| 309 | } |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 310 | |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 311 | hflip = !!(state->rotation & DRM_REFLECT_X); |
| 312 | vflip = !!(state->rotation & DRM_REFLECT_Y); |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 313 | if ((vflip && !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) || |
| 314 | (hflip && !(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP))) { |
Rob Clark | 07cd2e3 | 2016-10-17 12:00:21 -0400 | [diff] [blame] | 315 | DBG("Pipe doesn't support flip\n"); |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 316 | |
| 317 | return -EINVAL; |
| 318 | } |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 319 | } |
| 320 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 321 | if (plane_enabled(state) && plane_enabled(old_state)) { |
| 322 | /* we cannot change SMP block configuration during scanout: */ |
| 323 | bool full_modeset = false; |
| 324 | if (state->fb->pixel_format != old_state->fb->pixel_format) { |
| 325 | DBG("%s: pixel_format change!", mdp5_plane->name); |
| 326 | full_modeset = true; |
| 327 | } |
| 328 | if (state->src_w != old_state->src_w) { |
| 329 | DBG("%s: src_w change!", mdp5_plane->name); |
| 330 | full_modeset = true; |
| 331 | } |
| 332 | if (to_mdp5_plane_state(old_state)->pending) { |
| 333 | DBG("%s: still pending!", mdp5_plane->name); |
| 334 | full_modeset = true; |
| 335 | } |
| 336 | if (full_modeset) { |
| 337 | struct drm_crtc_state *crtc_state = |
| 338 | drm_atomic_get_crtc_state(state->state, state->crtc); |
| 339 | crtc_state->mode_changed = true; |
| 340 | to_mdp5_plane_state(state)->mode_changed = true; |
| 341 | } |
| 342 | } else { |
| 343 | to_mdp5_plane_state(state)->mode_changed = true; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 344 | } |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 345 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 346 | return 0; |
| 347 | } |
| 348 | |
Thierry Reding | f1c37e1 | 2014-11-25 12:09:44 +0100 | [diff] [blame] | 349 | static void mdp5_plane_atomic_update(struct drm_plane *plane, |
| 350 | struct drm_plane_state *old_state) |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 351 | { |
| 352 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 353 | struct drm_plane_state *state = plane->state; |
| 354 | |
| 355 | DBG("%s: update", mdp5_plane->name); |
| 356 | |
| 357 | if (!plane_enabled(state)) { |
| 358 | to_mdp5_plane_state(state)->pending = true; |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 359 | } else if (to_mdp5_plane_state(state)->mode_changed) { |
| 360 | int ret; |
| 361 | to_mdp5_plane_state(state)->pending = true; |
| 362 | ret = mdp5_plane_mode_set(plane, |
| 363 | state->crtc, state->fb, |
| 364 | state->crtc_x, state->crtc_y, |
| 365 | state->crtc_w, state->crtc_h, |
| 366 | state->src_x, state->src_y, |
| 367 | state->src_w, state->src_h); |
| 368 | /* atomic_check should have ensured that this doesn't fail */ |
| 369 | WARN_ON(ret < 0); |
| 370 | } else { |
| 371 | unsigned long flags; |
| 372 | spin_lock_irqsave(&mdp5_plane->pipe_lock, flags); |
| 373 | set_scanout_locked(plane, state->fb); |
| 374 | spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { |
| 379 | .prepare_fb = mdp5_plane_prepare_fb, |
| 380 | .cleanup_fb = mdp5_plane_cleanup_fb, |
| 381 | .atomic_check = mdp5_plane_atomic_check, |
| 382 | .atomic_update = mdp5_plane_atomic_update, |
| 383 | }; |
| 384 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 385 | static void set_scanout_locked(struct drm_plane *plane, |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 386 | struct drm_framebuffer *fb) |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 387 | { |
| 388 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 389 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
| 390 | enum mdp5_pipe pipe = mdp5_plane->pipe; |
| 391 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 392 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 393 | MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | |
| 394 | MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 395 | |
| 396 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 397 | MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | |
| 398 | MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 399 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 400 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), |
| 401 | msm_framebuffer_iova(fb, mdp5_kms->id, 0)); |
| 402 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), |
| 403 | msm_framebuffer_iova(fb, mdp5_kms->id, 1)); |
| 404 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), |
| 405 | msm_framebuffer_iova(fb, mdp5_kms->id, 2)); |
| 406 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), |
Stephane Viau | 755c814 | 2015-05-20 10:57:27 -0400 | [diff] [blame] | 407 | msm_framebuffer_iova(fb, mdp5_kms->id, 3)); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 408 | |
| 409 | plane->fb = fb; |
| 410 | } |
| 411 | |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 412 | /* Note: mdp5_plane->pipe_lock must be locked */ |
| 413 | static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) |
| 414 | { |
| 415 | uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & |
| 416 | ~MDP5_PIPE_OP_MODE_CSC_1_EN; |
| 417 | |
| 418 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); |
| 419 | } |
| 420 | |
| 421 | /* Note: mdp5_plane->pipe_lock must be locked */ |
| 422 | static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, |
| 423 | struct csc_cfg *csc) |
| 424 | { |
| 425 | uint32_t i, mode = 0; /* RGB, no CSC */ |
| 426 | uint32_t *matrix; |
| 427 | |
| 428 | if (unlikely(!csc)) |
| 429 | return; |
| 430 | |
| 431 | if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) |
| 432 | mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); |
| 433 | if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) |
| 434 | mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); |
| 435 | mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; |
| 436 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); |
| 437 | |
| 438 | matrix = csc->matrix; |
| 439 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), |
| 440 | MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | |
| 441 | MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); |
| 442 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), |
| 443 | MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | |
| 444 | MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); |
| 445 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), |
| 446 | MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | |
| 447 | MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); |
| 448 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), |
| 449 | MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | |
| 450 | MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); |
| 451 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), |
| 452 | MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); |
| 453 | |
| 454 | for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { |
| 455 | uint32_t *pre_clamp = csc->pre_clamp; |
| 456 | uint32_t *post_clamp = csc->post_clamp; |
| 457 | |
| 458 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), |
| 459 | MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | |
| 460 | MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); |
| 461 | |
| 462 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), |
| 463 | MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | |
| 464 | MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); |
| 465 | |
| 466 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), |
| 467 | MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); |
| 468 | |
| 469 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), |
| 470 | MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | #define PHASE_STEP_SHIFT 21 |
| 475 | #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ |
| 476 | |
| 477 | static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) |
| 478 | { |
| 479 | uint32_t unit; |
| 480 | |
| 481 | if (src == 0 || dst == 0) |
| 482 | return -EINVAL; |
| 483 | |
| 484 | /* |
| 485 | * PHASE_STEP_X/Y is coded on 26 bits (25:0), |
| 486 | * where 2^21 represents the unity "1" in fixed-point hardware design. |
| 487 | * This leaves 5 bits for the integer part (downscale case): |
| 488 | * -> maximum downscale ratio = 0b1_1111 = 31 |
| 489 | */ |
| 490 | if (src > (dst * DOWN_SCALE_RATIO_MAX)) |
| 491 | return -EOVERFLOW; |
| 492 | |
| 493 | unit = 1 << PHASE_STEP_SHIFT; |
| 494 | *out_phase = mult_frac(unit, src, dst); |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 499 | static int calc_scalex_steps(struct drm_plane *plane, |
| 500 | uint32_t pixel_format, uint32_t src, uint32_t dest, |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 501 | uint32_t phasex_steps[COMP_MAX]) |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 502 | { |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 503 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
| 504 | struct device *dev = mdp5_kms->dev->dev; |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 505 | uint32_t phasex_step; |
| 506 | unsigned int hsub; |
| 507 | int ret; |
| 508 | |
| 509 | ret = calc_phase_step(src, dest, &phasex_step); |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 510 | if (ret) { |
| 511 | dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 512 | return ret; |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 513 | } |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 514 | |
| 515 | hsub = drm_format_horz_chroma_subsampling(pixel_format); |
| 516 | |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 517 | phasex_steps[COMP_0] = phasex_step; |
| 518 | phasex_steps[COMP_3] = phasex_step; |
| 519 | phasex_steps[COMP_1_2] = phasex_step / hsub; |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 520 | |
| 521 | return 0; |
| 522 | } |
| 523 | |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 524 | static int calc_scaley_steps(struct drm_plane *plane, |
| 525 | uint32_t pixel_format, uint32_t src, uint32_t dest, |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 526 | uint32_t phasey_steps[COMP_MAX]) |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 527 | { |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 528 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
| 529 | struct device *dev = mdp5_kms->dev->dev; |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 530 | uint32_t phasey_step; |
| 531 | unsigned int vsub; |
| 532 | int ret; |
| 533 | |
| 534 | ret = calc_phase_step(src, dest, &phasey_step); |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 535 | if (ret) { |
| 536 | dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 537 | return ret; |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 538 | } |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 539 | |
| 540 | vsub = drm_format_vert_chroma_subsampling(pixel_format); |
| 541 | |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 542 | phasey_steps[COMP_0] = phasey_step; |
| 543 | phasey_steps[COMP_3] = phasey_step; |
| 544 | phasey_steps[COMP_1_2] = phasey_step / vsub; |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 549 | static uint32_t get_scale_config(const struct mdp_format *format, |
| 550 | uint32_t src, uint32_t dst, bool horz) |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 551 | { |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 552 | bool scaling = format->is_yuv ? true : (src != dst); |
| 553 | uint32_t sub, pix_fmt = format->base.pixel_format; |
| 554 | uint32_t ya_filter, uv_filter; |
| 555 | bool yuv = format->is_yuv; |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 556 | |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 557 | if (!scaling) |
| 558 | return 0; |
| 559 | |
| 560 | if (yuv) { |
| 561 | sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) : |
| 562 | drm_format_vert_chroma_subsampling(pix_fmt); |
| 563 | uv_filter = ((src / sub) <= dst) ? |
| 564 | SCALE_FILTER_BIL : SCALE_FILTER_PCMN; |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 565 | } |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 566 | ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 567 | |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 568 | if (horz) |
| 569 | return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | |
| 570 | MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | |
| 571 | MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | |
| 572 | COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); |
| 573 | else |
| 574 | return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | |
| 575 | MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | |
| 576 | MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | |
| 577 | COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 578 | } |
| 579 | |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 580 | static void calc_pixel_ext(const struct mdp_format *format, |
| 581 | uint32_t src, uint32_t dst, uint32_t phase_step[2], |
| 582 | int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], |
| 583 | bool horz) |
| 584 | { |
| 585 | bool scaling = format->is_yuv ? true : (src != dst); |
| 586 | int i; |
| 587 | |
| 588 | /* |
| 589 | * Note: |
| 590 | * We assume here that: |
| 591 | * 1. PCMN filter is used for downscale |
| 592 | * 2. bilinear filter is used for upscale |
| 593 | * 3. we are in a single pipe configuration |
| 594 | */ |
| 595 | |
| 596 | for (i = 0; i < COMP_MAX; i++) { |
| 597 | pix_ext_edge1[i] = 0; |
| 598 | pix_ext_edge2[i] = scaling ? 1 : 0; |
| 599 | } |
| 600 | } |
| 601 | |
| 602 | static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, |
| 603 | const struct mdp_format *format, |
| 604 | uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], |
| 605 | uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) |
| 606 | { |
| 607 | uint32_t pix_fmt = format->base.pixel_format; |
| 608 | uint32_t lr, tb, req; |
| 609 | int i; |
| 610 | |
| 611 | for (i = 0; i < COMP_MAX; i++) { |
| 612 | uint32_t roi_w = src_w; |
| 613 | uint32_t roi_h = src_h; |
| 614 | |
| 615 | if (format->is_yuv && i == COMP_1_2) { |
| 616 | roi_w /= drm_format_horz_chroma_subsampling(pix_fmt); |
| 617 | roi_h /= drm_format_vert_chroma_subsampling(pix_fmt); |
| 618 | } |
| 619 | |
| 620 | lr = (pe_left[i] >= 0) ? |
| 621 | MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : |
| 622 | MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); |
| 623 | |
| 624 | lr |= (pe_right[i] >= 0) ? |
| 625 | MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : |
| 626 | MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); |
| 627 | |
| 628 | tb = (pe_top[i] >= 0) ? |
| 629 | MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : |
| 630 | MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); |
| 631 | |
| 632 | tb |= (pe_bottom[i] >= 0) ? |
| 633 | MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : |
| 634 | MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); |
| 635 | |
| 636 | req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + |
| 637 | pe_left[i] + pe_right[i]); |
| 638 | |
| 639 | req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + |
| 640 | pe_top[i] + pe_bottom[i]); |
| 641 | |
| 642 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); |
| 643 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); |
| 644 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); |
| 645 | |
| 646 | DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, |
| 647 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), |
| 648 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), |
| 649 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), |
| 650 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), |
| 651 | FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); |
| 652 | |
| 653 | DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, |
| 654 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), |
| 655 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), |
| 656 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), |
| 657 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), |
| 658 | FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 663 | static int mdp5_plane_mode_set(struct drm_plane *plane, |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 664 | struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 665 | int crtc_x, int crtc_y, |
| 666 | unsigned int crtc_w, unsigned int crtc_h, |
| 667 | uint32_t src_x, uint32_t src_y, |
| 668 | uint32_t src_w, uint32_t src_h) |
| 669 | { |
| 670 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 671 | struct drm_plane_state *pstate = plane->state; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 672 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
| 673 | enum mdp5_pipe pipe = mdp5_plane->pipe; |
| 674 | const struct mdp_format *format; |
| 675 | uint32_t nplanes, config = 0; |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 676 | uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,}; |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 677 | bool pe = mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT; |
| 678 | int pe_left[COMP_MAX], pe_right[COMP_MAX]; |
| 679 | int pe_top[COMP_MAX], pe_bottom[COMP_MAX]; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 680 | uint32_t hdecm = 0, vdecm = 0; |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 681 | uint32_t pix_format; |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 682 | bool vflip, hflip; |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 683 | unsigned long flags; |
Stephane Viau | bfcdfb0 | 2014-11-18 12:49:47 -0500 | [diff] [blame] | 684 | int ret; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 685 | |
| 686 | nplanes = drm_format_num_planes(fb->pixel_format); |
| 687 | |
| 688 | /* bad formats should already be rejected: */ |
| 689 | if (WARN_ON(nplanes > pipe2nclients(pipe))) |
| 690 | return -EINVAL; |
| 691 | |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 692 | format = to_mdp_format(msm_framebuffer_format(fb)); |
| 693 | pix_format = format->base.pixel_format; |
| 694 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 695 | /* src values are in Q16 fixed point, convert to integer: */ |
| 696 | src_x = src_x >> 16; |
| 697 | src_y = src_y >> 16; |
| 698 | src_w = src_w >> 16; |
| 699 | src_h = src_h >> 16; |
| 700 | |
| 701 | DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name, |
| 702 | fb->base.id, src_x, src_y, src_w, src_h, |
| 703 | crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); |
| 704 | |
Stephane Viau | bfcdfb0 | 2014-11-18 12:49:47 -0500 | [diff] [blame] | 705 | /* Request some memory from the SMP: */ |
Stephane Viau | d879eb5 | 2015-09-15 08:41:53 -0400 | [diff] [blame] | 706 | if (mdp5_kms->smp) { |
| 707 | ret = mdp5_smp_request(mdp5_kms->smp, |
| 708 | mdp5_plane->pipe, format, src_w, false); |
| 709 | if (ret) |
| 710 | return ret; |
| 711 | } |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 712 | |
| 713 | /* |
| 714 | * Currently we update the hw for allocations/requests immediately, |
| 715 | * but once atomic modeset/pageflip is in place, the allocation |
| 716 | * would move into atomic->check_plane_state(), while updating the |
| 717 | * hw would remain here: |
| 718 | */ |
Stephane Viau | d879eb5 | 2015-09-15 08:41:53 -0400 | [diff] [blame] | 719 | if (mdp5_kms->smp) |
| 720 | mdp5_smp_configure(mdp5_kms->smp, pipe); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 721 | |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 722 | ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step); |
| 723 | if (ret) |
| 724 | return ret; |
| 725 | |
| 726 | ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, phasey_step); |
| 727 | if (ret) |
| 728 | return ret; |
| 729 | |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 730 | if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) { |
| 731 | calc_pixel_ext(format, src_w, crtc_w, phasex_step, |
| 732 | pe_left, pe_right, true); |
| 733 | calc_pixel_ext(format, src_h, crtc_h, phasey_step, |
| 734 | pe_top, pe_bottom, false); |
| 735 | } |
| 736 | |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 737 | /* TODO calc hdecm, vdecm */ |
| 738 | |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 739 | /* SCALE is used to both scale and up-sample chroma components */ |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 740 | config |= get_scale_config(format, src_w, crtc_w, true); |
| 741 | config |= get_scale_config(format, src_h, crtc_h, false); |
Stephane Viau | bef799f | 2015-07-06 16:35:31 -0400 | [diff] [blame] | 742 | DBG("scale config = %x", config); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 743 | |
Joonas Lahtinen | 31ad61e | 2016-07-29 08:50:05 +0300 | [diff] [blame] | 744 | hflip = !!(pstate->rotation & DRM_REFLECT_X); |
| 745 | vflip = !!(pstate->rotation & DRM_REFLECT_Y); |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 746 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 747 | spin_lock_irqsave(&mdp5_plane->pipe_lock, flags); |
| 748 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 749 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), |
Hai Li | de31ea6 | 2015-03-05 15:20:49 -0500 | [diff] [blame] | 750 | MDP5_PIPE_SRC_IMG_SIZE_WIDTH(fb->width) | |
| 751 | MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(fb->height)); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 752 | |
| 753 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), |
| 754 | MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | |
| 755 | MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); |
| 756 | |
| 757 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), |
| 758 | MDP5_PIPE_SRC_XY_X(src_x) | |
| 759 | MDP5_PIPE_SRC_XY_Y(src_y)); |
| 760 | |
| 761 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), |
| 762 | MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | |
| 763 | MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); |
| 764 | |
| 765 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), |
| 766 | MDP5_PIPE_OUT_XY_X(crtc_x) | |
| 767 | MDP5_PIPE_OUT_XY_Y(crtc_y)); |
| 768 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 769 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), |
| 770 | MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | |
| 771 | MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) | |
| 772 | MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) | |
| 773 | MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) | |
| 774 | COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | |
| 775 | MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) | |
| 776 | MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | |
| 777 | COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | |
Rob Clark | 2d3584e | 2015-07-27 19:37:12 -0400 | [diff] [blame] | 778 | MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 779 | MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 780 | |
| 781 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), |
| 782 | MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) | |
| 783 | MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) | |
| 784 | MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) | |
| 785 | MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3])); |
| 786 | |
| 787 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), |
jilai wang | 8089082 | 2015-07-31 10:13:26 -0400 | [diff] [blame] | 788 | (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | |
| 789 | (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 790 | COND(pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 791 | MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); |
| 792 | |
| 793 | /* not using secure mode: */ |
| 794 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); |
| 795 | |
Stephane Viau | 8e2930c | 2015-09-15 08:41:52 -0400 | [diff] [blame] | 796 | if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) |
| 797 | mdp5_write_pixel_ext(mdp5_kms, pipe, format, |
| 798 | src_w, pe_left, pe_right, |
| 799 | src_h, pe_top, pe_bottom); |
| 800 | |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 801 | if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) { |
| 802 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 803 | phasex_step[COMP_0]); |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 804 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 805 | phasey_step[COMP_0]); |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 806 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 807 | phasex_step[COMP_1_2]); |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 808 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), |
Stephane Viau | 95651cd | 2015-09-15 08:41:51 -0400 | [diff] [blame] | 809 | phasey_step[COMP_1_2]); |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 810 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), |
| 811 | MDP5_PIPE_DECIMATION_VERT(vdecm) | |
| 812 | MDP5_PIPE_DECIMATION_HORZ(hdecm)); |
| 813 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config); |
| 814 | } |
Stephane Viau | f8d9b51 | 2014-12-08 10:48:58 -0500 | [diff] [blame] | 815 | |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 816 | if (mdp5_plane->caps & MDP_PIPE_CAP_CSC) { |
| 817 | if (MDP_FORMAT_IS_YUV(format)) |
| 818 | csc_enable(mdp5_kms, pipe, |
| 819 | mdp_get_default_csc_cfg(CSC_YUV2RGB)); |
| 820 | else |
| 821 | csc_disable(mdp5_kms, pipe); |
| 822 | } |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 823 | |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 824 | set_scanout_locked(plane, fb); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 825 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 826 | spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags); |
| 827 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 828 | return ret; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 829 | } |
| 830 | |
| 831 | void mdp5_plane_complete_flip(struct drm_plane *plane) |
| 832 | { |
| 833 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 834 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 835 | enum mdp5_pipe pipe = mdp5_plane->pipe; |
| 836 | |
| 837 | DBG("%s: complete flip", mdp5_plane->name); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 838 | |
Stephane Viau | d879eb5 | 2015-09-15 08:41:53 -0400 | [diff] [blame] | 839 | if (mdp5_kms->smp) |
| 840 | mdp5_smp_commit(mdp5_kms->smp, pipe); |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 841 | |
| 842 | to_mdp5_plane_state(plane->state)->pending = false; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 843 | } |
| 844 | |
| 845 | enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) |
| 846 | { |
| 847 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 848 | return mdp5_plane->pipe; |
| 849 | } |
| 850 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 851 | uint32_t mdp5_plane_get_flush(struct drm_plane *plane) |
| 852 | { |
| 853 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 854 | |
| 855 | return mdp5_plane->flush_mask; |
| 856 | } |
| 857 | |
Wentao Xu | 657c63f | 2015-06-19 14:03:42 -0400 | [diff] [blame] | 858 | /* called after vsync in thread context */ |
| 859 | void mdp5_plane_complete_commit(struct drm_plane *plane, |
| 860 | struct drm_plane_state *state) |
| 861 | { |
| 862 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
| 863 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
| 864 | enum mdp5_pipe pipe = mdp5_plane->pipe; |
| 865 | |
Stephane Viau | d879eb5 | 2015-09-15 08:41:53 -0400 | [diff] [blame] | 866 | if (!plane_enabled(plane->state) && mdp5_kms->smp) { |
Wentao Xu | 657c63f | 2015-06-19 14:03:42 -0400 | [diff] [blame] | 867 | DBG("%s: free SMP", mdp5_plane->name); |
| 868 | mdp5_smp_release(mdp5_kms->smp, pipe); |
| 869 | } |
| 870 | } |
| 871 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 872 | /* initialize plane */ |
| 873 | struct drm_plane *mdp5_plane_init(struct drm_device *dev, |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 874 | enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset, |
| 875 | uint32_t caps) |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 876 | { |
| 877 | struct drm_plane *plane = NULL; |
| 878 | struct mdp5_plane *mdp5_plane; |
| 879 | int ret; |
Matt Roper | 2d82d18 | 2014-04-01 15:22:39 -0700 | [diff] [blame] | 880 | enum drm_plane_type type; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 881 | |
| 882 | mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL); |
| 883 | if (!mdp5_plane) { |
| 884 | ret = -ENOMEM; |
| 885 | goto fail; |
| 886 | } |
| 887 | |
| 888 | plane = &mdp5_plane->base; |
| 889 | |
| 890 | mdp5_plane->pipe = pipe; |
| 891 | mdp5_plane->name = pipe2name(pipe); |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 892 | mdp5_plane->caps = caps; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 893 | |
jilai wang | 3498409 | 2015-07-08 18:12:40 -0400 | [diff] [blame] | 894 | mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, |
| 895 | ARRAY_SIZE(mdp5_plane->formats), |
| 896 | !pipe_supports_yuv(mdp5_plane->caps)); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 897 | |
Stephane Viau | 0deed25 | 2014-11-18 12:49:49 -0500 | [diff] [blame] | 898 | mdp5_plane->flush_mask = mdp_ctl_flush_mask_pipe(pipe); |
| 899 | mdp5_plane->reg_offset = reg_offset; |
| 900 | spin_lock_init(&mdp5_plane->pipe_lock); |
| 901 | |
Matt Roper | 2d82d18 | 2014-04-01 15:22:39 -0700 | [diff] [blame] | 902 | type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 903 | ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs, |
Matt Roper | 2d82d18 | 2014-04-01 15:22:39 -0700 | [diff] [blame] | 904 | mdp5_plane->formats, mdp5_plane->nformats, |
Ville Syrjälä | b0b3b79 | 2015-12-09 16:19:55 +0200 | [diff] [blame] | 905 | type, NULL); |
Rob Clark | ed85196 | 2014-11-19 12:31:03 -0500 | [diff] [blame] | 906 | if (ret) |
| 907 | goto fail; |
| 908 | |
| 909 | drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 910 | |
| 911 | mdp5_plane_install_properties(plane, &plane->base); |
| 912 | |
| 913 | return plane; |
| 914 | |
| 915 | fail: |
| 916 | if (plane) |
| 917 | mdp5_plane_destroy(plane); |
| 918 | |
| 919 | return ERR_PTR(ret); |
| 920 | } |