blob: c12d8bead2eea89beccb58be81cdad22336d2b08 [file] [log] [blame]
Thierry Reding175f16f2012-09-20 17:06:09 +02001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra20-tamonten.dtsi"
Thierry Reding175f16f2012-09-20 17:06:09 +02004
5/ {
6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8
Stephen Warren58ecb232013-11-25 17:53:16 -07009 host1x@50000000 {
10 hdmi@54280000 {
Thierry Redingcab2ed62012-11-16 16:56:52 +010011 status = "okay";
12 };
13 };
14
Thierry Reding175f16f2012-09-20 17:06:09 +020015 i2c@7000c000 {
Thierry Reding175f16f2012-09-20 17:06:09 +020016 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903";
18 reg = <0x1a>;
19 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -070020 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Thierry Reding175f16f2012-09-20 17:06:09 +020021
22 gpio-controller;
23 #gpio-cells = <2>;
24
25 micdet-cfg = <0>;
26 micdet-delay = <100>;
27 gpio-cfg = <0xffffffff
28 0xffffffff
29 0
30 0xffffffff
31 0xffffffff>;
32 };
33 };
34
Stephen Warren58ecb232013-11-25 17:53:16 -070035 pcie-controller@80003000 {
Thierry Reding237bcad2013-08-09 16:49:21 +020036 status = "okay";
37
38 pci@1,0 {
39 status = "okay";
40 };
41 };
42
Thierry Reding175f16f2012-09-20 17:06:09 +020043 sound {
44 compatible = "ad,tegra-audio-wm8903-tec",
45 "nvidia,tegra-audio-wm8903";
46 nvidia,model = "Avionic Design TEC";
47
48 nvidia,audio-routing =
49 "Headphone Jack", "HPOUTR",
50 "Headphone Jack", "HPOUTL",
51 "Int Spk", "ROP",
52 "Int Spk", "RON",
53 "Int Spk", "LOP",
54 "Int Spk", "LON",
55 "Mic Jack", "MICBIAS",
56 "IN1L", "Mic Jack";
57
58 nvidia,i2s-controller = <&tegra_i2s1>;
59 nvidia,audio-codec = <&wm8903>;
60
Stephen Warren3325f1b2013-02-12 17:25:15 -070061 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
62 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
63 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -060064
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +030065 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
66 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
67 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -060068 clock-names = "pll_a", "pll_a_out0", "mclk";
Thierry Reding175f16f2012-09-20 17:06:09 +020069 };
Alban Bedel23e63342014-06-19 15:25:49 +020070
71 regulators {
72 vcc_24v_reg: regulator@100 {
73 compatible = "regulator-fixed";
74 reg = <100>;
75 regulator-name = "vcc_24v";
76 regulator-min-microvolt = <24000000>;
77 regulator-max-microvolt = <24000000>;
78 regulator-always-on;
79 };
80
81 vdd_5v0_reg: regulator@101 {
82 compatible = "regulator-fixed";
83 reg = <101>;
84 regulator-name = "vdd_5v0";
85 vin-supply = <&vcc_24v_reg>;
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 regulator-always-on;
89 };
90
91 vdd_3v3_reg: regulator@102 {
92 compatible = "regulator-fixed";
93 reg = <102>;
94 regulator-name = "vdd_3v3";
95 vin-supply = <&vcc_24v_reg>;
96 regulator-min-microvolt = <3300000>;
97 regulator-max-microvolt = <3300000>;
98 regulator-always-on;
99 };
100
101 vdd_1v8_reg: regulator@103 {
102 compatible = "regulator-fixed";
103 reg = <103>;
104 regulator-name = "vdd_1v8";
105 vin-supply = <&vdd_3v3_reg>;
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 regulator-always-on;
109 };
110 };
Thierry Reding175f16f2012-09-20 17:06:09 +0200111};