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James Hsiao049359d2009-02-05 16:18:13 +11001/**
2 * AMCC SoC PPC4xx Crypto Driver
3 *
4 * Copyright (c) 2008 Applied Micro Circuits Corporation.
5 * All rights reserved. James Hsiao <jhsiao@amcc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * This is the header file for AMCC Crypto offload Linux device driver for
18 * use with Linux CryptoAPI.
19
20 */
21
22#ifndef __CRYPTO4XX_CORE_H__
23#define __CRYPTO4XX_CORE_H__
24
Herbert Xu4dc10c02009-07-14 20:21:46 +080025#include <crypto/internal/hash.h>
26
Christian Lamparter5343e672016-04-18 12:57:41 +020027#define MODULE_NAME "crypto4xx"
28
James Hsiao049359d2009-02-05 16:18:13 +110029#define PPC460SX_SDR0_SRST 0x201
30#define PPC405EX_SDR0_SRST 0x200
31#define PPC460EX_SDR0_SRST 0x201
32#define PPC460EX_CE_RESET 0x08000000
33#define PPC460SX_CE_RESET 0x20000000
34#define PPC405EX_CE_RESET 0x00000008
35
36#define CRYPTO4XX_CRYPTO_PRIORITY 300
Christian Lamparter1525e332017-10-04 01:00:08 +020037#define PPC4XX_NUM_PD 256
38#define PPC4XX_LAST_PD (PPC4XX_NUM_PD - 1)
James Hsiao049359d2009-02-05 16:18:13 +110039#define PPC4XX_NUM_GD 1024
Christian Lamparter1525e332017-10-04 01:00:08 +020040#define PPC4XX_LAST_GD (PPC4XX_NUM_GD - 1)
41#define PPC4XX_NUM_SD 256
42#define PPC4XX_LAST_SD (PPC4XX_NUM_SD - 1)
James Hsiao049359d2009-02-05 16:18:13 +110043#define PPC4XX_SD_BUFFER_SIZE 2048
44
45#define PD_ENTRY_INUSE 1
46#define PD_ENTRY_FREE 0
47#define ERING_WAS_FULL 0xffffffff
48
49struct crypto4xx_device;
50
51struct pd_uinfo {
52 struct crypto4xx_device *dev;
53 u32 state;
54 u32 using_sd;
55 u32 first_gd; /* first gather discriptor
56 used by this packet */
57 u32 num_gd; /* number of gather discriptor
58 used by this packet */
59 u32 first_sd; /* first scatter discriptor
60 used by this packet */
61 u32 num_sd; /* number of scatter discriptors
62 used by this packet */
63 void *sa_va; /* shadow sa, when using cp from ctx->sa */
64 u32 sa_pa;
65 void *sr_va; /* state record for shadow sa */
66 u32 sr_pa;
67 struct scatterlist *dest_va;
68 struct crypto_async_request *async_req; /* base crypto request
69 for this packet */
70};
71
72struct crypto4xx_device {
73 struct crypto4xx_core_device *core_dev;
74 char *name;
75 u64 ce_phy_address;
76 void __iomem *ce_base;
Christian Lamparter5343e672016-04-18 12:57:41 +020077 void __iomem *trng_base;
James Hsiao049359d2009-02-05 16:18:13 +110078
79 void *pdr; /* base address of packet
80 descriptor ring */
81 dma_addr_t pdr_pa; /* physical address used to
82 program ce pdr_base_register */
83 void *gdr; /* gather descriptor ring */
84 dma_addr_t gdr_pa; /* physical address used to
85 program ce gdr_base_register */
86 void *sdr; /* scatter descriptor ring */
87 dma_addr_t sdr_pa; /* physical address used to
88 program ce sdr_base_register */
89 void *scatter_buffer_va;
90 dma_addr_t scatter_buffer_pa;
91 u32 scatter_buffer_size;
92
93 void *shadow_sa_pool; /* pool of memory for sa in pd_uinfo */
94 dma_addr_t shadow_sa_pool_pa;
95 void *shadow_sr_pool; /* pool of memory for sr in pd_uinfo */
96 dma_addr_t shadow_sr_pool_pa;
97 u32 pdr_tail;
98 u32 pdr_head;
99 u32 gdr_tail;
100 u32 gdr_head;
101 u32 sdr_tail;
102 u32 sdr_head;
103 void *pdr_uinfo;
104 struct list_head alg_list; /* List of algorithm supported
105 by this device */
106};
107
108struct crypto4xx_core_device {
109 struct device *device;
Grant Likely2dc11582010-08-06 09:25:50 -0600110 struct platform_device *ofdev;
James Hsiao049359d2009-02-05 16:18:13 +1100111 struct crypto4xx_device *dev;
Christian Lamparter5343e672016-04-18 12:57:41 +0200112 struct hwrng *trng;
James Hsiao049359d2009-02-05 16:18:13 +1100113 u32 int_status;
114 u32 irq;
115 struct tasklet_struct tasklet;
116 spinlock_t lock;
117};
118
119struct crypto4xx_ctx {
120 struct crypto4xx_device *dev;
121 void *sa_in;
122 dma_addr_t sa_in_dma_addr;
123 void *sa_out;
124 dma_addr_t sa_out_dma_addr;
125 void *state_record;
126 dma_addr_t state_record_dma_addr;
127 u32 sa_len;
128 u32 offset_to_sr_ptr; /* offset to state ptr, in dynamic sa */
129 u32 direction;
130 u32 next_hdr;
131 u32 save_iv;
132 u32 pd_ctl_len;
133 u32 pd_ctl;
134 u32 bypass;
135 u32 is_hash;
136 u32 hash_final;
137};
138
139struct crypto4xx_req_ctx {
140 struct crypto4xx_device *dev; /* Device in which
141 operation to send to */
142 void *sa;
143 u32 sa_dma_addr;
144 u16 sa_len;
145};
146
Herbert Xu4dc10c02009-07-14 20:21:46 +0800147struct crypto4xx_alg_common {
148 u32 type;
149 union {
150 struct crypto_alg cipher;
151 struct ahash_alg hash;
152 } u;
153};
154
James Hsiao049359d2009-02-05 16:18:13 +1100155struct crypto4xx_alg {
156 struct list_head entry;
Herbert Xu4dc10c02009-07-14 20:21:46 +0800157 struct crypto4xx_alg_common alg;
James Hsiao049359d2009-02-05 16:18:13 +1100158 struct crypto4xx_device *dev;
159};
160
Herbert Xu4dc10c02009-07-14 20:21:46 +0800161static inline struct crypto4xx_alg *crypto_alg_to_crypto4xx_alg(
162 struct crypto_alg *x)
163{
164 switch (x->cra_flags & CRYPTO_ALG_TYPE_MASK) {
165 case CRYPTO_ALG_TYPE_AHASH:
166 return container_of(__crypto_ahash_alg(x),
167 struct crypto4xx_alg, alg.u.hash);
168 }
169
170 return container_of(x, struct crypto4xx_alg, alg.u.cipher);
171}
James Hsiao049359d2009-02-05 16:18:13 +1100172
173extern int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size);
174extern void crypto4xx_free_sa(struct crypto4xx_ctx *ctx);
175extern u32 crypto4xx_alloc_sa_rctx(struct crypto4xx_ctx *ctx,
176 struct crypto4xx_ctx *rctx);
177extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx);
178extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
179extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
180extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx);
181extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx);
182extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx);
183extern void crypto4xx_memcpy_le(unsigned int *dst,
184 const unsigned char *buf, int len);
185extern u32 crypto4xx_build_pd(struct crypto_async_request *req,
186 struct crypto4xx_ctx *ctx,
187 struct scatterlist *src,
188 struct scatterlist *dst,
189 unsigned int datalen,
190 void *iv, u32 iv_len);
191extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
192 const u8 *key, unsigned int keylen);
193extern int crypto4xx_encrypt(struct ablkcipher_request *req);
194extern int crypto4xx_decrypt(struct ablkcipher_request *req);
195extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
196extern int crypto4xx_hash_digest(struct ahash_request *req);
197extern int crypto4xx_hash_final(struct ahash_request *req);
198extern int crypto4xx_hash_update(struct ahash_request *req);
199extern int crypto4xx_hash_init(struct ahash_request *req);
200#endif