Christian König | e409b12 | 2013-08-13 11:56:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Christian König <christian.koenig@amd.com> |
| 23 | */ |
| 24 | |
| 25 | #include <linux/firmware.h> |
| 26 | #include <drm/drmP.h> |
| 27 | #include "radeon.h" |
| 28 | #include "radeon_asic.h" |
| 29 | #include "rv770d.h" |
| 30 | |
| 31 | /** |
| 32 | * uvd_v2_2_fence_emit - emit an fence & trap command |
| 33 | * |
| 34 | * @rdev: radeon_device pointer |
| 35 | * @fence: fence to emit |
| 36 | * |
| 37 | * Write a fence and a trap command to the ring. |
| 38 | */ |
| 39 | void uvd_v2_2_fence_emit(struct radeon_device *rdev, |
| 40 | struct radeon_fence *fence) |
| 41 | { |
| 42 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
| 43 | uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; |
| 44 | |
| 45 | radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); |
| 46 | radeon_ring_write(ring, fence->seq); |
| 47 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
| 48 | radeon_ring_write(ring, addr & 0xffffffff); |
| 49 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
| 50 | radeon_ring_write(ring, upper_32_bits(addr) & 0xff); |
| 51 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
| 52 | radeon_ring_write(ring, 0); |
| 53 | |
| 54 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); |
| 55 | radeon_ring_write(ring, 0); |
| 56 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); |
| 57 | radeon_ring_write(ring, 0); |
| 58 | radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); |
| 59 | radeon_ring_write(ring, 2); |
| 60 | return; |
| 61 | } |
| 62 | |
| 63 | /** |
| 64 | * uvd_v2_2_resume - memory controller programming |
| 65 | * |
| 66 | * @rdev: radeon_device pointer |
| 67 | * |
| 68 | * Let the UVD memory controller know it's offsets |
| 69 | */ |
| 70 | int uvd_v2_2_resume(struct radeon_device *rdev) |
| 71 | { |
| 72 | uint64_t addr; |
| 73 | uint32_t chip_id, size; |
| 74 | int r; |
| 75 | |
| 76 | r = radeon_uvd_resume(rdev); |
| 77 | if (r) |
| 78 | return r; |
| 79 | |
| 80 | /* programm the VCPU memory controller bits 0-27 */ |
| 81 | addr = rdev->uvd.gpu_addr >> 3; |
| 82 | size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3; |
| 83 | WREG32(UVD_VCPU_CACHE_OFFSET0, addr); |
| 84 | WREG32(UVD_VCPU_CACHE_SIZE0, size); |
| 85 | |
| 86 | addr += size; |
| 87 | size = RADEON_UVD_STACK_SIZE >> 3; |
| 88 | WREG32(UVD_VCPU_CACHE_OFFSET1, addr); |
| 89 | WREG32(UVD_VCPU_CACHE_SIZE1, size); |
| 90 | |
| 91 | addr += size; |
| 92 | size = RADEON_UVD_HEAP_SIZE >> 3; |
| 93 | WREG32(UVD_VCPU_CACHE_OFFSET2, addr); |
| 94 | WREG32(UVD_VCPU_CACHE_SIZE2, size); |
| 95 | |
| 96 | /* bits 28-31 */ |
| 97 | addr = (rdev->uvd.gpu_addr >> 28) & 0xF; |
| 98 | WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); |
| 99 | |
| 100 | /* bits 32-39 */ |
| 101 | addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; |
| 102 | WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); |
| 103 | |
| 104 | /* tell firmware which hardware it is running on */ |
| 105 | switch (rdev->family) { |
| 106 | default: |
| 107 | return -EINVAL; |
| 108 | case CHIP_RV710: |
| 109 | chip_id = 0x01000005; |
| 110 | break; |
| 111 | case CHIP_RV730: |
| 112 | chip_id = 0x01000006; |
| 113 | break; |
| 114 | case CHIP_RV740: |
| 115 | chip_id = 0x01000007; |
| 116 | break; |
| 117 | case CHIP_CYPRESS: |
| 118 | case CHIP_HEMLOCK: |
| 119 | chip_id = 0x01000008; |
| 120 | break; |
| 121 | case CHIP_JUNIPER: |
| 122 | chip_id = 0x01000009; |
| 123 | break; |
| 124 | case CHIP_REDWOOD: |
| 125 | chip_id = 0x0100000a; |
| 126 | break; |
| 127 | case CHIP_CEDAR: |
| 128 | chip_id = 0x0100000b; |
| 129 | break; |
| 130 | case CHIP_SUMO: |
| 131 | case CHIP_SUMO2: |
| 132 | chip_id = 0x0100000c; |
| 133 | break; |
| 134 | case CHIP_PALM: |
| 135 | chip_id = 0x0100000e; |
| 136 | break; |
| 137 | case CHIP_CAYMAN: |
| 138 | chip_id = 0x0100000f; |
| 139 | break; |
| 140 | case CHIP_BARTS: |
| 141 | chip_id = 0x01000010; |
| 142 | break; |
| 143 | case CHIP_TURKS: |
| 144 | chip_id = 0x01000011; |
| 145 | break; |
| 146 | case CHIP_CAICOS: |
| 147 | chip_id = 0x01000012; |
| 148 | break; |
| 149 | case CHIP_TAHITI: |
| 150 | chip_id = 0x01000014; |
| 151 | break; |
| 152 | case CHIP_VERDE: |
| 153 | chip_id = 0x01000015; |
| 154 | break; |
| 155 | case CHIP_PITCAIRN: |
Alex Deucher | 5d02933 | 2014-01-20 11:25:35 -0500 | [diff] [blame] | 156 | case CHIP_OLAND: |
Christian König | e409b12 | 2013-08-13 11:56:53 +0200 | [diff] [blame] | 157 | chip_id = 0x01000016; |
| 158 | break; |
| 159 | case CHIP_ARUBA: |
| 160 | chip_id = 0x01000017; |
| 161 | break; |
| 162 | } |
| 163 | WREG32(UVD_VCPU_CHIP_ID, chip_id); |
| 164 | |
| 165 | return 0; |
| 166 | } |