Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 1 | /* |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #define pr_fmt(fmt) "dsi-hw:" fmt |
| 16 | #include <linux/delay.h> |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 17 | #include <linux/iopoll.h> |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 18 | |
| 19 | #include "dsi_ctrl_hw.h" |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 20 | #include "dsi_ctrl_reg.h" |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 21 | #include "dsi_hw.h" |
| 22 | |
| 23 | #define MMSS_MISC_CLAMP_REG_OFF 0x0014 |
| 24 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 25 | /** |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 26 | * dsi_ctrl_hw_14_setup_lane_map() - setup mapping between |
| 27 | * logical and physical lanes |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 28 | * @ctrl: Pointer to the controller host hardware. |
| 29 | * @lane_map: Structure defining the mapping between DSI logical |
| 30 | * lanes and physical lanes. |
| 31 | */ |
| 32 | void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl, |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 33 | struct dsi_lane_map *lane_map) |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 34 | { |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 35 | DSI_W32(ctrl, DSI_LANE_SWAP_CTRL, lane_map->lane_map_v1); |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 36 | |
| 37 | pr_debug("[DSI_%d] Lane swap setup complete\n", ctrl->index); |
| 38 | } |
| 39 | |
| 40 | /** |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 41 | * dsi_ctrl_hw_14_wait_for_lane_idle() |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 42 | * This function waits for all the active DSI lanes to be idle by polling all |
| 43 | * the FIFO_EMPTY bits and polling he lane status to ensure that all the lanes |
| 44 | * are in stop state. This function assumes that the bus clocks required to |
| 45 | * access the registers are already turned on. |
| 46 | * |
| 47 | * @ctrl: Pointer to the controller host hardware. |
| 48 | * @lanes: ORed list of lanes (enum dsi_data_lanes) which need |
| 49 | * to be stopped. |
| 50 | * |
| 51 | * return: Error code. |
| 52 | */ |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 53 | int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes) |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 54 | { |
| 55 | int rc = 0, val = 0; |
| 56 | u32 stop_state_mask = 0, fifo_empty_mask = 0; |
| 57 | u32 const sleep_us = 10; |
| 58 | u32 const timeout_us = 100; |
| 59 | |
| 60 | if (lanes & DSI_DATA_LANE_0) { |
| 61 | stop_state_mask |= BIT(0); |
| 62 | fifo_empty_mask |= (BIT(12) | BIT(16)); |
| 63 | } |
| 64 | if (lanes & DSI_DATA_LANE_1) { |
| 65 | stop_state_mask |= BIT(1); |
| 66 | fifo_empty_mask |= BIT(20); |
| 67 | } |
| 68 | if (lanes & DSI_DATA_LANE_2) { |
| 69 | stop_state_mask |= BIT(2); |
| 70 | fifo_empty_mask |= BIT(24); |
| 71 | } |
| 72 | if (lanes & DSI_DATA_LANE_3) { |
| 73 | stop_state_mask |= BIT(3); |
| 74 | fifo_empty_mask |= BIT(28); |
| 75 | } |
| 76 | |
| 77 | pr_debug("%s: polling for fifo empty, mask=0x%08x\n", __func__, |
| 78 | fifo_empty_mask); |
| 79 | rc = readl_poll_timeout(ctrl->base + DSI_FIFO_STATUS, val, |
| 80 | (val & fifo_empty_mask), sleep_us, timeout_us); |
| 81 | if (rc) { |
| 82 | pr_err("%s: fifo not empty, FIFO_STATUS=0x%08x\n", |
| 83 | __func__, val); |
| 84 | goto error; |
| 85 | } |
| 86 | |
| 87 | pr_debug("%s: polling for lanes to be in stop state, mask=0x%08x\n", |
| 88 | __func__, stop_state_mask); |
| 89 | rc = readl_poll_timeout(ctrl->base + DSI_LANE_STATUS, val, |
| 90 | (val & stop_state_mask), sleep_us, timeout_us); |
| 91 | if (rc) { |
| 92 | pr_err("%s: lanes not in stop state, LANE_STATUS=0x%08x\n", |
| 93 | __func__, val); |
| 94 | goto error; |
| 95 | } |
| 96 | |
| 97 | error: |
| 98 | return rc; |
| 99 | |
| 100 | } |
| 101 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 102 | /** |
| 103 | * ulps_request() - request ulps entry for specified lanes |
| 104 | * @ctrl: Pointer to the controller host hardware. |
| 105 | * @lanes: ORed list of lanes (enum dsi_data_lanes) which need |
| 106 | * to enter ULPS. |
| 107 | * |
| 108 | * Caller should check if lanes are in ULPS mode by calling |
| 109 | * get_lanes_in_ulps() operation. |
| 110 | */ |
| 111 | void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes) |
| 112 | { |
| 113 | u32 reg = 0; |
| 114 | |
| 115 | if (lanes & DSI_CLOCK_LANE) |
| 116 | reg = BIT(4); |
| 117 | if (lanes & DSI_DATA_LANE_0) |
| 118 | reg |= BIT(0); |
| 119 | if (lanes & DSI_DATA_LANE_1) |
| 120 | reg |= BIT(1); |
| 121 | if (lanes & DSI_DATA_LANE_2) |
| 122 | reg |= BIT(2); |
| 123 | if (lanes & DSI_DATA_LANE_3) |
| 124 | reg |= BIT(3); |
| 125 | |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 126 | /* |
| 127 | * ULPS entry request. Wait for short time to make sure |
| 128 | * that the lanes enter ULPS. Recommended as per HPG. |
| 129 | */ |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 130 | DSI_W32(ctrl, DSI_LANE_CTRL, reg); |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 131 | usleep_range(100, 110); |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 132 | |
| 133 | pr_debug("[DSI_%d] ULPS requested for lanes 0x%x\n", ctrl->index, |
| 134 | lanes); |
| 135 | } |
| 136 | |
| 137 | /** |
| 138 | * ulps_exit() - exit ULPS on specified lanes |
| 139 | * @ctrl: Pointer to the controller host hardware. |
| 140 | * @lanes: ORed list of lanes (enum dsi_data_lanes) which need |
| 141 | * to exit ULPS. |
| 142 | * |
| 143 | * Caller should check if lanes are in active mode by calling |
| 144 | * get_lanes_in_ulps() operation. |
| 145 | */ |
| 146 | void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes) |
| 147 | { |
| 148 | u32 reg = 0; |
| 149 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 150 | if (lanes & DSI_CLOCK_LANE) |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 151 | reg = BIT(12); |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 152 | if (lanes & DSI_DATA_LANE_0) |
| 153 | reg |= BIT(8); |
| 154 | if (lanes & DSI_DATA_LANE_1) |
| 155 | reg |= BIT(9); |
| 156 | if (lanes & DSI_DATA_LANE_2) |
| 157 | reg |= BIT(10); |
| 158 | if (lanes & DSI_DATA_LANE_3) |
| 159 | reg |= BIT(11); |
| 160 | |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 161 | /* |
| 162 | * ULPS Exit Request |
| 163 | * Hardware requirement is to wait for at least 1ms |
| 164 | */ |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 165 | DSI_W32(ctrl, DSI_LANE_CTRL, reg); |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 166 | usleep_range(1000, 1010); |
| 167 | /* |
| 168 | * Sometimes when exiting ULPS, it is possible that some DSI |
| 169 | * lanes are not in the stop state which could lead to DSI |
| 170 | * commands not going through. To avoid this, force the lanes |
| 171 | * to be in stop state. |
| 172 | */ |
| 173 | DSI_W32(ctrl, DSI_LANE_CTRL, reg << 8); |
| 174 | DSI_W32(ctrl, DSI_LANE_CTRL, 0x0); |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 175 | |
| 176 | pr_debug("[DSI_%d] ULPS exit request for lanes=0x%x\n", |
| 177 | ctrl->index, lanes); |
| 178 | } |
| 179 | |
| 180 | /** |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 181 | * get_lanes_in_ulps() - returns the list of lanes in ULPS mode |
| 182 | * @ctrl: Pointer to the controller host hardware. |
| 183 | * |
| 184 | * Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS |
| 185 | * state. If 0 is returned, all the lanes are active. |
| 186 | * |
| 187 | * Return: List of lanes in ULPS state. |
| 188 | */ |
| 189 | u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl) |
| 190 | { |
| 191 | u32 reg = 0; |
| 192 | u32 lanes = 0; |
| 193 | |
| 194 | reg = DSI_R32(ctrl, DSI_LANE_STATUS); |
| 195 | if (!(reg & BIT(8))) |
| 196 | lanes |= DSI_DATA_LANE_0; |
| 197 | if (!(reg & BIT(9))) |
| 198 | lanes |= DSI_DATA_LANE_1; |
| 199 | if (!(reg & BIT(10))) |
| 200 | lanes |= DSI_DATA_LANE_2; |
| 201 | if (!(reg & BIT(11))) |
| 202 | lanes |= DSI_DATA_LANE_3; |
| 203 | if (!(reg & BIT(12))) |
| 204 | lanes |= DSI_CLOCK_LANE; |
| 205 | |
| 206 | pr_debug("[DSI_%d] lanes in ulps = 0x%x\n", ctrl->index, lanes); |
| 207 | return lanes; |
| 208 | } |
| 209 | |
| 210 | /** |
| 211 | * clamp_enable() - enable DSI clamps to keep PHY driving a stable link |
| 212 | * @ctrl: Pointer to the controller host hardware. |
| 213 | * @lanes: ORed list of lanes which need to be clamped. |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 214 | * @enable_ulps: Boolean to specify if ULPS is enabled in DSI controller |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 215 | */ |
| 216 | void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl, |
| 217 | u32 lanes, |
| 218 | bool enable_ulps) |
| 219 | { |
| 220 | u32 clamp_reg = 0; |
| 221 | u32 bit_shift = 0; |
| 222 | u32 reg = 0; |
| 223 | |
| 224 | if (ctrl->index == 1) |
| 225 | bit_shift = 16; |
| 226 | |
| 227 | if (lanes & DSI_CLOCK_LANE) { |
| 228 | clamp_reg |= BIT(9); |
| 229 | if (enable_ulps) |
| 230 | clamp_reg |= BIT(8); |
| 231 | } |
| 232 | |
| 233 | if (lanes & DSI_DATA_LANE_0) { |
| 234 | clamp_reg |= BIT(7); |
| 235 | if (enable_ulps) |
| 236 | clamp_reg |= BIT(6); |
| 237 | } |
| 238 | |
| 239 | if (lanes & DSI_DATA_LANE_1) { |
| 240 | clamp_reg |= BIT(5); |
| 241 | if (enable_ulps) |
| 242 | clamp_reg |= BIT(4); |
| 243 | } |
| 244 | |
| 245 | if (lanes & DSI_DATA_LANE_2) { |
| 246 | clamp_reg |= BIT(3); |
| 247 | if (enable_ulps) |
| 248 | clamp_reg |= BIT(2); |
| 249 | } |
| 250 | |
| 251 | if (lanes & DSI_DATA_LANE_3) { |
| 252 | clamp_reg |= BIT(1); |
| 253 | if (enable_ulps) |
| 254 | clamp_reg |= BIT(0); |
| 255 | } |
| 256 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 257 | reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF); |
| 258 | reg |= (clamp_reg << bit_shift); |
| 259 | DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg); |
| 260 | |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 261 | reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF); |
| 262 | reg |= (BIT(15) << bit_shift); /* Enable clamp */ |
| 263 | DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg); |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 264 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 265 | pr_debug("[DSI_%d] Clamps enabled for lanes=0x%x\n", ctrl->index, |
| 266 | lanes); |
| 267 | } |
| 268 | |
| 269 | /** |
| 270 | * clamp_disable() - disable DSI clamps |
| 271 | * @ctrl: Pointer to the controller host hardware. |
| 272 | * @lanes: ORed list of lanes which need to have clamps released. |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 273 | * @disable_ulps: Boolean to specify if ULPS is enabled in DSI controller |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 274 | */ |
| 275 | void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl, |
| 276 | u32 lanes, |
| 277 | bool disable_ulps) |
| 278 | { |
| 279 | u32 clamp_reg = 0; |
| 280 | u32 bit_shift = 0; |
| 281 | u32 reg = 0; |
| 282 | |
| 283 | if (ctrl->index == 1) |
| 284 | bit_shift = 16; |
| 285 | |
| 286 | if (lanes & DSI_CLOCK_LANE) { |
| 287 | clamp_reg |= BIT(9); |
| 288 | if (disable_ulps) |
| 289 | clamp_reg |= BIT(8); |
| 290 | } |
| 291 | |
| 292 | if (lanes & DSI_DATA_LANE_0) { |
| 293 | clamp_reg |= BIT(7); |
| 294 | if (disable_ulps) |
| 295 | clamp_reg |= BIT(6); |
| 296 | } |
| 297 | |
| 298 | if (lanes & DSI_DATA_LANE_1) { |
| 299 | clamp_reg |= BIT(5); |
| 300 | if (disable_ulps) |
| 301 | clamp_reg |= BIT(4); |
| 302 | } |
| 303 | |
| 304 | if (lanes & DSI_DATA_LANE_2) { |
| 305 | clamp_reg |= BIT(3); |
| 306 | if (disable_ulps) |
| 307 | clamp_reg |= BIT(2); |
| 308 | } |
| 309 | |
| 310 | if (lanes & DSI_DATA_LANE_3) { |
| 311 | clamp_reg |= BIT(1); |
| 312 | if (disable_ulps) |
| 313 | clamp_reg |= BIT(0); |
| 314 | } |
| 315 | |
| 316 | clamp_reg |= BIT(15); /* Enable clamp */ |
| 317 | clamp_reg <<= bit_shift; |
| 318 | |
Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 319 | reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF); |
| 320 | reg &= ~(clamp_reg); |
| 321 | DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg); |
| 322 | |
| 323 | pr_debug("[DSI_%d] Disable clamps for lanes=%d\n", ctrl->index, lanes); |
| 324 | } |
| 325 | |
Ajay Singh Parmar | 48ea427 | 2016-06-27 11:44:34 -0700 | [diff] [blame] | 326 | #define DUMP_REG_VALUE(off) "\t%-30s: 0x%08x\n", #off, DSI_R32(ctrl, off) |
| 327 | ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl, |
| 328 | char *buf, |
| 329 | u32 size) |
| 330 | { |
| 331 | u32 len = 0; |
| 332 | |
| 333 | len += snprintf((buf + len), (size - len), "CONFIGURATION REGS:\n"); |
| 334 | |
| 335 | len += snprintf((buf + len), (size - len), |
| 336 | DUMP_REG_VALUE(DSI_HW_VERSION)); |
| 337 | len += snprintf((buf + len), (size - len), |
| 338 | DUMP_REG_VALUE(DSI_CTRL)); |
| 339 | len += snprintf((buf + len), (size - len), |
| 340 | DUMP_REG_VALUE(DSI_STATUS)); |
| 341 | len += snprintf((buf + len), (size - len), |
| 342 | DUMP_REG_VALUE(DSI_FIFO_STATUS)); |
| 343 | len += snprintf((buf + len), (size - len), |
| 344 | DUMP_REG_VALUE(DSI_VIDEO_MODE_CTRL)); |
| 345 | len += snprintf((buf + len), (size - len), |
| 346 | DUMP_REG_VALUE(DSI_VIDEO_MODE_SYNC_DATATYPE)); |
| 347 | len += snprintf((buf + len), (size - len), |
| 348 | DUMP_REG_VALUE(DSI_VIDEO_MODE_PIXEL_DATATYPE)); |
| 349 | len += snprintf((buf + len), (size - len), |
| 350 | DUMP_REG_VALUE(DSI_VIDEO_MODE_BLANKING_DATATYPE)); |
| 351 | len += snprintf((buf + len), (size - len), |
| 352 | DUMP_REG_VALUE(DSI_VIDEO_MODE_DATA_CTRL)); |
| 353 | len += snprintf((buf + len), (size - len), |
| 354 | DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_H)); |
| 355 | len += snprintf((buf + len), (size - len), |
| 356 | DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_V)); |
| 357 | len += snprintf((buf + len), (size - len), |
| 358 | DUMP_REG_VALUE(DSI_VIDEO_MODE_TOTAL)); |
| 359 | len += snprintf((buf + len), (size - len), |
| 360 | DUMP_REG_VALUE(DSI_VIDEO_MODE_HSYNC)); |
| 361 | len += snprintf((buf + len), (size - len), |
| 362 | DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC)); |
| 363 | len += snprintf((buf + len), (size - len), |
| 364 | DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC_VPOS)); |
| 365 | len += snprintf((buf + len), (size - len), |
| 366 | DUMP_REG_VALUE(DSI_COMMAND_MODE_DMA_CTRL)); |
| 367 | len += snprintf((buf + len), (size - len), |
| 368 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL)); |
| 369 | len += snprintf((buf + len), (size - len), |
| 370 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL)); |
| 371 | len += snprintf((buf + len), (size - len), |
| 372 | DUMP_REG_VALUE(DSI_DMA_CMD_OFFSET)); |
| 373 | len += snprintf((buf + len), (size - len), |
| 374 | DUMP_REG_VALUE(DSI_DMA_CMD_LENGTH)); |
| 375 | len += snprintf((buf + len), (size - len), |
| 376 | DUMP_REG_VALUE(DSI_DMA_FIFO_CTRL)); |
| 377 | len += snprintf((buf + len), (size - len), |
| 378 | DUMP_REG_VALUE(DSI_DMA_NULL_PACKET_DATA)); |
| 379 | len += snprintf((buf + len), (size - len), |
| 380 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_CTRL)); |
| 381 | len += snprintf((buf + len), (size - len), |
| 382 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_TOTAL)); |
| 383 | len += snprintf((buf + len), (size - len), |
| 384 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_CTRL)); |
| 385 | len += snprintf((buf + len), (size - len), |
| 386 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_TOTAL)); |
| 387 | len += snprintf((buf + len), (size - len), |
| 388 | DUMP_REG_VALUE(DSI_ACK_ERR_STATUS)); |
| 389 | len += snprintf((buf + len), (size - len), |
| 390 | DUMP_REG_VALUE(DSI_RDBK_DATA0)); |
| 391 | len += snprintf((buf + len), (size - len), |
| 392 | DUMP_REG_VALUE(DSI_RDBK_DATA1)); |
| 393 | len += snprintf((buf + len), (size - len), |
| 394 | DUMP_REG_VALUE(DSI_RDBK_DATA2)); |
| 395 | len += snprintf((buf + len), (size - len), |
| 396 | DUMP_REG_VALUE(DSI_RDBK_DATA3)); |
| 397 | len += snprintf((buf + len), (size - len), |
| 398 | DUMP_REG_VALUE(DSI_RDBK_DATATYPE0)); |
| 399 | len += snprintf((buf + len), (size - len), |
| 400 | DUMP_REG_VALUE(DSI_RDBK_DATATYPE1)); |
| 401 | len += snprintf((buf + len), (size - len), |
| 402 | DUMP_REG_VALUE(DSI_TRIG_CTRL)); |
| 403 | len += snprintf((buf + len), (size - len), |
| 404 | DUMP_REG_VALUE(DSI_EXT_MUX)); |
| 405 | len += snprintf((buf + len), (size - len), |
| 406 | DUMP_REG_VALUE(DSI_EXT_MUX_TE_PULSE_DETECT_CTRL)); |
| 407 | len += snprintf((buf + len), (size - len), |
| 408 | DUMP_REG_VALUE(DSI_CMD_MODE_DMA_SW_TRIGGER)); |
| 409 | len += snprintf((buf + len), (size - len), |
| 410 | DUMP_REG_VALUE(DSI_CMD_MODE_MDP_SW_TRIGGER)); |
| 411 | len += snprintf((buf + len), (size - len), |
| 412 | DUMP_REG_VALUE(DSI_CMD_MODE_BTA_SW_TRIGGER)); |
| 413 | len += snprintf((buf + len), (size - len), |
| 414 | DUMP_REG_VALUE(DSI_RESET_SW_TRIGGER)); |
| 415 | len += snprintf((buf + len), (size - len), |
| 416 | DUMP_REG_VALUE(DSI_LANE_STATUS)); |
| 417 | len += snprintf((buf + len), (size - len), |
| 418 | DUMP_REG_VALUE(DSI_LANE_CTRL)); |
| 419 | len += snprintf((buf + len), (size - len), |
| 420 | DUMP_REG_VALUE(DSI_LANE_SWAP_CTRL)); |
| 421 | len += snprintf((buf + len), (size - len), |
| 422 | DUMP_REG_VALUE(DSI_DLN0_PHY_ERR)); |
| 423 | len += snprintf((buf + len), (size - len), |
| 424 | DUMP_REG_VALUE(DSI_LP_TIMER_CTRL)); |
| 425 | len += snprintf((buf + len), (size - len), |
| 426 | DUMP_REG_VALUE(DSI_HS_TIMER_CTRL)); |
| 427 | len += snprintf((buf + len), (size - len), |
| 428 | DUMP_REG_VALUE(DSI_TIMEOUT_STATUS)); |
| 429 | len += snprintf((buf + len), (size - len), |
| 430 | DUMP_REG_VALUE(DSI_CLKOUT_TIMING_CTRL)); |
| 431 | len += snprintf((buf + len), (size - len), |
| 432 | DUMP_REG_VALUE(DSI_EOT_PACKET)); |
| 433 | len += snprintf((buf + len), (size - len), |
| 434 | DUMP_REG_VALUE(DSI_EOT_PACKET_CTRL)); |
| 435 | len += snprintf((buf + len), (size - len), |
| 436 | DUMP_REG_VALUE(DSI_GENERIC_ESC_TX_TRIGGER)); |
| 437 | len += snprintf((buf + len), (size - len), |
| 438 | DUMP_REG_VALUE(DSI_ERR_INT_MASK0)); |
| 439 | len += snprintf((buf + len), (size - len), |
| 440 | DUMP_REG_VALUE(DSI_INT_CTRL)); |
| 441 | len += snprintf((buf + len), (size - len), |
| 442 | DUMP_REG_VALUE(DSI_SOFT_RESET)); |
| 443 | len += snprintf((buf + len), (size - len), |
| 444 | DUMP_REG_VALUE(DSI_CLK_CTRL)); |
| 445 | len += snprintf((buf + len), (size - len), |
| 446 | DUMP_REG_VALUE(DSI_CLK_STATUS)); |
| 447 | len += snprintf((buf + len), (size - len), |
| 448 | DUMP_REG_VALUE(DSI_PHY_SW_RESET)); |
| 449 | len += snprintf((buf + len), (size - len), |
| 450 | DUMP_REG_VALUE(DSI_AXI2AHB_CTRL)); |
| 451 | len += snprintf((buf + len), (size - len), |
| 452 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL2)); |
| 453 | len += snprintf((buf + len), (size - len), |
| 454 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_CTRL)); |
| 455 | len += snprintf((buf + len), (size - len), |
| 456 | DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_TOTAL)); |
| 457 | len += snprintf((buf + len), (size - len), |
| 458 | DUMP_REG_VALUE(DSI_VBIF_CTRL)); |
| 459 | len += snprintf((buf + len), (size - len), |
| 460 | DUMP_REG_VALUE(DSI_AES_CTRL)); |
| 461 | len += snprintf((buf + len), (size - len), |
| 462 | DUMP_REG_VALUE(DSI_RDBK_DATA_CTRL)); |
| 463 | len += snprintf((buf + len), (size - len), |
| 464 | DUMP_REG_VALUE(DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL2)); |
| 465 | len += snprintf((buf + len), (size - len), |
| 466 | DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_STATUS)); |
| 467 | len += snprintf((buf + len), (size - len), |
| 468 | DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_WRITE_TRIGGER)); |
| 469 | len += snprintf((buf + len), (size - len), |
| 470 | DUMP_REG_VALUE(DSI_DSI_TIMING_FLUSH)); |
| 471 | len += snprintf((buf + len), (size - len), |
| 472 | DUMP_REG_VALUE(DSI_DSI_TIMING_DB_MODE)); |
| 473 | len += snprintf((buf + len), (size - len), |
| 474 | DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_RESET)); |
| 475 | len += snprintf((buf + len), (size - len), |
| 476 | DUMP_REG_VALUE(DSI_VERSION)); |
| 477 | |
| 478 | pr_err("LLENGTH = %d\n", len); |
| 479 | return len; |
| 480 | } |