Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #define pr_fmt(fmt) "dsi-hw:" fmt |
| 16 | |
| 17 | #include "dsi_ctrl_hw.h" |
| 18 | #include "dsi_ctrl_reg.h" |
| 19 | #include "dsi_hw.h" |
Sandeep Panda | a2a3c8c | 2017-07-09 02:10:44 +0530 | [diff] [blame] | 20 | #include "dsi_catalog.h" |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 21 | |
| 22 | /* Equivalent to register DISP_CC_MISC_CMD */ |
| 23 | #define DISP_CC_CLAMP_REG_OFF 0x00 |
| 24 | |
Sandeep Panda | a2a3c8c | 2017-07-09 02:10:44 +0530 | [diff] [blame] | 25 | /* register to configure DMA scheduling */ |
| 26 | #define DSI_DMA_SCHEDULE_CTRL 0x100 |
| 27 | |
Shashank Babu Chinta Venkata | afef820 | 2017-04-21 13:49:56 -0700 | [diff] [blame] | 28 | /** |
| 29 | * dsi_ctrl_hw_22_phy_reset_config() - to configure clamp control during ulps |
| 30 | * @ctrl: Pointer to the controller host hardware. |
| 31 | * @enable: boolean to specify enable/disable. |
| 32 | */ |
| 33 | void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl, |
| 34 | bool enable) |
| 35 | { |
| 36 | u32 reg = 0; |
| 37 | |
| 38 | reg = DSI_DISP_CC_R32(ctrl, DISP_CC_CLAMP_REG_OFF); |
| 39 | |
| 40 | /* Mask/unmask disable PHY reset bit */ |
| 41 | if (enable) |
| 42 | reg &= ~BIT(ctrl->index); |
| 43 | else |
| 44 | reg |= BIT(ctrl->index); |
| 45 | DSI_DISP_CC_W32(ctrl, DISP_CC_CLAMP_REG_OFF, reg); |
| 46 | } |
Sandeep Panda | a2a3c8c | 2017-07-09 02:10:44 +0530 | [diff] [blame] | 47 | |
| 48 | /** |
| 49 | * dsi_ctrl_hw_22_schedule_dma_cmd() - to schedule DMA command transfer |
| 50 | * @ctrl: Pointer to the controller host hardware. |
| 51 | * @line_no: Line number at which command needs to be sent. |
| 52 | */ |
| 53 | void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_no) |
| 54 | { |
| 55 | u32 reg = 0; |
| 56 | |
| 57 | reg = DSI_R32(ctrl, DSI_DMA_SCHEDULE_CTRL); |
| 58 | reg |= BIT(28); |
| 59 | reg |= (line_no & 0xffff); |
| 60 | |
| 61 | DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, reg); |
| 62 | } |
Shashank Babu Chinta Venkata | 7d60873 | 2017-05-31 14:10:26 -0700 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * dsi_ctrl_hw_22_get_cont_splash_status() - to verify whether continuous |
| 66 | * splash is enabled or not |
| 67 | * @ctrl: Pointer to the controller host hardware. |
| 68 | * |
| 69 | * Return: Return Continuous splash status |
| 70 | */ |
| 71 | bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl) |
| 72 | { |
| 73 | u32 reg = 0; |
| 74 | |
| 75 | /** |
| 76 | * DSI scratch register 1 is used to notify whether continuous |
| 77 | * splash is enabled or not by bootloader |
| 78 | */ |
| 79 | reg = DSI_R32(ctrl, DSI_SCRATCH_REGISTER_1); |
| 80 | return reg == 0x1 ? true : false; |
| 81 | } |
Vara Reddy | dbeab89 | 2017-11-17 16:38:16 -0800 | [diff] [blame] | 82 | |
| 83 | /* |
| 84 | * dsi_ctrl_hw_kickoff_non_embedded_mode()-Kickoff cmd in non-embedded mode |
| 85 | * @ctrl: - Pointer to the controller host hardware. |
| 86 | * @dsi_ctrl_cmd_dma_info: - command buffer information. |
| 87 | * @flags: - DSI CTRL Flags. |
| 88 | */ |
| 89 | void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl, |
| 90 | struct dsi_ctrl_cmd_dma_info *cmd, |
| 91 | u32 flags) |
| 92 | { |
| 93 | u32 reg = 0; |
| 94 | |
| 95 | reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL); |
| 96 | |
| 97 | reg &= ~BIT(31);/* disable broadcast */ |
| 98 | reg &= ~BIT(30); |
| 99 | |
| 100 | if (cmd->use_lpm) |
| 101 | reg |= BIT(26); |
| 102 | else |
| 103 | reg &= ~BIT(26); |
| 104 | |
| 105 | /* Select non EMBEDDED_MODE, pick the packet header from register */ |
| 106 | reg &= ~BIT(28); |
| 107 | reg |= BIT(24);/* long packet */ |
| 108 | reg |= BIT(29);/* wc_sel = 1 */ |
| 109 | reg |= (((cmd->datatype) & 0x03f) << 16);/* data type */ |
| 110 | DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg); |
| 111 | |
| 112 | /* Enable WRITE_WATERMARK_DISABLE and READ_WATERMARK_DISABLE bits */ |
| 113 | reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL); |
| 114 | reg |= BIT(20); |
| 115 | reg |= BIT(16); |
Vara Reddy | 7393abe | 2017-11-29 09:47:10 -0800 | [diff] [blame] | 116 | reg |= 0x33;/* Set READ and WRITE watermark levels to maximum */ |
Vara Reddy | dbeab89 | 2017-11-17 16:38:16 -0800 | [diff] [blame] | 117 | DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg); |
| 118 | |
| 119 | DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset); |
| 120 | DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, ((cmd->length) & 0xFFFFFF)); |
| 121 | |
| 122 | /* wait for writes to complete before kick off */ |
| 123 | wmb(); |
| 124 | |
| 125 | if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER)) |
| 126 | DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1); |
| 127 | } |