| Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 1 | /* |
| Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
| Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef _DSI_CTRL_REG_H_ |
| 16 | #define _DSI_CTRL_REG_H_ |
| 17 | |
| 18 | #define DSI_HW_VERSION (0x0000) |
| 19 | #define DSI_CTRL (0x0004) |
| 20 | #define DSI_STATUS (0x0008) |
| 21 | #define DSI_FIFO_STATUS (0x000C) |
| 22 | #define DSI_VIDEO_MODE_CTRL (0x0010) |
| 23 | #define DSI_VIDEO_MODE_SYNC_DATATYPE (0x0014) |
| 24 | #define DSI_VIDEO_MODE_PIXEL_DATATYPE (0x0018) |
| 25 | #define DSI_VIDEO_MODE_BLANKING_DATATYPE (0x001C) |
| 26 | #define DSI_VIDEO_MODE_DATA_CTRL (0x0020) |
| 27 | #define DSI_VIDEO_MODE_ACTIVE_H (0x0024) |
| 28 | #define DSI_VIDEO_MODE_ACTIVE_V (0x0028) |
| 29 | #define DSI_VIDEO_MODE_TOTAL (0x002C) |
| 30 | #define DSI_VIDEO_MODE_HSYNC (0x0030) |
| 31 | #define DSI_VIDEO_MODE_VSYNC (0x0034) |
| 32 | #define DSI_VIDEO_MODE_VSYNC_VPOS (0x0038) |
| 33 | #define DSI_COMMAND_MODE_DMA_CTRL (0x003C) |
| 34 | #define DSI_COMMAND_MODE_MDP_CTRL (0x0040) |
| 35 | #define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL (0x0044) |
| 36 | #define DSI_DMA_CMD_OFFSET (0x0048) |
| 37 | #define DSI_DMA_CMD_LENGTH (0x004C) |
| 38 | #define DSI_DMA_FIFO_CTRL (0x0050) |
| 39 | #define DSI_DMA_NULL_PACKET_DATA (0x0054) |
| 40 | #define DSI_COMMAND_MODE_MDP_STREAM0_CTRL (0x0058) |
| 41 | #define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL (0x005C) |
| 42 | #define DSI_COMMAND_MODE_MDP_STREAM1_CTRL (0x0060) |
| 43 | #define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL (0x0064) |
| 44 | #define DSI_ACK_ERR_STATUS (0x0068) |
| 45 | #define DSI_RDBK_DATA0 (0x006C) |
| 46 | #define DSI_RDBK_DATA1 (0x0070) |
| 47 | #define DSI_RDBK_DATA2 (0x0074) |
| 48 | #define DSI_RDBK_DATA3 (0x0078) |
| 49 | #define DSI_RDBK_DATATYPE0 (0x007C) |
| 50 | #define DSI_RDBK_DATATYPE1 (0x0080) |
| 51 | #define DSI_TRIG_CTRL (0x0084) |
| 52 | #define DSI_EXT_MUX (0x0088) |
| 53 | #define DSI_EXT_MUX_TE_PULSE_DETECT_CTRL (0x008C) |
| 54 | #define DSI_CMD_MODE_DMA_SW_TRIGGER (0x0090) |
| 55 | #define DSI_CMD_MODE_MDP_SW_TRIGGER (0x0094) |
| 56 | #define DSI_CMD_MODE_BTA_SW_TRIGGER (0x0098) |
| 57 | #define DSI_RESET_SW_TRIGGER (0x009C) |
| 58 | #define DSI_MISR_CMD_CTRL (0x00A0) |
| 59 | #define DSI_MISR_VIDEO_CTRL (0x00A4) |
| 60 | #define DSI_LANE_STATUS (0x00A8) |
| 61 | #define DSI_LANE_CTRL (0x00AC) |
| 62 | #define DSI_LANE_SWAP_CTRL (0x00B0) |
| 63 | #define DSI_DLN0_PHY_ERR (0x00B4) |
| 64 | #define DSI_LP_TIMER_CTRL (0x00B8) |
| 65 | #define DSI_HS_TIMER_CTRL (0x00BC) |
| 66 | #define DSI_TIMEOUT_STATUS (0x00C0) |
| 67 | #define DSI_CLKOUT_TIMING_CTRL (0x00C4) |
| 68 | #define DSI_EOT_PACKET (0x00C8) |
| 69 | #define DSI_EOT_PACKET_CTRL (0x00CC) |
| 70 | #define DSI_GENERIC_ESC_TX_TRIGGER (0x00D0) |
| 71 | #define DSI_CAM_BIST_CTRL (0x00D4) |
| 72 | #define DSI_CAM_BIST_FRAME_SIZE (0x00D8) |
| 73 | #define DSI_CAM_BIST_BLOCK_SIZE (0x00DC) |
| 74 | #define DSI_CAM_BIST_FRAME_CONFIG (0x00E0) |
| 75 | #define DSI_CAM_BIST_LSFR_CTRL (0x00E4) |
| 76 | #define DSI_CAM_BIST_LSFR_INIT (0x00E8) |
| 77 | #define DSI_CAM_BIST_START (0x00EC) |
| 78 | #define DSI_CAM_BIST_STATUS (0x00F0) |
| 79 | #define DSI_ERR_INT_MASK0 (0x010C) |
| 80 | #define DSI_INT_CTRL (0x0110) |
| 81 | #define DSI_IOBIST_CTRL (0x0114) |
| 82 | #define DSI_SOFT_RESET (0x0118) |
| 83 | #define DSI_CLK_CTRL (0x011C) |
| 84 | #define DSI_CLK_STATUS (0x0120) |
| Dhaval Patel | f9f3ffe | 2017-08-16 16:03:10 -0700 | [diff] [blame] | 85 | #define DSI_DEBUG_BUS_CTL (0x0124) |
| 86 | #define DSI_DEBUG_BUS_STATUS (0x0128) |
| Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 87 | #define DSI_PHY_SW_RESET (0x012C) |
| 88 | #define DSI_AXI2AHB_CTRL (0x0130) |
| 89 | #define DSI_MISR_CMD_MDP0_32BIT (0x0134) |
| 90 | #define DSI_MISR_CMD_MDP1_32BIT (0x0138) |
| 91 | #define DSI_MISR_CMD_DMA_32BIT (0x013C) |
| 92 | #define DSI_MISR_VIDEO_32BIT (0x0140) |
| 93 | #define DSI_LANE_MISR_CTRL (0x0144) |
| 94 | #define DSI_LANE0_MISR (0x0148) |
| 95 | #define DSI_LANE1_MISR (0x014C) |
| 96 | #define DSI_LANE2_MISR (0x0150) |
| 97 | #define DSI_LANE3_MISR (0x0154) |
| 98 | #define DSI_TEST_PATTERN_GEN_CTRL (0x015C) |
| 99 | #define DSI_TEST_PATTERN_GEN_VIDEO_POLY (0x0160) |
| 100 | #define DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL (0x0164) |
| 101 | #define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM0_POLY (0x0168) |
| 102 | #define DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 (0x016C) |
| 103 | #define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM1_POLY (0x0170) |
| 104 | #define DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL1 (0x0174) |
| 105 | #define DSI_TEST_PATTERN_GEN_CMD_DMA_POLY (0x0178) |
| 106 | #define DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL (0x017C) |
| 107 | #define DSI_TEST_PATTERN_GEN_VIDEO_ENABLE (0x0180) |
| 108 | #define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER (0x0184) |
| 109 | #define DSI_TEST_PATTERN_GEN_CMD_STREAM1_TRIGGER (0x0188) |
| 110 | #define DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL2 (0x018C) |
| 111 | #define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM2_POLY (0x0190) |
| 112 | #define DSI_TEST_PATTERN_GEN_CMD_MDP_STREAM2_POLY (0x0190) |
| 113 | #define DSI_COMMAND_MODE_MDP_IDLE_CTRL (0x0194) |
| 114 | #define DSI_TEST_PATTERN_GEN_CMD_STREAM2_TRIGGER (0x0198) |
| 115 | #define DSI_TPG_MAIN_CONTROL (0x019C) |
| 116 | #define DSI_TPG_MAIN_CONTROL2 (0x01A0) |
| 117 | #define DSI_TPG_VIDEO_CONFIG (0x01A4) |
| 118 | #define DSI_TPG_COMPONENT_LIMITS (0x01A8) |
| 119 | #define DSI_TPG_RECTANGLE (0x01AC) |
| 120 | #define DSI_TPG_BLACK_WHITE_PATTERN_FRAMES (0x01B0) |
| 121 | #define DSI_TPG_RGB_MAPPING (0x01B4) |
| 122 | #define DSI_COMMAND_MODE_MDP_CTRL2 (0x01B8) |
| 123 | #define DSI_COMMAND_MODE_MDP_STREAM2_CTRL (0x01BC) |
| 124 | #define DSI_COMMAND_MODE_MDP_STREAM2_TOTAL (0x01C0) |
| 125 | #define DSI_MISR_CMD_MDP2_8BIT (0x01C4) |
| 126 | #define DSI_MISR_CMD_MDP2_32BIT (0x01C8) |
| 127 | #define DSI_VBIF_CTRL (0x01CC) |
| 128 | #define DSI_AES_CTRL (0x01D0) |
| 129 | #define DSI_RDBK_DATA_CTRL (0x01D4) |
| 130 | #define DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL2 (0x01D8) |
| 131 | #define DSI_TPG_DMA_FIFO_STATUS (0x01DC) |
| 132 | #define DSI_TPG_DMA_FIFO_WRITE_TRIGGER (0x01E0) |
| 133 | #define DSI_DSI_TIMING_FLUSH (0x01E4) |
| 134 | #define DSI_DSI_TIMING_DB_MODE (0x01E8) |
| 135 | #define DSI_TPG_DMA_FIFO_RESET (0x01EC) |
| 136 | #define DSI_SCRATCH_REGISTER_0 (0x01F0) |
| 137 | #define DSI_VERSION (0x01F4) |
| 138 | #define DSI_SCRATCH_REGISTER_1 (0x01F8) |
| 139 | #define DSI_SCRATCH_REGISTER_2 (0x01FC) |
| 140 | #define DSI_DYNAMIC_REFRESH_CTRL (0x0200) |
| 141 | #define DSI_DYNAMIC_REFRESH_PIPE_DELAY (0x0204) |
| 142 | #define DSI_DYNAMIC_REFRESH_PIPE_DELAY2 (0x0208) |
| 143 | #define DSI_DYNAMIC_REFRESH_PLL_DELAY (0x020C) |
| 144 | #define DSI_DYNAMIC_REFRESH_STATUS (0x0210) |
| 145 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL0 (0x0214) |
| 146 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL1 (0x0218) |
| 147 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL2 (0x021C) |
| 148 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL3 (0x0220) |
| 149 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL4 (0x0224) |
| 150 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL5 (0x0228) |
| 151 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL6 (0x022C) |
| 152 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL7 (0x0230) |
| 153 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL8 (0x0234) |
| 154 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL9 (0x0238) |
| 155 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL10 (0x023C) |
| 156 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL11 (0x0240) |
| 157 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL12 (0x0244) |
| 158 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL13 (0x0248) |
| 159 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL14 (0x024C) |
| 160 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL15 (0x0250) |
| 161 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL16 (0x0254) |
| 162 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL17 (0x0258) |
| 163 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL18 (0x025C) |
| 164 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL19 (0x0260) |
| 165 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL20 (0x0264) |
| 166 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL21 (0x0268) |
| 167 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL22 (0x026C) |
| 168 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL23 (0x0270) |
| 169 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL24 (0x0274) |
| 170 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL25 (0x0278) |
| 171 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL26 (0x027C) |
| 172 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL27 (0x0280) |
| 173 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL28 (0x0284) |
| 174 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL29 (0x0288) |
| 175 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL30 (0x028C) |
| 176 | #define DSI_DYNAMIC_REFRESH_PLL_CTRL31 (0x0290) |
| 177 | #define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR (0x0294) |
| 178 | #define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2 (0x0298) |
| 179 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL (0x02A0) |
| 180 | #define DSI_VIDEO_COMPRESSION_MODE_CTRL2 (0x02A4) |
| 181 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL (0x02A8) |
| 182 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL2 (0x02AC) |
| 183 | #define DSI_COMMAND_COMPRESSION_MODE_CTRL3 (0x02B0) |
| 184 | #define DSI_COMMAND_MODE_NULL_INSERTION_CTRL (0x02B4) |
| 185 | #define DSI_READ_BACK_DISABLE_STATUS (0x02B8) |
| 186 | #define DSI_DESKEW_CTRL (0x02BC) |
| 187 | #define DSI_DESKEW_DELAY_CTRL (0x02C0) |
| 188 | #define DSI_DESKEW_SW_TRIGGER (0x02C4) |
| Dhaval Patel | abfaa08 | 2017-07-28 12:41:10 -0700 | [diff] [blame] | 189 | #define DSI_DEBUG_CTRL (0x02C8) |
| Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 190 | #define DSI_SECURE_DISPLAY_STATUS (0x02CC) |
| 191 | #define DSI_SECURE_DISPLAY_BLOCK_COMMAND_COLOR (0x02D0) |
| 192 | #define DSI_SECURE_DISPLAY_BLOCK_VIDEO_COLOR (0x02D4) |
| Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 193 | #define DSI_LOGICAL_LANE_SWAP_CTRL (0x0310) |
| Ajay Singh Parmar | 7509888 | 2016-05-16 17:43:17 -0700 | [diff] [blame] | 194 | |
| 195 | |
| 196 | #endif /* _DSI_CTRL_REG_H_ */ |