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gerrit-public.fairphone.software / kernel / msm-4.9 / 3afabc363becc3fa9505f37cd9ba23acbdfac8e1 / . / drivers / gpu / drm / msm / dsi-staging / dsi_phy_timing_calc.h
blob: bae6d0535aba66aeb02b96b1921eb33a9afc5f6b [file] [log] [blame]
Padmanabhan Komanduru56611ef2016-12-19 12:21:11 +0530[diff] [blame]1/*
2 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DSI_PHY_TIMING_CALC_H_
15#define _DSI_PHY_TIMING_CALC_H_
16
17#include <linux/math64.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/slab.h>
21#include <linux/bitops.h>
22#include <linux/bitmap.h>
23#include <linux/errno.h>
24
25#include "dsi_defs.h"
26#include "dsi_phy_hw.h"
27#include "dsi_catalog.h"
28
29/**
30 * struct timing_entry - Calculated values for each timing parameter.
31 * @mipi_min:
32 * @mipi_max:
33 * @rec_min:
34 * @rec_max:
35 * @rec:
36 * @reg_value: Value to be programmed in register.
37 */
38struct timing_entry {
39 s32 mipi_min;
40 s32 mipi_max;
41 s32 rec_min;
42 s32 rec_max;
43 s32 rec;
44 u8 reg_value;
45};
46
47/**
48 * struct phy_timing_desc - Timing parameters for DSI PHY.
49 */
50struct phy_timing_desc {
51 struct timing_entry clk_prepare;
52 struct timing_entry clk_zero;
53 struct timing_entry clk_trail;
54 struct timing_entry hs_prepare;
55 struct timing_entry hs_zero;
56 struct timing_entry hs_trail;
57 struct timing_entry hs_rqst;
58 struct timing_entry hs_rqst_clk;
59 struct timing_entry hs_exit;
60 struct timing_entry ta_go;
61 struct timing_entry ta_sure;
62 struct timing_entry ta_set;
63 struct timing_entry clk_post;
64 struct timing_entry clk_pre;
65};
66
67/**
68 * struct phy_clk_params - Clock parameters for PHY timing calculations.
69 */
70struct phy_clk_params {
71 u32 bitclk_mbps;
72 u32 escclk_numer;
73 u32 escclk_denom;
74 u32 tlpx_numer_ns;
75 u32 treot_ns;
76 u32 clk_prep_buf;
77 u32 clk_zero_buf;
78 u32 clk_trail_buf;
79 u32 hs_prep_buf;
80 u32 hs_zero_buf;
81 u32 hs_trail_buf;
82 u32 hs_rqst_buf;
83 u32 hs_exit_buf;
84};
85
86/**
87 * Various Ops needed for auto-calculation of DSI PHY timing parameters.
88 */
89struct phy_timing_ops {
90 void (*get_default_phy_params)(struct phy_clk_params *params);
91
92 int32_t (*calc_clk_zero)(s64 rec_temp1, s64 mult);
93
94 int32_t (*calc_clk_trail_rec_min)(s64 temp_mul,
95 s64 frac, s64 mult);
96
97 int32_t (*calc_clk_trail_rec_max)(s64 temp1, s64 mult);
98
99 int32_t (*calc_hs_zero)(s64 temp1, s64 mult);
100
101 void (*calc_hs_trail)(struct phy_clk_params *clk_params,
102 struct phy_timing_desc *desc);
103
104 void (*update_timing_params)(struct dsi_phy_per_lane_cfgs *timing,
105 struct phy_timing_desc *desc);
106};
107
108/* DSI PHY timing functions for 14nm */
109void dsi_phy_hw_v2_0_get_default_phy_params(struct phy_clk_params *params);
110
111int32_t dsi_phy_hw_v2_0_calc_clk_zero(s64 rec_temp1, s64 mult);
112
113int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_min(s64 temp_mul,
114 s64 frac, s64 mult);
115
116int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_max(s64 temp1, s64 mult);
117
118int32_t dsi_phy_hw_v2_0_calc_hs_zero(s64 temp1, s64 mult);
119
120void dsi_phy_hw_v2_0_calc_hs_trail(struct phy_clk_params *clk_params,
121 struct phy_timing_desc *desc);
122
123void dsi_phy_hw_v2_0_update_timing_params(struct dsi_phy_per_lane_cfgs *timing,
124 struct phy_timing_desc *desc);
125
126/* DSI PHY timing functions for 10nm */
127void dsi_phy_hw_v3_0_get_default_phy_params(struct phy_clk_params *params);
128
129int32_t dsi_phy_hw_v3_0_calc_clk_zero(s64 rec_temp1, s64 mult);
130
131int32_t dsi_phy_hw_v3_0_calc_clk_trail_rec_min(s64 temp_mul,
132 s64 frac, s64 mult);
133
134int32_t dsi_phy_hw_v3_0_calc_clk_trail_rec_max(s64 temp1, s64 mult);
135
136int32_t dsi_phy_hw_v3_0_calc_hs_zero(s64 temp1, s64 mult);
137
138void dsi_phy_hw_v3_0_calc_hs_trail(struct phy_clk_params *clk_params,
139 struct phy_timing_desc *desc);
140
141void dsi_phy_hw_v3_0_update_timing_params(struct dsi_phy_per_lane_cfgs *timing,
142 struct phy_timing_desc *desc);
143
144#endif /* _DSI_PHY_TIMING_CALC_H_ */