Padmanabhan Komanduru | 56611ef | 2016-12-19 12:21:11 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "dsi-phy-timing:" fmt |
| 15 | #include "dsi_phy_timing_calc.h" |
| 16 | |
| 17 | void dsi_phy_hw_v2_0_get_default_phy_params(struct phy_clk_params *params) |
| 18 | { |
| 19 | params->clk_prep_buf = 50; |
| 20 | params->clk_zero_buf = 2; |
| 21 | params->clk_trail_buf = 30; |
| 22 | params->hs_prep_buf = 50; |
| 23 | params->hs_zero_buf = 10; |
| 24 | params->hs_trail_buf = 30; |
| 25 | params->hs_rqst_buf = 0; |
| 26 | params->hs_exit_buf = 10; |
| 27 | } |
| 28 | |
| 29 | int32_t dsi_phy_hw_v2_0_calc_clk_zero(s64 rec_temp1, s64 mult) |
| 30 | { |
| 31 | s64 rec_temp2, rec_temp3; |
| 32 | |
| 33 | rec_temp2 = (rec_temp1 - (11 * mult)); |
| 34 | rec_temp3 = roundup(div_s64(rec_temp2, 8), mult); |
| 35 | return (div_s64(rec_temp3, mult) - 3); |
| 36 | } |
| 37 | |
| 38 | int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_min(s64 temp_mul, |
| 39 | s64 frac, s64 mult) |
| 40 | { |
| 41 | s64 rec_temp1, rec_temp2, rec_temp3; |
| 42 | |
| 43 | rec_temp1 = temp_mul + frac + (3 * mult); |
| 44 | rec_temp2 = div_s64(rec_temp1, 8); |
| 45 | rec_temp3 = roundup(rec_temp2, mult); |
| 46 | |
| 47 | return div_s64(rec_temp3, mult); |
| 48 | } |
| 49 | |
| 50 | int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_max(s64 temp1, s64 mult) |
| 51 | { |
| 52 | s64 rec_temp2, rec_temp3; |
| 53 | |
| 54 | rec_temp2 = temp1 + (3 * mult); |
| 55 | rec_temp3 = rec_temp2 / 8; |
| 56 | return div_s64(rec_temp3, mult); |
| 57 | |
| 58 | } |
| 59 | |
| 60 | int32_t dsi_phy_hw_v2_0_calc_hs_zero(s64 temp1, s64 mult) |
| 61 | { |
| 62 | s64 rec_temp2, rec_temp3, rec_min; |
| 63 | |
| 64 | rec_temp2 = temp1 - (11 * mult); |
| 65 | rec_temp3 = roundup((rec_temp2 / 8), mult); |
| 66 | rec_min = rec_temp3 - (3 * mult); |
| 67 | return div_s64(rec_min, mult); |
| 68 | } |
| 69 | |
| 70 | void dsi_phy_hw_v2_0_calc_hs_trail(struct phy_clk_params *clk_params, |
| 71 | struct phy_timing_desc *desc) |
| 72 | { |
| 73 | s64 rec_temp1; |
| 74 | struct timing_entry *t = &desc->hs_trail; |
| 75 | |
| 76 | t->rec_min = DIV_ROUND_UP( |
| 77 | ((t->mipi_min * clk_params->bitclk_mbps) + |
| 78 | (3 * clk_params->tlpx_numer_ns)), |
| 79 | (8 * clk_params->tlpx_numer_ns)); |
| 80 | |
| 81 | rec_temp1 = ((t->mipi_max * clk_params->bitclk_mbps) + |
| 82 | (3 * clk_params->tlpx_numer_ns)); |
| 83 | t->rec_max = (rec_temp1 / (8 * clk_params->tlpx_numer_ns)); |
| 84 | } |
| 85 | |
| 86 | void dsi_phy_hw_v2_0_update_timing_params( |
| 87 | struct dsi_phy_per_lane_cfgs *timing, |
| 88 | struct phy_timing_desc *desc) |
| 89 | { |
| 90 | int i = 0; |
| 91 | |
| 92 | for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) { |
| 93 | timing->lane[i][0] = desc->hs_exit.reg_value; |
| 94 | |
| 95 | if (i == DSI_LOGICAL_CLOCK_LANE) |
| 96 | timing->lane[i][1] = desc->clk_zero.reg_value; |
| 97 | else |
| 98 | timing->lane[i][1] = desc->hs_zero.reg_value; |
| 99 | |
| 100 | if (i == DSI_LOGICAL_CLOCK_LANE) |
| 101 | timing->lane[i][2] = desc->clk_prepare.reg_value; |
| 102 | else |
| 103 | timing->lane[i][2] = desc->hs_prepare.reg_value; |
| 104 | |
| 105 | if (i == DSI_LOGICAL_CLOCK_LANE) |
| 106 | timing->lane[i][3] = desc->clk_trail.reg_value; |
| 107 | else |
| 108 | timing->lane[i][3] = desc->hs_trail.reg_value; |
| 109 | |
| 110 | if (i == DSI_LOGICAL_CLOCK_LANE) |
| 111 | timing->lane[i][4] = desc->hs_rqst_clk.reg_value; |
| 112 | else |
| 113 | timing->lane[i][4] = desc->hs_rqst.reg_value; |
| 114 | |
| 115 | timing->lane[i][5] = 0x3; |
| 116 | timing->lane[i][6] = 0x4; |
| 117 | timing->lane[i][7] = 0xA0; |
| 118 | pr_debug("[%d][%d %d %d %d %d]\n", i, timing->lane[i][0], |
| 119 | timing->lane[i][1], |
| 120 | timing->lane[i][2], |
| 121 | timing->lane[i][3], |
| 122 | timing->lane[i][4]); |
| 123 | } |
| 124 | timing->count_per_lane = 8; |
| 125 | } |
| 126 | |