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gerrit-public.fairphone.software / kernel / msm-4.9 / 3b12308f3337c09b424a2b9cf73c2c06521abe7e / . / arch / mips / ath25 / ar5312.c
blob: c2adaf2cd73a116bd175ff367f545bfe68ecf3cb [file] [log] [blame]
Sergey Ryazanov3b12308f2014-10-29 03:18:39 +0400[diff] [blame^]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
11 */
12
13/*
14 * Platform devices for Atheros AR5312 SoCs
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/reboot.h>
20#include <asm/bootinfo.h>
21#include <asm/reboot.h>
22#include <asm/time.h>
23
24#include "devices.h"
25#include "ar5312.h"
26#include "ar5312_regs.h"
27
28static void __iomem *ar5312_rst_base;
29
30static inline u32 ar5312_rst_reg_read(u32 reg)
31{
32 return __raw_readl(ar5312_rst_base + reg);
33}
34
35static inline void ar5312_rst_reg_write(u32 reg, u32 val)
36{
37 __raw_writel(val, ar5312_rst_base + reg);
38}
39
40static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
41{
42 u32 ret = ar5312_rst_reg_read(reg);
43
44 ret &= ~mask;
45 ret |= val;
46 ar5312_rst_reg_write(reg, ret);
47}
48
49static void ar5312_restart(char *command)
50{
51 /* reset the system */
52 local_irq_disable();
53 while (1)
54 ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
55}
56
57/*
58 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
59 * to determine the predevisor value.
60 */
61static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
62
63static unsigned __init ar5312_cpu_frequency(void)
64{
65 u32 scratch, devid, clock_ctl1;
66 u32 predivide_mask, multiplier_mask, doubler_mask;
67 unsigned predivide_shift, multiplier_shift;
68 unsigned predivide_select, predivisor, multiplier;
69
70 /* Trust the bootrom's idea of cpu frequency. */
71 scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
72 if (scratch)
73 return scratch;
74
75 devid = ar5312_rst_reg_read(AR5312_REV);
76 devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
77 if (devid == AR5312_REV_MAJ_AR2313) {
78 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
79 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
80 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
81 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
82 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
83 } else { /* AR5312 and AR2312 */
84 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
85 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
86 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
87 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
88 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
89 }
90
91 /*
92 * Clocking is derived from a fixed 40MHz input clock.
93 *
94 * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
95 * sys_freq = cpu_freq / 4 (used for APB clock, serial,
96 * flash, Timer, Watchdog Timer)
97 *
98 * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
99 *
100 * So, for example, with a PLL multiplier of 5, we have
101 *
102 * cpu_freq = 200MHz
103 * sys_freq = 50MHz
104 * cnt_freq = 100MHz
105 *
106 * We compute the CPU frequency, based on PLL settings.
107 */
108
109 clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
110 predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
111 predivisor = clockctl1_predivide_table[predivide_select];
112 multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
113
114 if (clock_ctl1 & doubler_mask)
115 multiplier <<= 1;
116
117 return (40000000 / predivisor) * multiplier;
118}
119
120static inline unsigned ar5312_sys_frequency(void)
121{
122 return ar5312_cpu_frequency() / 4;
123}
124
125void __init ar5312_plat_time_init(void)
126{
127 mips_hpt_frequency = ar5312_cpu_frequency() / 2;
128}
129
130void __init ar5312_plat_mem_setup(void)
131{
132 void __iomem *sdram_base;
133 u32 memsize, memcfg, bank0_ac, bank1_ac;
134
135 /* Detect memory size */
136 sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
137 AR5312_SDRAMCTL_SIZE);
138 memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
139 bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
140 bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
141 memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
142 (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
143 memsize <<= 20;
144 add_memory_region(0, memsize, BOOT_MEM_RAM);
145 iounmap(sdram_base);
146
147 ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
148
149 /* Clear any lingering AHB errors */
150 ar5312_rst_reg_read(AR5312_PROCADDR);
151 ar5312_rst_reg_read(AR5312_DMAADDR);
152 ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
153
154 _machine_restart = ar5312_restart;
155}