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Mike Turquette9d9f78e2012-03-15 23:11:20 -07001/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Simple multiplexer clock implementation
11 */
12
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/module.h>
16#include <linux/slab.h>
17#include <linux/io.h>
18#include <linux/err.h>
19
20/*
21 * DOC: basic adjustable multiplexer clock that cannot gate
22 *
23 * Traits of this clock:
24 * prepare - clk_prepare only ensures that parents are prepared
25 * enable - clk_enable only ensures that parents are enabled
26 * rate - rate is only affected by parent switching. No clk_set_rate support
27 * parent - parent is adjustable through clk_set_parent
28 */
29
30#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
31
32static u8 clk_mux_get_parent(struct clk_hw *hw)
33{
34 struct clk_mux *mux = to_clk_mux(hw);
Peter De Schrijverce4f3312013-03-22 14:07:53 +020035 int num_parents = __clk_get_num_parents(hw->clk);
Mike Turquette9d9f78e2012-03-15 23:11:20 -070036 u32 val;
37
38 /*
39 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
40 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
41 * to 0x7 (index starts at one)
42 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
43 * val = 0x4 really means "bit 2, index starts at bit 0"
44 */
Gerhard Sittigaa514ce2013-07-22 14:14:40 +020045 val = clk_readl(mux->reg) >> mux->shift;
Peter De Schrijverce4f3312013-03-22 14:07:53 +020046 val &= mux->mask;
47
48 if (mux->table) {
49 int i;
50
51 for (i = 0; i < num_parents; i++)
52 if (mux->table[i] == val)
53 return i;
54 return -EINVAL;
55 }
Mike Turquette9d9f78e2012-03-15 23:11:20 -070056
57 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
58 val = ffs(val) - 1;
59
60 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
61 val--;
62
Peter De Schrijverce4f3312013-03-22 14:07:53 +020063 if (val >= num_parents)
Mike Turquette9d9f78e2012-03-15 23:11:20 -070064 return -EINVAL;
65
66 return val;
67}
Mike Turquette9d9f78e2012-03-15 23:11:20 -070068
69static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
70{
71 struct clk_mux *mux = to_clk_mux(hw);
72 u32 val;
73 unsigned long flags = 0;
74
Peter De Schrijverce4f3312013-03-22 14:07:53 +020075 if (mux->table)
76 index = mux->table[index];
Mike Turquette9d9f78e2012-03-15 23:11:20 -070077
Peter De Schrijverce4f3312013-03-22 14:07:53 +020078 else {
79 if (mux->flags & CLK_MUX_INDEX_BIT)
Hans de Goede6793b3c2014-11-19 14:48:59 +010080 index = 1 << index;
Peter De Schrijverce4f3312013-03-22 14:07:53 +020081
82 if (mux->flags & CLK_MUX_INDEX_ONE)
83 index++;
84 }
Mike Turquette9d9f78e2012-03-15 23:11:20 -070085
86 if (mux->lock)
87 spin_lock_irqsave(mux->lock, flags);
88
Haojian Zhuangba492e92013-06-08 22:47:17 +080089 if (mux->flags & CLK_MUX_HIWORD_MASK) {
90 val = mux->mask << (mux->shift + 16);
91 } else {
Gerhard Sittigaa514ce2013-07-22 14:14:40 +020092 val = clk_readl(mux->reg);
Haojian Zhuangba492e92013-06-08 22:47:17 +080093 val &= ~(mux->mask << mux->shift);
94 }
Mike Turquette9d9f78e2012-03-15 23:11:20 -070095 val |= index << mux->shift;
Gerhard Sittigaa514ce2013-07-22 14:14:40 +020096 clk_writel(val, mux->reg);
Mike Turquette9d9f78e2012-03-15 23:11:20 -070097
98 if (mux->lock)
99 spin_unlock_irqrestore(mux->lock, flags);
100
101 return 0;
102}
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700103
Shawn Guo822c2502012-03-27 15:23:22 +0800104const struct clk_ops clk_mux_ops = {
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700105 .get_parent = clk_mux_get_parent,
106 .set_parent = clk_mux_set_parent,
James Hogane366fdd2013-07-29 12:25:02 +0100107 .determine_rate = __clk_mux_determine_rate,
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700108};
109EXPORT_SYMBOL_GPL(clk_mux_ops);
110
Tomasz Figac57acd12013-07-23 01:49:18 +0200111const struct clk_ops clk_mux_ro_ops = {
112 .get_parent = clk_mux_get_parent,
113};
114EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
115
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200116struct clk *clk_register_mux_table(struct device *dev, const char *name,
Sascha Hauer2893c372015-03-31 20:16:52 +0200117 const char * const *parent_names, u8 num_parents,
118 unsigned long flags,
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200119 void __iomem *reg, u8 shift, u32 mask,
120 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700121{
122 struct clk_mux *mux;
Mike Turquette27d54592012-03-26 17:51:03 -0700123 struct clk *clk;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700124 struct clk_init_data init;
Haojian Zhuangba492e92013-06-08 22:47:17 +0800125 u8 width = 0;
126
127 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
128 width = fls(mask) - ffs(mask) + 1;
129 if (width + shift > 16) {
130 pr_err("mux value exceeds LOWORD field\n");
131 return ERR_PTR(-EINVAL);
132 }
133 }
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700134
Mike Turquette27d54592012-03-26 17:51:03 -0700135 /* allocate the mux */
Shawn Guo10363b52012-03-27 15:23:20 +0800136 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700137 if (!mux) {
138 pr_err("%s: could not allocate mux clk\n", __func__);
139 return ERR_PTR(-ENOMEM);
140 }
141
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700142 init.name = name;
Tomasz Figac57acd12013-07-23 01:49:18 +0200143 if (clk_mux_flags & CLK_MUX_READ_ONLY)
144 init.ops = &clk_mux_ro_ops;
145 else
146 init.ops = &clk_mux_ops;
Rajendra Nayakf7d8caa2012-06-01 14:02:47 +0530147 init.flags = flags | CLK_IS_BASIC;
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700148 init.parent_names = parent_names;
149 init.num_parents = num_parents;
150
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700151 /* struct clk_mux assignments */
152 mux->reg = reg;
153 mux->shift = shift;
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200154 mux->mask = mask;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700155 mux->flags = clk_mux_flags;
156 mux->lock = lock;
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200157 mux->table = table;
Mike Turquette31df9db2012-05-06 18:48:11 -0700158 mux->hw.init = &init;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700159
Saravana Kannan0197b3e2012-04-25 22:58:56 -0700160 clk = clk_register(dev, &mux->hw);
Mike Turquette27d54592012-03-26 17:51:03 -0700161
162 if (IS_ERR(clk))
163 kfree(mux);
164
165 return clk;
Mike Turquette9d9f78e2012-03-15 23:11:20 -0700166}
Mike Turquette5cfe10b2013-08-15 19:06:29 -0700167EXPORT_SYMBOL_GPL(clk_register_mux_table);
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200168
169struct clk *clk_register_mux(struct device *dev, const char *name,
Sascha Hauer2893c372015-03-31 20:16:52 +0200170 const char * const *parent_names, u8 num_parents,
171 unsigned long flags,
Peter De Schrijverce4f3312013-03-22 14:07:53 +0200172 void __iomem *reg, u8 shift, u8 width,
173 u8 clk_mux_flags, spinlock_t *lock)
174{
175 u32 mask = BIT(width) - 1;
176
177 return clk_register_mux_table(dev, name, parent_names, num_parents,
178 flags, reg, shift, mask, clk_mux_flags,
179 NULL, lock);
180}
Mike Turquette5cfe10b2013-08-15 19:06:29 -0700181EXPORT_SYMBOL_GPL(clk_register_mux);
Krzysztof Kozlowski4e3c0212015-01-05 10:52:40 +0100182
183void clk_unregister_mux(struct clk *clk)
184{
185 struct clk_mux *mux;
186 struct clk_hw *hw;
187
188 hw = __clk_get_hw(clk);
189 if (!hw)
190 return;
191
192 mux = to_clk_mux(hw);
193
194 clk_unregister(clk);
195 kfree(mux);
196}
197EXPORT_SYMBOL_GPL(clk_unregister_mux);