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Dhaval Patel49ef6d72017-03-26 09:35:53 -07001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef _SDE_RSC_PRIV_H_
15#define _SDE_RSC_PRIV_H_
16
17#include <linux/kernel.h>
18#include <linux/sde_io_util.h>
19#include <linux/sde_rsc.h>
20
21#include <soc/qcom/tcs.h>
22#include "sde_power_handle.h"
23
24#define SDE_RSC_COMPATIBLE "disp_rscc"
25
26#define MAX_RSC_COUNT 5
27
Dhaval Patel3d56f892017-05-05 12:21:08 -070028#define ALL_MODES_DISABLED 0x0
29#define ONLY_MODE_0_ENABLED 0x1
30#define ONLY_MODE_0_1_ENABLED 0x3
31#define ALL_MODES_ENABLED 0x7
32
33#define MAX_COUNT_SIZE_SUPPORTED 128
34
Dhaval Patel49ef6d72017-03-26 09:35:53 -070035struct sde_rsc_priv;
36
37/**
38 * rsc_mode_req: sde rsc mode request information
39 * MODE_READ: read vsync status
Dhaval Patel3d56f892017-05-05 12:21:08 -070040 * MODE_UPDATE: mode timeslot update
41 * 0x0: all modes are disabled.
42 * 0x1: Mode-0 is enabled and other two modes are disabled.
43 * 0x3: Mode-0 & Mode-1 are enabled and mode-2 is disabled.
44 * 0x7: all modes are enabled.
Dhaval Patel49ef6d72017-03-26 09:35:53 -070045 */
46enum rsc_mode_req {
47 MODE_READ,
Dhaval Patel3d56f892017-05-05 12:21:08 -070048 MODE_UPDATE = 0x1,
Dhaval Patel49ef6d72017-03-26 09:35:53 -070049};
50
51/**
52 * rsc_vsync_req: sde rsc vsync request information
53 * VSYNC_READ: read vsync status
Lloyd Atkinsonf68a2132017-07-17 10:16:30 -040054 * VSYNC_READ_VSYNC0: read value vsync0 timestamp (cast to int from u32)
Dhaval Patel49ef6d72017-03-26 09:35:53 -070055 * VSYNC_ENABLE: enable rsc wrapper vsync status
56 * VSYNC_DISABLE: disable rsc wrapper vsync status
57 */
58enum rsc_vsync_req {
59 VSYNC_READ,
Lloyd Atkinsonf68a2132017-07-17 10:16:30 -040060 VSYNC_READ_VSYNC0,
Dhaval Patel49ef6d72017-03-26 09:35:53 -070061 VSYNC_ENABLE,
62 VSYNC_DISABLE,
63};
64
65/**
66 * struct sde_rsc_hw_ops - sde resource state coordinator hardware ops
67 * @init: Initialize the sequencer, solver, qtimer,
68 etc. hardware blocks on RSC.
Dhaval Patelf9c5c602017-08-01 12:32:04 -070069 * @timer_update: update the static wrapper time and pdc/rsc
70 backoff time.
Dhaval Patel49ef6d72017-03-26 09:35:53 -070071 * @tcs_wait: Waits for TCS block OK to allow sending a
72 * TCS command.
73 * @hw_vsync: Enables the vsync on RSC block.
74 * @tcs_use_ok: set TCS set to high to allow RSC to use it.
Dhaval Patel49ef6d72017-03-26 09:35:53 -070075 * @is_amc_mode: Check current amc mode status
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -070076 * @debug_dump: dump debug bus registers or enable debug bus
Dhaval Patel49ef6d72017-03-26 09:35:53 -070077 * @state_update: Enable/override the solver based on rsc state
78 * status (command/video)
79 * @mode_show: shows current mode status, mode0/1/2
80 * @debug_show: Show current debug status.
81 */
82
83struct sde_rsc_hw_ops {
84 int (*init)(struct sde_rsc_priv *rsc);
Dhaval Patelf9c5c602017-08-01 12:32:04 -070085 int (*timer_update)(struct sde_rsc_priv *rsc);
Dhaval Patel49ef6d72017-03-26 09:35:53 -070086 int (*tcs_wait)(struct sde_rsc_priv *rsc);
87 int (*hw_vsync)(struct sde_rsc_priv *rsc, enum rsc_vsync_req request,
88 char *buffer, int buffer_size, u32 mode);
89 int (*tcs_use_ok)(struct sde_rsc_priv *rsc);
Dhaval Patel49ef6d72017-03-26 09:35:53 -070090 bool (*is_amc_mode)(struct sde_rsc_priv *rsc);
Dhaval Patelc5a2e5d2017-09-18 12:39:41 -070091 void (*debug_dump)(struct sde_rsc_priv *rsc, u32 mux_sel);
Dhaval Patel49ef6d72017-03-26 09:35:53 -070092 int (*state_update)(struct sde_rsc_priv *rsc, enum sde_rsc_state state);
93 int (*debug_show)(struct seq_file *s, struct sde_rsc_priv *rsc);
94 int (*mode_ctrl)(struct sde_rsc_priv *rsc, enum rsc_mode_req request,
Dhaval Patel3d56f892017-05-05 12:21:08 -070095 char *buffer, int buffer_size, u32 mode);
Dhaval Patel49ef6d72017-03-26 09:35:53 -070096};
97
98/**
99 * struct sde_rsc_timer_config: this is internal configuration between
100 * rsc and rsc_hw API.
101 *
102 * @static_wakeup_time_ns: wrapper backoff time in nano seconds
103 * @rsc_backoff_time_ns: rsc backoff time in nano seconds
104 * @pdc_backoff_time_ns: pdc backoff time in nano seconds
105 * @rsc_mode_threshold_time_ns: rsc mode threshold time in nano seconds
106 * @rsc_time_slot_0_ns: mode-0 time slot threshold in nano seconds
107 * @rsc_time_slot_1_ns: mode-1 time slot threshold in nano seconds
108 * @rsc_time_slot_2_ns: mode-2 time slot threshold in nano seconds
109 */
110struct sde_rsc_timer_config {
111 u32 static_wakeup_time_ns;
112
113 u32 rsc_backoff_time_ns;
114 u32 pdc_backoff_time_ns;
115 u32 rsc_mode_threshold_time_ns;
116 u32 rsc_time_slot_0_ns;
117 u32 rsc_time_slot_1_ns;
118 u32 rsc_time_slot_2_ns;
119};
120
121/**
122 * struct sde_rsc_priv: sde resource state coordinator(rsc) private handle
123 * @version: rsc sequence version
124 * @phandle: module power handle for clocks
125 * @pclient: module power client of phandle
126 * @fs: "MDSS GDSC" handle
127 *
Dhaval Pateld2dd1ad2017-03-29 16:13:17 -0700128 * @disp_rsc: display rsc handle
Dhaval Patel49ef6d72017-03-26 09:35:53 -0700129 * @drv_io: sde drv io data mapping
130 * @wrapper_io: wrapper io data mapping
131 *
132 * @client_list: current rsc client list handle
133 * @event_list: current rsc event list handle
134 * @client_lock: current rsc client synchronization lock
135 *
136 * timer_config: current rsc timer configuration
137 * cmd_config: current panel config
138 * current_state: current rsc state (video/command), solver
139 * override/enabled.
140 * debug_mode: enables the logging for each register read/write
141 * debugfs_root: debugfs file system root node
142 *
143 * hw_ops: sde rsc hardware operations
144 * power_collapse: if all clients are in IDLE state then it enters in
145 * mode2 state and enable the power collapse state
146 * power_collapse_block:By default, rsc move to mode-2 if all clients are in
147 * invalid state. It can be blocked by this boolean entry.
148 * primary_client: A client which is allowed to make command state request
149 * and ab/ib vote on display rsc
150 * master_drm: Primary client waits for vsync on this drm object based
151 * on crtc id
Ingrid Gallardoe52302c2017-11-28 19:30:47 -0800152 * rsc_vsync_wait: Refcount to indicate if we have to wait for the vsync.
153 * rsc_vsync_waitq: Queue to wait for the vsync.
Dhaval Patel49ef6d72017-03-26 09:35:53 -0700154 */
155struct sde_rsc_priv {
156 u32 version;
157 struct sde_power_handle phandle;
158 struct sde_power_client *pclient;
159 struct regulator *fs;
160
Dhaval Pateld2dd1ad2017-03-29 16:13:17 -0700161 struct rpmh_client *disp_rsc;
Dhaval Patel49ef6d72017-03-26 09:35:53 -0700162 struct dss_io_data drv_io;
163 struct dss_io_data wrapper_io;
164
165 struct list_head client_list;
166 struct list_head event_list;
167 struct mutex client_lock;
168
169 struct sde_rsc_timer_config timer_config;
170 struct sde_rsc_cmd_config cmd_config;
171 u32 current_state;
172
173 u32 debug_mode;
174 struct dentry *debugfs_root;
175
176 struct sde_rsc_hw_ops hw_ops;
177 bool power_collapse;
178 bool power_collapse_block;
179 struct sde_rsc_client *primary_client;
180
181 struct drm_device *master_drm;
Ingrid Gallardoe52302c2017-11-28 19:30:47 -0800182 atomic_t rsc_vsync_wait;
183 wait_queue_head_t rsc_vsync_waitq;
Dhaval Patel49ef6d72017-03-26 09:35:53 -0700184};
185
186/**
187 * sde_rsc_hw_register() - register hardware API
188 *
189 * @client: Client pointer provided by sde_rsc_client_create().
190 *
191 * Return: error code.
192 */
193int sde_rsc_hw_register(struct sde_rsc_priv *rsc);
194
195#endif /* _SDE_RSC_PRIV_H_ */