John W. Linville | 0aec00a | 2007-06-12 22:11:42 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Definitions for RTL818x hardware |
| 3 | * |
| 4 | * Copyright 2007 Michael Wu <flamingice@sourmilk.net> |
| 5 | * Copyright 2007 Andrea Merello <andreamrl@tiscali.it> |
| 6 | * |
| 7 | * Based on the r8187 driver, which is: |
| 8 | * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 15 | #ifndef RTL818X_H |
| 16 | #define RTL818X_H |
| 17 | |
| 18 | struct rtl818x_csr { |
| 19 | u8 MAC[6]; |
| 20 | u8 reserved_0[2]; |
| 21 | __le32 MAR[2]; |
| 22 | u8 RX_FIFO_COUNT; |
| 23 | u8 reserved_1; |
| 24 | u8 TX_FIFO_COUNT; |
| 25 | u8 BQREQ; |
| 26 | u8 reserved_2[4]; |
| 27 | __le32 TSFT[2]; |
| 28 | __le32 TLPDA; |
| 29 | __le32 TNPDA; |
| 30 | __le32 THPDA; |
| 31 | __le16 BRSR; |
| 32 | u8 BSSID[6]; |
| 33 | u8 RESP_RATE; |
| 34 | u8 EIFS; |
| 35 | u8 reserved_3[1]; |
| 36 | u8 CMD; |
| 37 | #define RTL818X_CMD_TX_ENABLE (1 << 2) |
| 38 | #define RTL818X_CMD_RX_ENABLE (1 << 3) |
| 39 | #define RTL818X_CMD_RESET (1 << 4) |
| 40 | u8 reserved_4[4]; |
| 41 | __le16 INT_MASK; |
| 42 | __le16 INT_STATUS; |
| 43 | #define RTL818X_INT_RX_OK (1 << 0) |
| 44 | #define RTL818X_INT_RX_ERR (1 << 1) |
| 45 | #define RTL818X_INT_TXL_OK (1 << 2) |
| 46 | #define RTL818X_INT_TXL_ERR (1 << 3) |
| 47 | #define RTL818X_INT_RX_DU (1 << 4) |
| 48 | #define RTL818X_INT_RX_FO (1 << 5) |
| 49 | #define RTL818X_INT_TXN_OK (1 << 6) |
| 50 | #define RTL818X_INT_TXN_ERR (1 << 7) |
| 51 | #define RTL818X_INT_TXH_OK (1 << 8) |
| 52 | #define RTL818X_INT_TXH_ERR (1 << 9) |
| 53 | #define RTL818X_INT_TXB_OK (1 << 10) |
| 54 | #define RTL818X_INT_TXB_ERR (1 << 11) |
| 55 | #define RTL818X_INT_ATIM (1 << 12) |
| 56 | #define RTL818X_INT_BEACON (1 << 13) |
| 57 | #define RTL818X_INT_TIME_OUT (1 << 14) |
| 58 | #define RTL818X_INT_TX_FO (1 << 15) |
| 59 | __le32 TX_CONF; |
| 60 | #define RTL818X_TX_CONF_LOOPBACK_MAC (1 << 17) |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 61 | #define RTL818X_TX_CONF_LOOPBACK_CONT (3 << 17) |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 62 | #define RTL818X_TX_CONF_NO_ICV (1 << 19) |
| 63 | #define RTL818X_TX_CONF_DISCW (1 << 20) |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 64 | #define RTL818X_TX_CONF_SAT_HWPLCP (1 << 24) |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 65 | #define RTL818X_TX_CONF_R8180_ABCD (2 << 25) |
| 66 | #define RTL818X_TX_CONF_R8180_F (3 << 25) |
| 67 | #define RTL818X_TX_CONF_R8185_ABC (4 << 25) |
| 68 | #define RTL818X_TX_CONF_R8185_D (5 << 25) |
| 69 | #define RTL818X_TX_CONF_HWVER_MASK (7 << 25) |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 70 | #define RTL818X_TX_CONF_PROBE_DTS (1 << 29) |
| 71 | #define RTL818X_TX_CONF_HW_SEQNUM (1 << 30) |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 72 | #define RTL818X_TX_CONF_CW_MIN (1 << 31) |
| 73 | __le32 RX_CONF; |
| 74 | #define RTL818X_RX_CONF_MONITOR (1 << 0) |
| 75 | #define RTL818X_RX_CONF_NICMAC (1 << 1) |
| 76 | #define RTL818X_RX_CONF_MULTICAST (1 << 2) |
| 77 | #define RTL818X_RX_CONF_BROADCAST (1 << 3) |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 78 | #define RTL818X_RX_CONF_FCS (1 << 5) |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 79 | #define RTL818X_RX_CONF_DATA (1 << 18) |
| 80 | #define RTL818X_RX_CONF_CTRL (1 << 19) |
| 81 | #define RTL818X_RX_CONF_MGMT (1 << 20) |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 82 | #define RTL818X_RX_CONF_ADDR3 (1 << 21) |
| 83 | #define RTL818X_RX_CONF_PM (1 << 22) |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 84 | #define RTL818X_RX_CONF_BSSID (1 << 23) |
| 85 | #define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28) |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 86 | #define RTL818X_RX_CONF_CSDM1 (1 << 29) |
| 87 | #define RTL818X_RX_CONF_CSDM2 (1 << 30) |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 88 | #define RTL818X_RX_CONF_ONLYERLPKT (1 << 31) |
| 89 | __le32 INT_TIMEOUT; |
| 90 | __le32 TBDA; |
| 91 | u8 EEPROM_CMD; |
| 92 | #define RTL818X_EEPROM_CMD_READ (1 << 0) |
| 93 | #define RTL818X_EEPROM_CMD_WRITE (1 << 1) |
| 94 | #define RTL818X_EEPROM_CMD_CK (1 << 2) |
| 95 | #define RTL818X_EEPROM_CMD_CS (1 << 3) |
| 96 | #define RTL818X_EEPROM_CMD_NORMAL (0 << 6) |
| 97 | #define RTL818X_EEPROM_CMD_LOAD (1 << 6) |
| 98 | #define RTL818X_EEPROM_CMD_PROGRAM (2 << 6) |
| 99 | #define RTL818X_EEPROM_CMD_CONFIG (3 << 6) |
| 100 | u8 CONFIG0; |
| 101 | u8 CONFIG1; |
| 102 | u8 CONFIG2; |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 103 | #define RTL818X_CONFIG2_ANTENNA_DIV (1 << 6) |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 104 | __le32 ANAPARAM; |
| 105 | u8 MSR; |
| 106 | #define RTL818X_MSR_NO_LINK (0 << 2) |
| 107 | #define RTL818X_MSR_ADHOC (1 << 2) |
| 108 | #define RTL818X_MSR_INFRA (2 << 2) |
| 109 | u8 CONFIG3; |
| 110 | #define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6) |
| 111 | u8 CONFIG4; |
| 112 | #define RTL818X_CONFIG4_POWEROFF (1 << 6) |
| 113 | #define RTL818X_CONFIG4_VCOOFF (1 << 7) |
| 114 | u8 TESTR; |
| 115 | u8 reserved_9[2]; |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 116 | u8 PGSELECT; |
| 117 | u8 SECURITY; |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 118 | __le32 ANAPARAM2; |
| 119 | u8 reserved_10[12]; |
| 120 | __le16 BEACON_INTERVAL; |
| 121 | __le16 ATIM_WND; |
| 122 | __le16 BEACON_INTERVAL_TIME; |
| 123 | __le16 ATIMTR_INTERVAL; |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 124 | u8 PHY_DELAY; |
| 125 | u8 CARRIER_SENSE_COUNTER; |
| 126 | u8 reserved_11[2]; |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 127 | u8 PHY[4]; |
| 128 | __le16 RFPinsOutput; |
| 129 | __le16 RFPinsEnable; |
| 130 | __le16 RFPinsSelect; |
| 131 | __le16 RFPinsInput; |
| 132 | __le32 RF_PARA; |
| 133 | __le32 RF_TIMING; |
| 134 | u8 GP_ENABLE; |
| 135 | u8 GPIO; |
| 136 | u8 reserved_12[10]; |
| 137 | u8 TX_AGC_CTL; |
| 138 | #define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT (1 << 0) |
| 139 | #define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT (1 << 1) |
| 140 | #define RTL818X_TX_AGC_CTL_FEEDBACK_ANT (1 << 2) |
| 141 | u8 TX_GAIN_CCK; |
| 142 | u8 TX_GAIN_OFDM; |
| 143 | u8 TX_ANTENNA; |
| 144 | u8 reserved_13[16]; |
| 145 | u8 WPA_CONF; |
| 146 | u8 reserved_14[3]; |
| 147 | u8 SIFS; |
| 148 | u8 DIFS; |
| 149 | u8 SLOT; |
| 150 | u8 reserved_15[5]; |
| 151 | u8 CW_CONF; |
| 152 | #define RTL818X_CW_CONF_PERPACKET_CW_SHIFT (1 << 0) |
| 153 | #define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT (1 << 1) |
| 154 | u8 CW_VAL; |
| 155 | u8 RATE_FALLBACK; |
| 156 | u8 reserved_16[25]; |
| 157 | u8 CONFIG5; |
| 158 | u8 TX_DMA_POLLING; |
| 159 | u8 reserved_17[2]; |
| 160 | __le16 CWR; |
| 161 | u8 RETRY_CTR; |
| 162 | u8 reserved_18[5]; |
| 163 | __le32 RDSAR; |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 164 | u8 reserved_19[12]; |
| 165 | __le16 FEMR; |
| 166 | u8 reserved_20[4]; |
| 167 | __le16 TALLY_CNT; |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 168 | u8 TALLY_SEL; |
| 169 | } __attribute__((packed)); |
| 170 | |
Michael Wu | f653211 | 2007-10-14 14:43:16 -0400 | [diff] [blame] | 171 | struct rtl818x_rf_ops { |
| 172 | char *name; |
| 173 | void (*init)(struct ieee80211_hw *); |
| 174 | void (*stop)(struct ieee80211_hw *); |
| 175 | void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *); |
| 176 | }; |
| 177 | |
Michael Wu | 605bebe | 2007-05-14 01:41:02 -0400 | [diff] [blame] | 178 | #endif /* RTL818X_H */ |