Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <ttm/ttm_bo_api.h> |
| 33 | #include <ttm/ttm_bo_driver.h> |
| 34 | #include <ttm/ttm_placement.h> |
| 35 | #include <ttm/ttm_module.h> |
Pauli Nieminen | 8d7cddc | 2010-04-01 12:44:59 +0000 | [diff] [blame] | 36 | #include <ttm/ttm_page_alloc.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | #include <drm/drmP.h> |
| 38 | #include <drm/radeon_drm.h> |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 39 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 40 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | #include "radeon_reg.h" |
| 42 | #include "radeon.h" |
| 43 | |
| 44 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
| 45 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 46 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
| 47 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
| 49 | { |
| 50 | struct radeon_mman *mman; |
| 51 | struct radeon_device *rdev; |
| 52 | |
| 53 | mman = container_of(bdev, struct radeon_mman, bdev); |
| 54 | rdev = container_of(mman, struct radeon_device, mman); |
| 55 | return rdev; |
| 56 | } |
| 57 | |
| 58 | |
| 59 | /* |
| 60 | * Global memory. |
| 61 | */ |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 62 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | { |
| 64 | return ttm_mem_global_init(ref->object); |
| 65 | } |
| 66 | |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 67 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 68 | { |
| 69 | ttm_mem_global_release(ref->object); |
| 70 | } |
| 71 | |
| 72 | static int radeon_ttm_global_init(struct radeon_device *rdev) |
| 73 | { |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 74 | struct drm_global_reference *global_ref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | int r; |
| 76 | |
| 77 | rdev->mman.mem_global_referenced = false; |
| 78 | global_ref = &rdev->mman.mem_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 79 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 80 | global_ref->size = sizeof(struct ttm_mem_global); |
| 81 | global_ref->init = &radeon_ttm_mem_global_init; |
| 82 | global_ref->release = &radeon_ttm_mem_global_release; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 83 | r = drm_global_item_ref(global_ref); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 84 | if (r != 0) { |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 85 | DRM_ERROR("Failed setting up TTM memory accounting " |
| 86 | "subsystem.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 87 | return r; |
| 88 | } |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 89 | |
| 90 | rdev->mman.bo_global_ref.mem_glob = |
| 91 | rdev->mman.mem_global_ref.object; |
| 92 | global_ref = &rdev->mman.bo_global_ref.ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 93 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
Thomas Hellstrom | 7f5f4db | 2009-08-20 10:29:08 +0200 | [diff] [blame] | 94 | global_ref->size = sizeof(struct ttm_bo_global); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 95 | global_ref->init = &ttm_bo_global_init; |
| 96 | global_ref->release = &ttm_bo_global_release; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 97 | r = drm_global_item_ref(global_ref); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 98 | if (r != 0) { |
| 99 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 100 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 101 | return r; |
| 102 | } |
| 103 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | rdev->mman.mem_global_referenced = true; |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static void radeon_ttm_global_fini(struct radeon_device *rdev) |
| 109 | { |
| 110 | if (rdev->mman.mem_global_referenced) { |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 111 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
| 112 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 113 | rdev->mman.mem_global_referenced = false; |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev); |
| 118 | |
| 119 | static struct ttm_backend* |
| 120 | radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev) |
| 121 | { |
| 122 | struct radeon_device *rdev; |
| 123 | |
| 124 | rdev = radeon_get_rdev(bdev); |
| 125 | #if __OS_HAS_AGP |
| 126 | if (rdev->flags & RADEON_IS_AGP) { |
| 127 | return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge); |
| 128 | } else |
| 129 | #endif |
| 130 | { |
| 131 | return radeon_ttm_backend_create(rdev); |
| 132 | } |
| 133 | } |
| 134 | |
| 135 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
| 136 | { |
| 137 | return 0; |
| 138 | } |
| 139 | |
| 140 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, |
| 141 | struct ttm_mem_type_manager *man) |
| 142 | { |
| 143 | struct radeon_device *rdev; |
| 144 | |
| 145 | rdev = radeon_get_rdev(bdev); |
| 146 | |
| 147 | switch (type) { |
| 148 | case TTM_PL_SYSTEM: |
| 149 | /* System memory */ |
| 150 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
| 151 | man->available_caching = TTM_PL_MASK_CACHING; |
| 152 | man->default_caching = TTM_PL_FLAG_CACHED; |
| 153 | break; |
| 154 | case TTM_PL_TT: |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 155 | man->func = &ttm_bo_manager_func; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 156 | man->gpu_offset = rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | man->available_caching = TTM_PL_MASK_CACHING; |
| 158 | man->default_caching = TTM_PL_FLAG_CACHED; |
Michel Dänzer | 55c9327 | 2009-06-15 16:56:11 +0200 | [diff] [blame] | 159 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 160 | #if __OS_HAS_AGP |
| 161 | if (rdev->flags & RADEON_IS_AGP) { |
| 162 | if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { |
| 163 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
| 164 | (unsigned)type); |
| 165 | return -EINVAL; |
| 166 | } |
Michel Dänzer | 55c9327 | 2009-06-15 16:56:11 +0200 | [diff] [blame] | 167 | if (!rdev->ddev->agp->cant_use_aperture) |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 168 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
| 170 | TTM_PL_FLAG_WC; |
| 171 | man->default_caching = TTM_PL_FLAG_WC; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 172 | } |
Jerome Glisse | 0c321c7 | 2010-04-07 10:21:27 +0000 | [diff] [blame] | 173 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 174 | break; |
| 175 | case TTM_PL_VRAM: |
| 176 | /* "On-card" video ram */ |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 177 | man->func = &ttm_bo_manager_func; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 178 | man->gpu_offset = rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 179 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 180 | TTM_MEMTYPE_FLAG_MAPPABLE; |
| 181 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; |
| 182 | man->default_caching = TTM_PL_FLAG_WC; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 183 | break; |
| 184 | default: |
| 185 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); |
| 186 | return -EINVAL; |
| 187 | } |
| 188 | return 0; |
| 189 | } |
| 190 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 191 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
| 192 | struct ttm_placement *placement) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 193 | { |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 194 | struct radeon_bo *rbo; |
| 195 | static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
| 196 | |
| 197 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { |
| 198 | placement->fpfn = 0; |
| 199 | placement->lpfn = 0; |
| 200 | placement->placement = &placements; |
| 201 | placement->busy_placement = &placements; |
| 202 | placement->num_placement = 1; |
| 203 | placement->num_busy_placement = 1; |
| 204 | return; |
| 205 | } |
| 206 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 207 | switch (bo->mem.mem_type) { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 208 | case TTM_PL_VRAM: |
Dave Airlie | 9270eb1 | 2010-01-13 09:21:49 +1000 | [diff] [blame] | 209 | if (rbo->rdev->cp.ready == false) |
| 210 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
| 211 | else |
| 212 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 213 | break; |
| 214 | case TTM_PL_TT: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 215 | default: |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 216 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 217 | } |
Jerome Glisse | eaa5fd1 | 2009-12-09 21:57:37 +0100 | [diff] [blame] | 218 | *placement = rbo->placement; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | } |
| 220 | |
| 221 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) |
| 222 | { |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static void radeon_move_null(struct ttm_buffer_object *bo, |
| 227 | struct ttm_mem_reg *new_mem) |
| 228 | { |
| 229 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 230 | |
| 231 | BUG_ON(old_mem->mm_node != NULL); |
| 232 | *old_mem = *new_mem; |
| 233 | new_mem->mm_node = NULL; |
| 234 | } |
| 235 | |
| 236 | static int radeon_move_blit(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 237 | bool evict, int no_wait_reserve, bool no_wait_gpu, |
| 238 | struct ttm_mem_reg *new_mem, |
| 239 | struct ttm_mem_reg *old_mem) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 240 | { |
| 241 | struct radeon_device *rdev; |
| 242 | uint64_t old_start, new_start; |
| 243 | struct radeon_fence *fence; |
| 244 | int r; |
| 245 | |
| 246 | rdev = radeon_get_rdev(bo->bdev); |
| 247 | r = radeon_fence_create(rdev, &fence); |
| 248 | if (unlikely(r)) { |
| 249 | return r; |
| 250 | } |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 251 | old_start = old_mem->start << PAGE_SHIFT; |
| 252 | new_start = new_mem->start << PAGE_SHIFT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 253 | |
| 254 | switch (old_mem->mem_type) { |
| 255 | case TTM_PL_VRAM: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 256 | old_start += rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 257 | break; |
| 258 | case TTM_PL_TT: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 259 | old_start += rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 260 | break; |
| 261 | default: |
| 262 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); |
| 263 | return -EINVAL; |
| 264 | } |
| 265 | switch (new_mem->mem_type) { |
| 266 | case TTM_PL_VRAM: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 267 | new_start += rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 268 | break; |
| 269 | case TTM_PL_TT: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 270 | new_start += rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | break; |
| 272 | default: |
| 273 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); |
| 274 | return -EINVAL; |
| 275 | } |
| 276 | if (!rdev->cp.ready) { |
| 277 | DRM_ERROR("Trying to move memory with CP turned off.\n"); |
| 278 | return -EINVAL; |
| 279 | } |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 280 | |
| 281 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); |
| 282 | |
| 283 | r = radeon_copy(rdev, old_start, new_start, |
| 284 | new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ |
| 285 | fence); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 286 | /* FIXME: handle copy error */ |
| 287 | r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 288 | evict, no_wait_reserve, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 289 | radeon_fence_unref(&fence); |
| 290 | return r; |
| 291 | } |
| 292 | |
| 293 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 294 | bool evict, bool interruptible, |
| 295 | bool no_wait_reserve, bool no_wait_gpu, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 296 | struct ttm_mem_reg *new_mem) |
| 297 | { |
| 298 | struct radeon_device *rdev; |
| 299 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 300 | struct ttm_mem_reg tmp_mem; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 301 | u32 placements; |
| 302 | struct ttm_placement placement; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | int r; |
| 304 | |
| 305 | rdev = radeon_get_rdev(bo->bdev); |
| 306 | tmp_mem = *new_mem; |
| 307 | tmp_mem.mm_node = NULL; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 308 | placement.fpfn = 0; |
| 309 | placement.lpfn = 0; |
| 310 | placement.num_placement = 1; |
| 311 | placement.placement = &placements; |
| 312 | placement.num_busy_placement = 1; |
| 313 | placement.busy_placement = &placements; |
| 314 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
| 315 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 316 | interruptible, no_wait_reserve, no_wait_gpu); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 317 | if (unlikely(r)) { |
| 318 | return r; |
| 319 | } |
Dave Airlie | df67bed | 2009-10-30 13:31:26 +1000 | [diff] [blame] | 320 | |
| 321 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); |
| 322 | if (unlikely(r)) { |
| 323 | goto out_cleanup; |
| 324 | } |
| 325 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 326 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
| 327 | if (unlikely(r)) { |
| 328 | goto out_cleanup; |
| 329 | } |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 330 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 331 | if (unlikely(r)) { |
| 332 | goto out_cleanup; |
| 333 | } |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 334 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 335 | out_cleanup: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 336 | ttm_bo_mem_put(bo, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 337 | return r; |
| 338 | } |
| 339 | |
| 340 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 341 | bool evict, bool interruptible, |
| 342 | bool no_wait_reserve, bool no_wait_gpu, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 343 | struct ttm_mem_reg *new_mem) |
| 344 | { |
| 345 | struct radeon_device *rdev; |
| 346 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 347 | struct ttm_mem_reg tmp_mem; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 348 | struct ttm_placement placement; |
| 349 | u32 placements; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 350 | int r; |
| 351 | |
| 352 | rdev = radeon_get_rdev(bo->bdev); |
| 353 | tmp_mem = *new_mem; |
| 354 | tmp_mem.mm_node = NULL; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 355 | placement.fpfn = 0; |
| 356 | placement.lpfn = 0; |
| 357 | placement.num_placement = 1; |
| 358 | placement.placement = &placements; |
| 359 | placement.num_busy_placement = 1; |
| 360 | placement.busy_placement = &placements; |
| 361 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 362 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 363 | if (unlikely(r)) { |
| 364 | return r; |
| 365 | } |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 366 | r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 367 | if (unlikely(r)) { |
| 368 | goto out_cleanup; |
| 369 | } |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 370 | r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 371 | if (unlikely(r)) { |
| 372 | goto out_cleanup; |
| 373 | } |
| 374 | out_cleanup: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 375 | ttm_bo_mem_put(bo, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 376 | return r; |
| 377 | } |
| 378 | |
| 379 | static int radeon_bo_move(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 380 | bool evict, bool interruptible, |
| 381 | bool no_wait_reserve, bool no_wait_gpu, |
| 382 | struct ttm_mem_reg *new_mem) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | { |
| 384 | struct radeon_device *rdev; |
| 385 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 386 | int r; |
| 387 | |
| 388 | rdev = radeon_get_rdev(bo->bdev); |
| 389 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { |
| 390 | radeon_move_null(bo, new_mem); |
| 391 | return 0; |
| 392 | } |
| 393 | if ((old_mem->mem_type == TTM_PL_TT && |
| 394 | new_mem->mem_type == TTM_PL_SYSTEM) || |
| 395 | (old_mem->mem_type == TTM_PL_SYSTEM && |
| 396 | new_mem->mem_type == TTM_PL_TT)) { |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 397 | /* bind is enough */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 398 | radeon_move_null(bo, new_mem); |
| 399 | return 0; |
| 400 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 401 | if (!rdev->cp.ready || rdev->asic->copy == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 402 | /* use memcpy */ |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 403 | goto memcpy; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | if (old_mem->mem_type == TTM_PL_VRAM && |
| 407 | new_mem->mem_type == TTM_PL_SYSTEM) { |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 408 | r = radeon_move_vram_ram(bo, evict, interruptible, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 409 | no_wait_reserve, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 410 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
| 411 | new_mem->mem_type == TTM_PL_VRAM) { |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 412 | r = radeon_move_ram_vram(bo, evict, interruptible, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 413 | no_wait_reserve, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 414 | } else { |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 415 | r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 416 | } |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 417 | |
| 418 | if (r) { |
| 419 | memcpy: |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 420 | r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 421 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 422 | return r; |
| 423 | } |
| 424 | |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 425 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 426 | { |
| 427 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; |
| 428 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
| 429 | |
| 430 | mem->bus.addr = NULL; |
| 431 | mem->bus.offset = 0; |
| 432 | mem->bus.size = mem->num_pages << PAGE_SHIFT; |
| 433 | mem->bus.base = 0; |
| 434 | mem->bus.is_iomem = false; |
| 435 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) |
| 436 | return -EINVAL; |
| 437 | switch (mem->mem_type) { |
| 438 | case TTM_PL_SYSTEM: |
| 439 | /* system memory */ |
| 440 | return 0; |
| 441 | case TTM_PL_TT: |
| 442 | #if __OS_HAS_AGP |
| 443 | if (rdev->flags & RADEON_IS_AGP) { |
| 444 | /* RADEON_IS_AGP is set only if AGP is active */ |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 445 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 446 | mem->bus.base = rdev->mc.agp_base; |
Michel Dänzer | 365048f | 2010-05-19 12:46:22 +0200 | [diff] [blame] | 447 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 448 | } |
| 449 | #endif |
| 450 | break; |
| 451 | case TTM_PL_VRAM: |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 452 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 453 | /* check if it's visible */ |
| 454 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) |
| 455 | return -EINVAL; |
| 456 | mem->bus.base = rdev->mc.aper_base; |
| 457 | mem->bus.is_iomem = true; |
Jay Estabrook | ffb57c4 | 2011-07-06 23:57:13 +0000 | [diff] [blame] | 458 | #ifdef __alpha__ |
| 459 | /* |
| 460 | * Alpha: use bus.addr to hold the ioremap() return, |
| 461 | * so we can modify bus.base below. |
| 462 | */ |
| 463 | if (mem->placement & TTM_PL_FLAG_WC) |
| 464 | mem->bus.addr = |
| 465 | ioremap_wc(mem->bus.base + mem->bus.offset, |
| 466 | mem->bus.size); |
| 467 | else |
| 468 | mem->bus.addr = |
| 469 | ioremap_nocache(mem->bus.base + mem->bus.offset, |
| 470 | mem->bus.size); |
| 471 | |
| 472 | /* |
| 473 | * Alpha: Use just the bus offset plus |
| 474 | * the hose/domain memory base for bus.base. |
| 475 | * It then can be used to build PTEs for VRAM |
| 476 | * access, as done in ttm_bo_vm_fault(). |
| 477 | */ |
| 478 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + |
| 479 | rdev->ddev->hose->dense_mem_base; |
| 480 | #endif |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 481 | break; |
| 482 | default: |
| 483 | return -EINVAL; |
| 484 | } |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 489 | { |
| 490 | } |
| 491 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 492 | static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg, |
| 493 | bool lazy, bool interruptible) |
| 494 | { |
| 495 | return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); |
| 496 | } |
| 497 | |
| 498 | static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg) |
| 499 | { |
| 500 | return 0; |
| 501 | } |
| 502 | |
| 503 | static void radeon_sync_obj_unref(void **sync_obj) |
| 504 | { |
| 505 | radeon_fence_unref((struct radeon_fence **)sync_obj); |
| 506 | } |
| 507 | |
| 508 | static void *radeon_sync_obj_ref(void *sync_obj) |
| 509 | { |
| 510 | return radeon_fence_ref((struct radeon_fence *)sync_obj); |
| 511 | } |
| 512 | |
| 513 | static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg) |
| 514 | { |
| 515 | return radeon_fence_signaled((struct radeon_fence *)sync_obj); |
| 516 | } |
| 517 | |
| 518 | static struct ttm_bo_driver radeon_bo_driver = { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 519 | .create_ttm_backend_entry = &radeon_create_ttm_backend_entry, |
| 520 | .invalidate_caches = &radeon_invalidate_caches, |
| 521 | .init_mem_type = &radeon_init_mem_type, |
| 522 | .evict_flags = &radeon_evict_flags, |
| 523 | .move = &radeon_bo_move, |
| 524 | .verify_access = &radeon_verify_access, |
| 525 | .sync_obj_signaled = &radeon_sync_obj_signaled, |
| 526 | .sync_obj_wait = &radeon_sync_obj_wait, |
| 527 | .sync_obj_flush = &radeon_sync_obj_flush, |
| 528 | .sync_obj_unref = &radeon_sync_obj_unref, |
| 529 | .sync_obj_ref = &radeon_sync_obj_ref, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 530 | .move_notify = &radeon_bo_move_notify, |
| 531 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 532 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
| 533 | .io_mem_free = &radeon_ttm_io_mem_free, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 534 | }; |
| 535 | |
| 536 | int radeon_ttm_init(struct radeon_device *rdev) |
| 537 | { |
| 538 | int r; |
| 539 | |
| 540 | r = radeon_ttm_global_init(rdev); |
| 541 | if (r) { |
| 542 | return r; |
| 543 | } |
| 544 | /* No others user of address space so set it to 0 */ |
| 545 | r = ttm_bo_device_init(&rdev->mman.bdev, |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 546 | rdev->mman.bo_global_ref.ref.object, |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 547 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
| 548 | rdev->need_dma32); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 549 | if (r) { |
| 550 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); |
| 551 | return r; |
| 552 | } |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 553 | rdev->mman.initialized = true; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 554 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 555 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 556 | if (r) { |
| 557 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
| 558 | return r; |
| 559 | } |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 560 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 561 | RADEON_GEM_DOMAIN_VRAM, |
| 562 | &rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 563 | if (r) { |
| 564 | return r; |
| 565 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 566 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
| 567 | if (r) |
| 568 | return r; |
| 569 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
| 570 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 571 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 572 | radeon_bo_unref(&rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 573 | return r; |
| 574 | } |
| 575 | DRM_INFO("radeon: %uM of VRAM memory ready\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 576 | (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 577 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 578 | rdev->mc.gtt_size >> PAGE_SHIFT); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 579 | if (r) { |
| 580 | DRM_ERROR("Failed initializing GTT heap.\n"); |
| 581 | return r; |
| 582 | } |
| 583 | DRM_INFO("radeon: %uM of GTT memory ready.\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 584 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 585 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
| 586 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
| 587 | } |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 588 | |
| 589 | r = radeon_ttm_debugfs_init(rdev); |
| 590 | if (r) { |
| 591 | DRM_ERROR("Failed to init debugfs\n"); |
| 592 | return r; |
| 593 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 594 | return 0; |
| 595 | } |
| 596 | |
| 597 | void radeon_ttm_fini(struct radeon_device *rdev) |
| 598 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 599 | int r; |
| 600 | |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 601 | if (!rdev->mman.initialized) |
| 602 | return; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 603 | if (rdev->stollen_vga_memory) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 604 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
| 605 | if (r == 0) { |
| 606 | radeon_bo_unpin(rdev->stollen_vga_memory); |
| 607 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
| 608 | } |
| 609 | radeon_bo_unref(&rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 610 | } |
| 611 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 612 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); |
| 613 | ttm_bo_device_release(&rdev->mman.bdev); |
| 614 | radeon_gart_fini(rdev); |
| 615 | radeon_ttm_global_fini(rdev); |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 616 | rdev->mman.initialized = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 617 | DRM_INFO("radeon: ttm finalized\n"); |
| 618 | } |
| 619 | |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 620 | /* this should only be called at bootup or when userspace |
| 621 | * isn't running */ |
| 622 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) |
| 623 | { |
| 624 | struct ttm_mem_type_manager *man; |
| 625 | |
| 626 | if (!rdev->mman.initialized) |
| 627 | return; |
| 628 | |
| 629 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; |
| 630 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ |
| 631 | man->size = size >> PAGE_SHIFT; |
| 632 | } |
| 633 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 634 | static struct vm_operations_struct radeon_ttm_vm_ops; |
Alexey Dobriyan | f0f37e2 | 2009-09-27 22:29:37 +0400 | [diff] [blame] | 635 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 636 | |
| 637 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 638 | { |
| 639 | struct ttm_buffer_object *bo; |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 640 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 641 | int r; |
| 642 | |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 643 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 644 | if (bo == NULL) { |
| 645 | return VM_FAULT_NOPAGE; |
| 646 | } |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 647 | rdev = radeon_get_rdev(bo->bdev); |
| 648 | mutex_lock(&rdev->vram_mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 649 | r = ttm_vm_ops->fault(vma, vmf); |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 650 | mutex_unlock(&rdev->vram_mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 651 | return r; |
| 652 | } |
| 653 | |
| 654 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) |
| 655 | { |
| 656 | struct drm_file *file_priv; |
| 657 | struct radeon_device *rdev; |
| 658 | int r; |
| 659 | |
| 660 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { |
| 661 | return drm_mmap(filp, vma); |
| 662 | } |
| 663 | |
Joe Perches | 40b3be3 | 2010-09-04 18:52:42 -0700 | [diff] [blame] | 664 | file_priv = filp->private_data; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 665 | rdev = file_priv->minor->dev->dev_private; |
| 666 | if (rdev == NULL) { |
| 667 | return -EINVAL; |
| 668 | } |
| 669 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); |
| 670 | if (unlikely(r != 0)) { |
| 671 | return r; |
| 672 | } |
| 673 | if (unlikely(ttm_vm_ops == NULL)) { |
| 674 | ttm_vm_ops = vma->vm_ops; |
| 675 | radeon_ttm_vm_ops = *ttm_vm_ops; |
| 676 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; |
| 677 | } |
| 678 | vma->vm_ops = &radeon_ttm_vm_ops; |
| 679 | return 0; |
| 680 | } |
| 681 | |
| 682 | |
| 683 | /* |
| 684 | * TTM backend functions. |
| 685 | */ |
| 686 | struct radeon_ttm_backend { |
| 687 | struct ttm_backend backend; |
| 688 | struct radeon_device *rdev; |
| 689 | unsigned long num_pages; |
| 690 | struct page **pages; |
| 691 | struct page *dummy_read_page; |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 692 | dma_addr_t *dma_addrs; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 693 | bool populated; |
| 694 | bool bound; |
| 695 | unsigned offset; |
| 696 | }; |
| 697 | |
| 698 | static int radeon_ttm_backend_populate(struct ttm_backend *backend, |
| 699 | unsigned long num_pages, |
| 700 | struct page **pages, |
Konrad Rzeszutek Wilk | 27e8b23 | 2010-12-02 10:24:13 -0500 | [diff] [blame] | 701 | struct page *dummy_read_page, |
| 702 | dma_addr_t *dma_addrs) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 703 | { |
| 704 | struct radeon_ttm_backend *gtt; |
| 705 | |
| 706 | gtt = container_of(backend, struct radeon_ttm_backend, backend); |
| 707 | gtt->pages = pages; |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 708 | gtt->dma_addrs = dma_addrs; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 709 | gtt->num_pages = num_pages; |
| 710 | gtt->dummy_read_page = dummy_read_page; |
| 711 | gtt->populated = true; |
| 712 | return 0; |
| 713 | } |
| 714 | |
| 715 | static void radeon_ttm_backend_clear(struct ttm_backend *backend) |
| 716 | { |
| 717 | struct radeon_ttm_backend *gtt; |
| 718 | |
| 719 | gtt = container_of(backend, struct radeon_ttm_backend, backend); |
| 720 | gtt->pages = NULL; |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 721 | gtt->dma_addrs = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 722 | gtt->num_pages = 0; |
| 723 | gtt->dummy_read_page = NULL; |
| 724 | gtt->populated = false; |
| 725 | gtt->bound = false; |
| 726 | } |
| 727 | |
| 728 | |
| 729 | static int radeon_ttm_backend_bind(struct ttm_backend *backend, |
| 730 | struct ttm_mem_reg *bo_mem) |
| 731 | { |
| 732 | struct radeon_ttm_backend *gtt; |
| 733 | int r; |
| 734 | |
| 735 | gtt = container_of(backend, struct radeon_ttm_backend, backend); |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 736 | gtt->offset = bo_mem->start << PAGE_SHIFT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 737 | if (!gtt->num_pages) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 738 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", |
| 739 | gtt->num_pages, bo_mem, backend); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 740 | } |
| 741 | r = radeon_gart_bind(gtt->rdev, gtt->offset, |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 742 | gtt->num_pages, gtt->pages, gtt->dma_addrs); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 743 | if (r) { |
| 744 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", |
| 745 | gtt->num_pages, gtt->offset); |
| 746 | return r; |
| 747 | } |
| 748 | gtt->bound = true; |
| 749 | return 0; |
| 750 | } |
| 751 | |
| 752 | static int radeon_ttm_backend_unbind(struct ttm_backend *backend) |
| 753 | { |
| 754 | struct radeon_ttm_backend *gtt; |
| 755 | |
| 756 | gtt = container_of(backend, struct radeon_ttm_backend, backend); |
| 757 | radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages); |
| 758 | gtt->bound = false; |
| 759 | return 0; |
| 760 | } |
| 761 | |
| 762 | static void radeon_ttm_backend_destroy(struct ttm_backend *backend) |
| 763 | { |
| 764 | struct radeon_ttm_backend *gtt; |
| 765 | |
| 766 | gtt = container_of(backend, struct radeon_ttm_backend, backend); |
| 767 | if (gtt->bound) { |
| 768 | radeon_ttm_backend_unbind(backend); |
| 769 | } |
| 770 | kfree(gtt); |
| 771 | } |
| 772 | |
| 773 | static struct ttm_backend_func radeon_backend_func = { |
| 774 | .populate = &radeon_ttm_backend_populate, |
| 775 | .clear = &radeon_ttm_backend_clear, |
| 776 | .bind = &radeon_ttm_backend_bind, |
| 777 | .unbind = &radeon_ttm_backend_unbind, |
| 778 | .destroy = &radeon_ttm_backend_destroy, |
| 779 | }; |
| 780 | |
| 781 | struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev) |
| 782 | { |
| 783 | struct radeon_ttm_backend *gtt; |
| 784 | |
| 785 | gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL); |
| 786 | if (gtt == NULL) { |
| 787 | return NULL; |
| 788 | } |
| 789 | gtt->backend.bdev = &rdev->mman.bdev; |
| 790 | gtt->backend.flags = 0; |
| 791 | gtt->backend.func = &radeon_backend_func; |
| 792 | gtt->rdev = rdev; |
| 793 | gtt->pages = NULL; |
| 794 | gtt->num_pages = 0; |
| 795 | gtt->dummy_read_page = NULL; |
| 796 | gtt->populated = false; |
| 797 | gtt->bound = false; |
| 798 | return >t->backend; |
| 799 | } |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 800 | |
| 801 | #define RADEON_DEBUGFS_MEM_TYPES 2 |
| 802 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 803 | #if defined(CONFIG_DEBUG_FS) |
| 804 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
| 805 | { |
| 806 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 807 | struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; |
| 808 | struct drm_device *dev = node->minor->dev; |
| 809 | struct radeon_device *rdev = dev->dev_private; |
| 810 | int ret; |
| 811 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; |
| 812 | |
| 813 | spin_lock(&glob->lru_lock); |
| 814 | ret = drm_mm_dump_table(m, mm); |
| 815 | spin_unlock(&glob->lru_lock); |
| 816 | return ret; |
| 817 | } |
| 818 | #endif |
| 819 | |
| 820 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) |
| 821 | { |
Mikael Pettersson | f4e45d0 | 2009-09-28 18:27:23 +0200 | [diff] [blame] | 822 | #if defined(CONFIG_DEBUG_FS) |
Pauli Nieminen | 8d7cddc | 2010-04-01 12:44:59 +0000 | [diff] [blame] | 823 | static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+1]; |
| 824 | static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+1][32]; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 825 | unsigned i; |
| 826 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 827 | for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { |
| 828 | if (i == 0) |
| 829 | sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); |
| 830 | else |
| 831 | sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); |
| 832 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; |
| 833 | radeon_mem_types_list[i].show = &radeon_mm_dump_table; |
| 834 | radeon_mem_types_list[i].driver_features = 0; |
| 835 | if (i == 0) |
Dave Airlie | 16f9fdc | 2011-02-07 12:00:51 +1000 | [diff] [blame] | 836 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 837 | else |
Dave Airlie | 16f9fdc | 2011-02-07 12:00:51 +1000 | [diff] [blame] | 838 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 839 | |
| 840 | } |
Pauli Nieminen | 8d7cddc | 2010-04-01 12:44:59 +0000 | [diff] [blame] | 841 | /* Add ttm page pool to debugfs */ |
| 842 | sprintf(radeon_mem_types_names[i], "ttm_page_pool"); |
| 843 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; |
| 844 | radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; |
| 845 | radeon_mem_types_list[i].driver_features = 0; |
| 846 | radeon_mem_types_list[i].data = NULL; |
| 847 | return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES+1); |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 848 | |
| 849 | #endif |
| 850 | return 0; |
| 851 | } |