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gerrit-public.fairphone.software / kernel / msm-4.9 / 3c5b1d92b3b02be07873d611a27950addff544d3 / . / arch / arm64 / kvm / hyp-init.S
blob: d073b5a216f72b1db65fbef79efd942b28df6f6e [file] [log] [blame]
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/linkage.h>
19
20#include <asm/assembler.h>
21#include <asm/kvm_arm.h>
22#include <asm/kvm_mmu.h>
Ard Biesheuvele4c5a682015-03-19 16:42:28 +0000[diff] [blame]23#include <asm/pgtable-hwdef.h>
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]24
25 .text
26 .pushsection .hyp.idmap.text, "ax"
27
28 .align 11
29
30ENTRY(__kvm_hyp_init)
31 ventry __invalid // Synchronous EL2t
32 ventry __invalid // IRQ EL2t
33 ventry __invalid // FIQ EL2t
34 ventry __invalid // Error EL2t
35
36 ventry __invalid // Synchronous EL2h
37 ventry __invalid // IRQ EL2h
38 ventry __invalid // FIQ EL2h
39 ventry __invalid // Error EL2h
40
41 ventry __do_hyp_init // Synchronous 64-bit EL1
42 ventry __invalid // IRQ 64-bit EL1
43 ventry __invalid // FIQ 64-bit EL1
44 ventry __invalid // Error 64-bit EL1
45
46 ventry __invalid // Synchronous 32-bit EL1
47 ventry __invalid // IRQ 32-bit EL1
48 ventry __invalid // FIQ 32-bit EL1
49 ventry __invalid // Error 32-bit EL1
50
51__invalid:
52 b .
53
54 /*
55 * x0: HYP boot pgd
56 * x1: HYP pgd
57 * x2: HYP stack
58 * x3: HYP vectors
59 */
60__do_hyp_init:
61
62 msr ttbr0_el2, x0
63
64 mrs x4, tcr_el1
65 ldr x5, =TCR_EL2_MASK
66 and x4, x4, x5
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -0800[diff] [blame^]67 mov x5, #TCR_EL2_RES1
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]68 orr x4, x4, x5
Ard Biesheuvele4c5a682015-03-19 16:42:28 +0000[diff] [blame]69
70#ifndef CONFIG_ARM64_VA_BITS_48
71 /*
72 * If we are running with VA_BITS < 48, we may be running with an extra
73 * level of translation in the ID map. This is only the case if system
74 * RAM is out of range for the currently configured page size and number
75 * of translation levels, in which case we will also need the extra
76 * level for the HYP ID map, or we won't be able to enable the EL2 MMU.
77 *
78 * However, at EL2, there is only one TTBR register, and we can't switch
79 * between translation tables *and* update TCR_EL2.T0SZ at the same
80 * time. Bottom line: we need the extra level in *both* our translation
81 * tables.
82 *
83 * So use the same T0SZ value we use for the ID map.
84 */
85 ldr_l x5, idmap_t0sz
86 bfi x4, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
87#endif
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -0800[diff] [blame^]88 /*
89 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in
90 * TCR_EL2 and VTCR_EL2.
91 */
92 mrs x5, ID_AA64MMFR0_EL1
93 bfi x4, x5, #16, #3
94
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]95 msr tcr_el2, x4
96
97 ldr x4, =VTCR_EL2_FLAGS
Radha Mohan Chintakuntla87366d82014-03-07 08:49:25 +0000[diff] [blame]98 bfi x4, x5, #16, #3
Vladimir Murzin20475f72015-11-16 11:28:18 +0000[diff] [blame]99 /*
100 * Read the VMIDBits bits from ID_AA64MMFR1_EL1 and set the VS bit in
101 * VTCR_EL2.
102 */
103 mrs x5, ID_AA64MMFR1_EL1
104 ubfx x5, x5, #5, #1
105 lsl x5, x5, #VTCR_EL2_VS
106 orr x4, x4, x5
107
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]108 msr vtcr_el2, x4
109
110 mrs x4, mair_el1
111 msr mair_el2, x4
112 isb
113
Pranavkumar Sawargaonkarf6edbbf2014-07-31 12:23:23 +0530[diff] [blame]114 /* Invalidate the stale TLBs from Bootloader */
115 tlbi alle2
116 dsb sy
117
Marc Zyngier18ea3db2013-11-05 18:29:45 +0000[diff] [blame]118 mrs x4, sctlr_el2
119 and x4, x4, #SCTLR_EL2_EE // preserve endianness of EL2
120 ldr x5, =SCTLR_EL2_FLAGS
121 orr x4, x4, x5
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]122 msr sctlr_el2, x4
123 isb
124
Ard Biesheuvele4c5a682015-03-19 16:42:28 +0000[diff] [blame]125 /* Skip the trampoline dance if we merged the boot and runtime PGDs */
126 cmp x0, x1
127 b.eq merged
128
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]129 /* MMU is now enabled. Get ready for the trampoline dance */
130 ldr x4, =TRAMPOLINE_VA
131 adr x5, target
132 bfi x4, x5, #0, #PAGE_SHIFT
133 br x4
134
135target: /* We're now in the trampoline code, switch page tables */
136 msr ttbr0_el2, x1
137 isb
138
139 /* Invalidate the old TLBs */
140 tlbi alle2
141 dsb sy
142
Ard Biesheuvele4c5a682015-03-19 16:42:28 +0000[diff] [blame]143merged:
Marc Zyngier092bd142012-12-17 17:07:52 +0000[diff] [blame]144 /* Set the stack and new vectors */
145 kern_hyp_va x2
146 mov sp, x2
147 kern_hyp_va x3
148 msr vbar_el2, x3
149
150 /* Hello, World! */
151 eret
152ENDPROC(__kvm_hyp_init)
153
154 .ltorg
155
156 .popsection