| R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * Carveout for multimedia usecases |
| 12 | * It should be the last 48MB of the first 512MB memory part |
| 13 | * In theory, it should not even exist. That zone should be reserved |
| 14 | * dynamically during the .reserve callback. |
| 15 | */ |
| 16 | /memreserve/ 0x9d000000 0x03000000; |
| 17 | |
| 18 | /include/ "skeleton.dtsi" |
| 19 | |
| 20 | / { |
| 21 | compatible = "ti,omap5"; |
| 22 | interrupt-parent = <&gic>; |
| 23 | |
| 24 | aliases { |
| 25 | serial0 = &uart1; |
| 26 | serial1 = &uart2; |
| 27 | serial2 = &uart3; |
| 28 | serial3 = &uart4; |
| 29 | serial4 = &uart5; |
| 30 | serial5 = &uart6; |
| 31 | }; |
| 32 | |
| 33 | cpus { |
| 34 | cpu@0 { |
| 35 | compatible = "arm,cortex-a15"; |
| Santosh Shilimkar | 3c7c5da | 2012-08-13 14:39:03 +0530 | [diff] [blame^] | 36 | timer { |
| 37 | compatible = "arm,armv7-timer"; |
| 38 | /* 14th PPI IRQ, active low level-sensitive */ |
| 39 | interrupts = <1 14 0x308>; |
| 40 | clock-frequency = <6144000>; |
| 41 | }; |
| R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 42 | }; |
| 43 | cpu@1 { |
| 44 | compatible = "arm,cortex-a15"; |
| Santosh Shilimkar | 3c7c5da | 2012-08-13 14:39:03 +0530 | [diff] [blame^] | 45 | timer { |
| 46 | compatible = "arm,armv7-timer"; |
| 47 | /* 14th PPI IRQ, active low level-sensitive */ |
| 48 | interrupts = <1 14 0x308>; |
| 49 | clock-frequency = <6144000>; |
| 50 | }; |
| R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 51 | }; |
| 52 | }; |
| 53 | |
| 54 | /* |
| 55 | * The soc node represents the soc top level view. It is uses for IPs |
| 56 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 57 | */ |
| 58 | soc { |
| 59 | compatible = "ti,omap-infra"; |
| 60 | mpu { |
| 61 | compatible = "ti,omap5-mpu"; |
| 62 | ti,hwmods = "mpu"; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | /* |
| 67 | * XXX: Use a flat representation of the OMAP3 interconnect. |
| 68 | * The real OMAP interconnect network is quite complex. |
| 69 | * Since that will not bring real advantage to represent that in DT for |
| 70 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 71 | * hierarchy. |
| 72 | */ |
| 73 | ocp { |
| 74 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
| 75 | #address-cells = <1>; |
| 76 | #size-cells = <1>; |
| 77 | ranges; |
| 78 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
| 79 | |
| 80 | gic: interrupt-controller@48211000 { |
| 81 | compatible = "arm,cortex-a15-gic"; |
| 82 | interrupt-controller; |
| 83 | #interrupt-cells = <3>; |
| 84 | reg = <0x48211000 0x1000>, |
| 85 | <0x48212000 0x1000>; |
| 86 | }; |
| 87 | |
| 88 | gpio1: gpio@4ae10000 { |
| 89 | compatible = "ti,omap4-gpio"; |
| 90 | ti,hwmods = "gpio1"; |
| 91 | gpio-controller; |
| 92 | #gpio-cells = <2>; |
| 93 | interrupt-controller; |
| 94 | #interrupt-cells = <1>; |
| 95 | }; |
| 96 | |
| 97 | gpio2: gpio@48055000 { |
| 98 | compatible = "ti,omap4-gpio"; |
| 99 | ti,hwmods = "gpio2"; |
| 100 | gpio-controller; |
| 101 | #gpio-cells = <2>; |
| 102 | interrupt-controller; |
| 103 | #interrupt-cells = <1>; |
| 104 | }; |
| 105 | |
| 106 | gpio3: gpio@48057000 { |
| 107 | compatible = "ti,omap4-gpio"; |
| 108 | ti,hwmods = "gpio3"; |
| 109 | gpio-controller; |
| 110 | #gpio-cells = <2>; |
| 111 | interrupt-controller; |
| 112 | #interrupt-cells = <1>; |
| 113 | }; |
| 114 | |
| 115 | gpio4: gpio@48059000 { |
| 116 | compatible = "ti,omap4-gpio"; |
| 117 | ti,hwmods = "gpio4"; |
| 118 | gpio-controller; |
| 119 | #gpio-cells = <2>; |
| 120 | interrupt-controller; |
| 121 | #interrupt-cells = <1>; |
| 122 | }; |
| 123 | |
| 124 | gpio5: gpio@4805b000 { |
| 125 | compatible = "ti,omap4-gpio"; |
| 126 | ti,hwmods = "gpio5"; |
| 127 | gpio-controller; |
| 128 | #gpio-cells = <2>; |
| 129 | interrupt-controller; |
| 130 | #interrupt-cells = <1>; |
| 131 | }; |
| 132 | |
| 133 | gpio6: gpio@4805d000 { |
| 134 | compatible = "ti,omap4-gpio"; |
| 135 | ti,hwmods = "gpio6"; |
| 136 | gpio-controller; |
| 137 | #gpio-cells = <2>; |
| 138 | interrupt-controller; |
| 139 | #interrupt-cells = <1>; |
| 140 | }; |
| 141 | |
| 142 | gpio7: gpio@48051000 { |
| 143 | compatible = "ti,omap4-gpio"; |
| 144 | ti,hwmods = "gpio7"; |
| 145 | gpio-controller; |
| 146 | #gpio-cells = <2>; |
| 147 | interrupt-controller; |
| 148 | #interrupt-cells = <1>; |
| 149 | }; |
| 150 | |
| 151 | gpio8: gpio@48053000 { |
| 152 | compatible = "ti,omap4-gpio"; |
| 153 | ti,hwmods = "gpio8"; |
| 154 | gpio-controller; |
| 155 | #gpio-cells = <2>; |
| 156 | interrupt-controller; |
| 157 | #interrupt-cells = <1>; |
| 158 | }; |
| 159 | |
| 160 | uart1: serial@4806a000 { |
| 161 | compatible = "ti,omap4-uart"; |
| 162 | ti,hwmods = "uart1"; |
| 163 | clock-frequency = <48000000>; |
| 164 | }; |
| 165 | |
| 166 | uart2: serial@4806c000 { |
| 167 | compatible = "ti,omap4-uart"; |
| 168 | ti,hwmods = "uart2"; |
| 169 | clock-frequency = <48000000>; |
| 170 | }; |
| 171 | |
| 172 | uart3: serial@48020000 { |
| 173 | compatible = "ti,omap4-uart"; |
| 174 | ti,hwmods = "uart3"; |
| 175 | clock-frequency = <48000000>; |
| 176 | }; |
| 177 | |
| 178 | uart4: serial@4806e000 { |
| 179 | compatible = "ti,omap4-uart"; |
| 180 | ti,hwmods = "uart4"; |
| 181 | clock-frequency = <48000000>; |
| 182 | }; |
| 183 | |
| 184 | uart5: serial@48066000 { |
| 185 | compatible = "ti,omap5-uart"; |
| 186 | ti,hwmods = "uart5"; |
| 187 | clock-frequency = <48000000>; |
| 188 | }; |
| 189 | |
| 190 | uart6: serial@48068000 { |
| 191 | compatible = "ti,omap6-uart"; |
| 192 | ti,hwmods = "uart6"; |
| 193 | clock-frequency = <48000000>; |
| 194 | }; |
| 195 | }; |
| 196 | }; |