Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 13 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 14 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 15 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 18 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 19 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 20 | #include <plat/gpio.h> |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 21 | #include <plat/mcspi.h> |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 22 | #include <plat/l3_2xxx.h> |
| 23 | #include <plat/l4_2xxx.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 24 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 25 | #include "omap_hwmod_common_data.h" |
| 26 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 27 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 28 | #include "prm-regbits-24xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 29 | #include "wd_timer.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 30 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 31 | /* |
| 32 | * OMAP2420 hardware module integration data |
| 33 | * |
| 34 | * ALl of the data in this section should be autogeneratable from the |
| 35 | * TI hardware database or other technical documentation. Data that |
| 36 | * is driver-specific or driver-kernel integration-specific belongs |
| 37 | * elsewhere. |
| 38 | */ |
| 39 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 40 | static struct omap_hwmod omap2420_mpu_hwmod; |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 41 | static struct omap_hwmod omap2420_iva_hwmod; |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 42 | static struct omap_hwmod omap2420_l3_main_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 43 | static struct omap_hwmod omap2420_l4_core_hwmod; |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 44 | static struct omap_hwmod omap2420_dss_core_hwmod; |
| 45 | static struct omap_hwmod omap2420_dss_dispc_hwmod; |
| 46 | static struct omap_hwmod omap2420_dss_rfbi_hwmod; |
| 47 | static struct omap_hwmod omap2420_dss_venc_hwmod; |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 48 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 49 | static struct omap_hwmod omap2420_gpio1_hwmod; |
| 50 | static struct omap_hwmod omap2420_gpio2_hwmod; |
| 51 | static struct omap_hwmod omap2420_gpio3_hwmod; |
| 52 | static struct omap_hwmod omap2420_gpio4_hwmod; |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 53 | static struct omap_hwmod omap2420_dma_system_hwmod; |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 54 | static struct omap_hwmod omap2420_mcspi1_hwmod; |
| 55 | static struct omap_hwmod omap2420_mcspi2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 56 | |
| 57 | /* L3 -> L4_CORE interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 58 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 59 | .master = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 60 | .slave = &omap2420_l4_core_hwmod, |
| 61 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 62 | }; |
| 63 | |
| 64 | /* MPU -> L3 interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 65 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 66 | .master = &omap2420_mpu_hwmod, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 67 | .slave = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 68 | .user = OCP_USER_MPU, |
| 69 | }; |
| 70 | |
| 71 | /* Slave interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 72 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
| 73 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 74 | }; |
| 75 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 76 | /* DSS -> l3 */ |
| 77 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { |
| 78 | .master = &omap2420_dss_core_hwmod, |
| 79 | .slave = &omap2420_l3_main_hwmod, |
| 80 | .fw = { |
| 81 | .omap2 = { |
| 82 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, |
| 83 | .flags = OMAP_FIREWALL_L3, |
| 84 | } |
| 85 | }, |
| 86 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 87 | }; |
| 88 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 89 | /* Master interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 90 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
| 91 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 95 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 96 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 97 | .class = &l3_hwmod_class, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 98 | .masters = omap2420_l3_main_masters, |
| 99 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), |
| 100 | .slaves = omap2420_l3_main_slaves, |
| 101 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 103 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | static struct omap_hwmod omap2420_l4_wkup_hwmod; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 107 | static struct omap_hwmod omap2420_uart1_hwmod; |
| 108 | static struct omap_hwmod omap2420_uart2_hwmod; |
| 109 | static struct omap_hwmod omap2420_uart3_hwmod; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 110 | static struct omap_hwmod omap2420_i2c1_hwmod; |
| 111 | static struct omap_hwmod omap2420_i2c2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 112 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 113 | /* l4 core -> mcspi1 interface */ |
| 114 | static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { |
| 115 | { |
| 116 | .pa_start = 0x48098000, |
| 117 | .pa_end = 0x480980ff, |
| 118 | .flags = ADDR_TYPE_RT, |
| 119 | }, |
| 120 | }; |
| 121 | |
| 122 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
| 123 | .master = &omap2420_l4_core_hwmod, |
| 124 | .slave = &omap2420_mcspi1_hwmod, |
| 125 | .clk = "mcspi1_ick", |
| 126 | .addr = omap2420_mcspi1_addr_space, |
| 127 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), |
| 128 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 129 | }; |
| 130 | |
| 131 | /* l4 core -> mcspi2 interface */ |
| 132 | static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { |
| 133 | { |
| 134 | .pa_start = 0x4809a000, |
| 135 | .pa_end = 0x4809a0ff, |
| 136 | .flags = ADDR_TYPE_RT, |
| 137 | }, |
| 138 | }; |
| 139 | |
| 140 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
| 141 | .master = &omap2420_l4_core_hwmod, |
| 142 | .slave = &omap2420_mcspi2_hwmod, |
| 143 | .clk = "mcspi2_ick", |
| 144 | .addr = omap2420_mcspi2_addr_space, |
| 145 | .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), |
| 146 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 147 | }; |
| 148 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 149 | /* L4_CORE -> L4_WKUP interface */ |
| 150 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| 151 | .master = &omap2420_l4_core_hwmod, |
| 152 | .slave = &omap2420_l4_wkup_hwmod, |
| 153 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 154 | }; |
| 155 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 156 | /* L4 CORE -> UART1 interface */ |
| 157 | static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { |
| 158 | { |
| 159 | .pa_start = OMAP2_UART1_BASE, |
| 160 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, |
| 161 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 162 | }, |
| 163 | }; |
| 164 | |
| 165 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 166 | .master = &omap2420_l4_core_hwmod, |
| 167 | .slave = &omap2420_uart1_hwmod, |
| 168 | .clk = "uart1_ick", |
| 169 | .addr = omap2420_uart1_addr_space, |
| 170 | .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), |
| 171 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 172 | }; |
| 173 | |
| 174 | /* L4 CORE -> UART2 interface */ |
| 175 | static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { |
| 176 | { |
| 177 | .pa_start = OMAP2_UART2_BASE, |
| 178 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, |
| 179 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 180 | }, |
| 181 | }; |
| 182 | |
| 183 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 184 | .master = &omap2420_l4_core_hwmod, |
| 185 | .slave = &omap2420_uart2_hwmod, |
| 186 | .clk = "uart2_ick", |
| 187 | .addr = omap2420_uart2_addr_space, |
| 188 | .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), |
| 189 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 190 | }; |
| 191 | |
| 192 | /* L4 PER -> UART3 interface */ |
| 193 | static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { |
| 194 | { |
| 195 | .pa_start = OMAP2_UART3_BASE, |
| 196 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, |
| 197 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 198 | }, |
| 199 | }; |
| 200 | |
| 201 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 202 | .master = &omap2420_l4_core_hwmod, |
| 203 | .slave = &omap2420_uart3_hwmod, |
| 204 | .clk = "uart3_ick", |
| 205 | .addr = omap2420_uart3_addr_space, |
| 206 | .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), |
| 207 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 208 | }; |
| 209 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 210 | /* I2C IP block address space length (in bytes) */ |
| 211 | #define OMAP2_I2C_AS_LEN 128 |
| 212 | |
| 213 | /* L4 CORE -> I2C1 interface */ |
| 214 | static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { |
| 215 | { |
| 216 | .pa_start = 0x48070000, |
| 217 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, |
| 218 | .flags = ADDR_TYPE_RT, |
| 219 | }, |
| 220 | }; |
| 221 | |
| 222 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
| 223 | .master = &omap2420_l4_core_hwmod, |
| 224 | .slave = &omap2420_i2c1_hwmod, |
| 225 | .clk = "i2c1_ick", |
| 226 | .addr = omap2420_i2c1_addr_space, |
| 227 | .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), |
| 228 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 229 | }; |
| 230 | |
| 231 | /* L4 CORE -> I2C2 interface */ |
| 232 | static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { |
| 233 | { |
| 234 | .pa_start = 0x48072000, |
| 235 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, |
| 236 | .flags = ADDR_TYPE_RT, |
| 237 | }, |
| 238 | }; |
| 239 | |
| 240 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
| 241 | .master = &omap2420_l4_core_hwmod, |
| 242 | .slave = &omap2420_i2c2_hwmod, |
| 243 | .clk = "i2c2_ick", |
| 244 | .addr = omap2420_i2c2_addr_space, |
| 245 | .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), |
| 246 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 247 | }; |
| 248 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 249 | /* Slave interfaces on the L4_CORE interconnect */ |
| 250 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 251 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | /* Master interfaces on the L4_CORE interconnect */ |
| 255 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { |
| 256 | &omap2420_l4_core__l4_wkup, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 257 | &omap2_l4_core__uart1, |
| 258 | &omap2_l4_core__uart2, |
| 259 | &omap2_l4_core__uart3, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 260 | &omap2420_l4_core__i2c1, |
| 261 | &omap2420_l4_core__i2c2 |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 262 | }; |
| 263 | |
| 264 | /* L4 CORE */ |
| 265 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 266 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 267 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 268 | .masters = omap2420_l4_core_masters, |
| 269 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 270 | .slaves = omap2420_l4_core_slaves, |
| 271 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 272 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 273 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 274 | }; |
| 275 | |
| 276 | /* Slave interfaces on the L4_WKUP interconnect */ |
| 277 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { |
| 278 | &omap2420_l4_core__l4_wkup, |
| 279 | }; |
| 280 | |
| 281 | /* Master interfaces on the L4_WKUP interconnect */ |
| 282 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { |
| 283 | }; |
| 284 | |
| 285 | /* L4 WKUP */ |
| 286 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 287 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 288 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 289 | .masters = omap2420_l4_wkup_masters, |
| 290 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 291 | .slaves = omap2420_l4_wkup_slaves, |
| 292 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 293 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 294 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 295 | }; |
| 296 | |
| 297 | /* Master interfaces on the MPU device */ |
| 298 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 299 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 300 | }; |
| 301 | |
| 302 | /* MPU */ |
| 303 | static struct omap_hwmod omap2420_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 304 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 305 | .class = &mpu_hwmod_class, |
Paul Walmsley | 50ebdac | 2010-02-22 22:09:31 -0700 | [diff] [blame] | 306 | .main_clk = "mpu_ck", |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 307 | .masters = omap2420_mpu_masters, |
| 308 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
| 309 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 310 | }; |
| 311 | |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 312 | /* |
| 313 | * IVA1 interface data |
| 314 | */ |
| 315 | |
| 316 | /* IVA <- L3 interface */ |
| 317 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
| 318 | .master = &omap2420_l3_main_hwmod, |
| 319 | .slave = &omap2420_iva_hwmod, |
| 320 | .clk = "iva1_ifck", |
| 321 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 322 | }; |
| 323 | |
| 324 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { |
| 325 | &omap2420_l3__iva, |
| 326 | }; |
| 327 | |
| 328 | /* |
| 329 | * IVA2 (IVA2) |
| 330 | */ |
| 331 | |
| 332 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 333 | .name = "iva", |
| 334 | .class = &iva_hwmod_class, |
| 335 | .masters = omap2420_iva_masters, |
| 336 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), |
| 337 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 338 | }; |
| 339 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 340 | /* l4_wkup -> wd_timer2 */ |
| 341 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 342 | { |
| 343 | .pa_start = 0x48022000, |
| 344 | .pa_end = 0x4802207f, |
| 345 | .flags = ADDR_TYPE_RT |
| 346 | }, |
| 347 | }; |
| 348 | |
| 349 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
| 350 | .master = &omap2420_l4_wkup_hwmod, |
| 351 | .slave = &omap2420_wd_timer2_hwmod, |
| 352 | .clk = "mpu_wdt_ick", |
| 353 | .addr = omap2420_wd_timer2_addrs, |
| 354 | .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), |
| 355 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 356 | }; |
| 357 | |
| 358 | /* |
| 359 | * 'wd_timer' class |
| 360 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 361 | * overflow condition |
| 362 | */ |
| 363 | |
| 364 | static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { |
| 365 | .rev_offs = 0x0000, |
| 366 | .sysc_offs = 0x0010, |
| 367 | .syss_offs = 0x0014, |
| 368 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 369 | SYSC_HAS_AUTOIDLE), |
| 370 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 371 | }; |
| 372 | |
| 373 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 374 | .name = "wd_timer", |
| 375 | .sysc = &omap2420_wd_timer_sysc, |
| 376 | .pre_shutdown = &omap2_wd_timer_disable |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 377 | }; |
| 378 | |
| 379 | /* wd_timer2 */ |
| 380 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { |
| 381 | &omap2420_l4_wkup__wd_timer2, |
| 382 | }; |
| 383 | |
| 384 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
| 385 | .name = "wd_timer2", |
| 386 | .class = &omap2420_wd_timer_hwmod_class, |
| 387 | .main_clk = "mpu_wdt_fck", |
| 388 | .prcm = { |
| 389 | .omap2 = { |
| 390 | .prcm_reg_id = 1, |
| 391 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 392 | .module_offs = WKUP_MOD, |
| 393 | .idlest_reg_id = 1, |
| 394 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 395 | }, |
| 396 | }, |
| 397 | .slaves = omap2420_wd_timer2_slaves, |
| 398 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), |
| 399 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 400 | }; |
| 401 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 402 | /* UART */ |
| 403 | |
| 404 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 405 | .rev_offs = 0x50, |
| 406 | .sysc_offs = 0x54, |
| 407 | .syss_offs = 0x58, |
| 408 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 409 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 410 | SYSC_HAS_AUTOIDLE), |
| 411 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 412 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 413 | }; |
| 414 | |
| 415 | static struct omap_hwmod_class uart_class = { |
| 416 | .name = "uart", |
| 417 | .sysc = &uart_sysc, |
| 418 | }; |
| 419 | |
| 420 | /* UART1 */ |
| 421 | |
| 422 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { |
| 423 | { .irq = INT_24XX_UART1_IRQ, }, |
| 424 | }; |
| 425 | |
| 426 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { |
| 427 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 428 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 429 | }; |
| 430 | |
| 431 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { |
| 432 | &omap2_l4_core__uart1, |
| 433 | }; |
| 434 | |
| 435 | static struct omap_hwmod omap2420_uart1_hwmod = { |
| 436 | .name = "uart1", |
| 437 | .mpu_irqs = uart1_mpu_irqs, |
| 438 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), |
| 439 | .sdma_reqs = uart1_sdma_reqs, |
| 440 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), |
| 441 | .main_clk = "uart1_fck", |
| 442 | .prcm = { |
| 443 | .omap2 = { |
| 444 | .module_offs = CORE_MOD, |
| 445 | .prcm_reg_id = 1, |
| 446 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 447 | .idlest_reg_id = 1, |
| 448 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 449 | }, |
| 450 | }, |
| 451 | .slaves = omap2420_uart1_slaves, |
| 452 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), |
| 453 | .class = &uart_class, |
| 454 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 455 | }; |
| 456 | |
| 457 | /* UART2 */ |
| 458 | |
| 459 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { |
| 460 | { .irq = INT_24XX_UART2_IRQ, }, |
| 461 | }; |
| 462 | |
| 463 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { |
| 464 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 465 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 466 | }; |
| 467 | |
| 468 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { |
| 469 | &omap2_l4_core__uart2, |
| 470 | }; |
| 471 | |
| 472 | static struct omap_hwmod omap2420_uart2_hwmod = { |
| 473 | .name = "uart2", |
| 474 | .mpu_irqs = uart2_mpu_irqs, |
| 475 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), |
| 476 | .sdma_reqs = uart2_sdma_reqs, |
| 477 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), |
| 478 | .main_clk = "uart2_fck", |
| 479 | .prcm = { |
| 480 | .omap2 = { |
| 481 | .module_offs = CORE_MOD, |
| 482 | .prcm_reg_id = 1, |
| 483 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 484 | .idlest_reg_id = 1, |
| 485 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 486 | }, |
| 487 | }, |
| 488 | .slaves = omap2420_uart2_slaves, |
| 489 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), |
| 490 | .class = &uart_class, |
| 491 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 492 | }; |
| 493 | |
| 494 | /* UART3 */ |
| 495 | |
| 496 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { |
| 497 | { .irq = INT_24XX_UART3_IRQ, }, |
| 498 | }; |
| 499 | |
| 500 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { |
| 501 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 502 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 503 | }; |
| 504 | |
| 505 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { |
| 506 | &omap2_l4_core__uart3, |
| 507 | }; |
| 508 | |
| 509 | static struct omap_hwmod omap2420_uart3_hwmod = { |
| 510 | .name = "uart3", |
| 511 | .mpu_irqs = uart3_mpu_irqs, |
| 512 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), |
| 513 | .sdma_reqs = uart3_sdma_reqs, |
| 514 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), |
| 515 | .main_clk = "uart3_fck", |
| 516 | .prcm = { |
| 517 | .omap2 = { |
| 518 | .module_offs = CORE_MOD, |
| 519 | .prcm_reg_id = 2, |
| 520 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 521 | .idlest_reg_id = 2, |
| 522 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 523 | }, |
| 524 | }, |
| 525 | .slaves = omap2420_uart3_slaves, |
| 526 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), |
| 527 | .class = &uart_class, |
| 528 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 529 | }; |
| 530 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 531 | /* |
| 532 | * 'dss' class |
| 533 | * display sub-system |
| 534 | */ |
| 535 | |
| 536 | static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { |
| 537 | .rev_offs = 0x0000, |
| 538 | .sysc_offs = 0x0010, |
| 539 | .syss_offs = 0x0014, |
| 540 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 541 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 542 | }; |
| 543 | |
| 544 | static struct omap_hwmod_class omap2420_dss_hwmod_class = { |
| 545 | .name = "dss", |
| 546 | .sysc = &omap2420_dss_sysc, |
| 547 | }; |
| 548 | |
| 549 | /* dss */ |
| 550 | static struct omap_hwmod_irq_info omap2420_dss_irqs[] = { |
| 551 | { .irq = 25 }, |
| 552 | }; |
| 553 | |
| 554 | static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { |
| 555 | { .name = "dispc", .dma_req = 5 }, |
| 556 | }; |
| 557 | |
| 558 | /* dss */ |
| 559 | /* dss master ports */ |
| 560 | static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { |
| 561 | &omap2420_dss__l3, |
| 562 | }; |
| 563 | |
| 564 | static struct omap_hwmod_addr_space omap2420_dss_addrs[] = { |
| 565 | { |
| 566 | .pa_start = 0x48050000, |
| 567 | .pa_end = 0x480503FF, |
| 568 | .flags = ADDR_TYPE_RT |
| 569 | }, |
| 570 | }; |
| 571 | |
| 572 | /* l4_core -> dss */ |
| 573 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { |
| 574 | .master = &omap2420_l4_core_hwmod, |
| 575 | .slave = &omap2420_dss_core_hwmod, |
| 576 | .clk = "dss_ick", |
| 577 | .addr = omap2420_dss_addrs, |
| 578 | .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs), |
| 579 | .fw = { |
| 580 | .omap2 = { |
| 581 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 582 | .flags = OMAP_FIREWALL_L4, |
| 583 | } |
| 584 | }, |
| 585 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 586 | }; |
| 587 | |
| 588 | /* dss slave ports */ |
| 589 | static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { |
| 590 | &omap2420_l4_core__dss, |
| 591 | }; |
| 592 | |
| 593 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
| 594 | { .role = "tv_clk", .clk = "dss_54m_fck" }, |
| 595 | { .role = "sys_clk", .clk = "dss2_fck" }, |
| 596 | }; |
| 597 | |
| 598 | static struct omap_hwmod omap2420_dss_core_hwmod = { |
| 599 | .name = "dss_core", |
| 600 | .class = &omap2420_dss_hwmod_class, |
| 601 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
| 602 | .mpu_irqs = omap2420_dss_irqs, |
| 603 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs), |
| 604 | .sdma_reqs = omap2420_dss_sdma_chs, |
| 605 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), |
| 606 | .prcm = { |
| 607 | .omap2 = { |
| 608 | .prcm_reg_id = 1, |
| 609 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 610 | .module_offs = CORE_MOD, |
| 611 | .idlest_reg_id = 1, |
| 612 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 613 | }, |
| 614 | }, |
| 615 | .opt_clks = dss_opt_clks, |
| 616 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), |
| 617 | .slaves = omap2420_dss_slaves, |
| 618 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), |
| 619 | .masters = omap2420_dss_masters, |
| 620 | .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), |
| 621 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 622 | .flags = HWMOD_NO_IDLEST, |
| 623 | }; |
| 624 | |
| 625 | /* |
| 626 | * 'dispc' class |
| 627 | * display controller |
| 628 | */ |
| 629 | |
| 630 | static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { |
| 631 | .rev_offs = 0x0000, |
| 632 | .sysc_offs = 0x0010, |
| 633 | .syss_offs = 0x0014, |
| 634 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
| 635 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 636 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 637 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 638 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 639 | }; |
| 640 | |
| 641 | static struct omap_hwmod_class omap2420_dispc_hwmod_class = { |
| 642 | .name = "dispc", |
| 643 | .sysc = &omap2420_dispc_sysc, |
| 644 | }; |
| 645 | |
| 646 | static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { |
| 647 | { |
| 648 | .pa_start = 0x48050400, |
| 649 | .pa_end = 0x480507FF, |
| 650 | .flags = ADDR_TYPE_RT |
| 651 | }, |
| 652 | }; |
| 653 | |
| 654 | /* l4_core -> dss_dispc */ |
| 655 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { |
| 656 | .master = &omap2420_l4_core_hwmod, |
| 657 | .slave = &omap2420_dss_dispc_hwmod, |
| 658 | .clk = "dss_ick", |
| 659 | .addr = omap2420_dss_dispc_addrs, |
| 660 | .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs), |
| 661 | .fw = { |
| 662 | .omap2 = { |
| 663 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, |
| 664 | .flags = OMAP_FIREWALL_L4, |
| 665 | } |
| 666 | }, |
| 667 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 668 | }; |
| 669 | |
| 670 | /* dss_dispc slave ports */ |
| 671 | static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { |
| 672 | &omap2420_l4_core__dss_dispc, |
| 673 | }; |
| 674 | |
| 675 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { |
| 676 | .name = "dss_dispc", |
| 677 | .class = &omap2420_dispc_hwmod_class, |
| 678 | .main_clk = "dss1_fck", |
| 679 | .prcm = { |
| 680 | .omap2 = { |
| 681 | .prcm_reg_id = 1, |
| 682 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 683 | .module_offs = CORE_MOD, |
| 684 | .idlest_reg_id = 1, |
| 685 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 686 | }, |
| 687 | }, |
| 688 | .slaves = omap2420_dss_dispc_slaves, |
| 689 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), |
| 690 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 691 | .flags = HWMOD_NO_IDLEST, |
| 692 | }; |
| 693 | |
| 694 | /* |
| 695 | * 'rfbi' class |
| 696 | * remote frame buffer interface |
| 697 | */ |
| 698 | |
| 699 | static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { |
| 700 | .rev_offs = 0x0000, |
| 701 | .sysc_offs = 0x0010, |
| 702 | .syss_offs = 0x0014, |
| 703 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 704 | SYSC_HAS_AUTOIDLE), |
| 705 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 706 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 707 | }; |
| 708 | |
| 709 | static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { |
| 710 | .name = "rfbi", |
| 711 | .sysc = &omap2420_rfbi_sysc, |
| 712 | }; |
| 713 | |
| 714 | static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = { |
| 715 | { |
| 716 | .pa_start = 0x48050800, |
| 717 | .pa_end = 0x48050BFF, |
| 718 | .flags = ADDR_TYPE_RT |
| 719 | }, |
| 720 | }; |
| 721 | |
| 722 | /* l4_core -> dss_rfbi */ |
| 723 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { |
| 724 | .master = &omap2420_l4_core_hwmod, |
| 725 | .slave = &omap2420_dss_rfbi_hwmod, |
| 726 | .clk = "dss_ick", |
| 727 | .addr = omap2420_dss_rfbi_addrs, |
| 728 | .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs), |
| 729 | .fw = { |
| 730 | .omap2 = { |
| 731 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 732 | .flags = OMAP_FIREWALL_L4, |
| 733 | } |
| 734 | }, |
| 735 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 736 | }; |
| 737 | |
| 738 | /* dss_rfbi slave ports */ |
| 739 | static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { |
| 740 | &omap2420_l4_core__dss_rfbi, |
| 741 | }; |
| 742 | |
| 743 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { |
| 744 | .name = "dss_rfbi", |
| 745 | .class = &omap2420_rfbi_hwmod_class, |
| 746 | .main_clk = "dss1_fck", |
| 747 | .prcm = { |
| 748 | .omap2 = { |
| 749 | .prcm_reg_id = 1, |
| 750 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 751 | .module_offs = CORE_MOD, |
| 752 | }, |
| 753 | }, |
| 754 | .slaves = omap2420_dss_rfbi_slaves, |
| 755 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), |
| 756 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 757 | .flags = HWMOD_NO_IDLEST, |
| 758 | }; |
| 759 | |
| 760 | /* |
| 761 | * 'venc' class |
| 762 | * video encoder |
| 763 | */ |
| 764 | |
| 765 | static struct omap_hwmod_class omap2420_venc_hwmod_class = { |
| 766 | .name = "venc", |
| 767 | }; |
| 768 | |
| 769 | /* dss_venc */ |
| 770 | static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = { |
| 771 | { |
| 772 | .pa_start = 0x48050C00, |
| 773 | .pa_end = 0x48050FFF, |
| 774 | .flags = ADDR_TYPE_RT |
| 775 | }, |
| 776 | }; |
| 777 | |
| 778 | /* l4_core -> dss_venc */ |
| 779 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { |
| 780 | .master = &omap2420_l4_core_hwmod, |
| 781 | .slave = &omap2420_dss_venc_hwmod, |
| 782 | .clk = "dss_54m_fck", |
| 783 | .addr = omap2420_dss_venc_addrs, |
| 784 | .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs), |
| 785 | .fw = { |
| 786 | .omap2 = { |
| 787 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, |
| 788 | .flags = OMAP_FIREWALL_L4, |
| 789 | } |
| 790 | }, |
| 791 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 792 | }; |
| 793 | |
| 794 | /* dss_venc slave ports */ |
| 795 | static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { |
| 796 | &omap2420_l4_core__dss_venc, |
| 797 | }; |
| 798 | |
| 799 | static struct omap_hwmod omap2420_dss_venc_hwmod = { |
| 800 | .name = "dss_venc", |
| 801 | .class = &omap2420_venc_hwmod_class, |
| 802 | .main_clk = "dss1_fck", |
| 803 | .prcm = { |
| 804 | .omap2 = { |
| 805 | .prcm_reg_id = 1, |
| 806 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 807 | .module_offs = CORE_MOD, |
| 808 | }, |
| 809 | }, |
| 810 | .slaves = omap2420_dss_venc_slaves, |
| 811 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), |
| 812 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 813 | .flags = HWMOD_NO_IDLEST, |
| 814 | }; |
| 815 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 816 | /* I2C common */ |
| 817 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 818 | .rev_offs = 0x00, |
| 819 | .sysc_offs = 0x20, |
| 820 | .syss_offs = 0x10, |
| 821 | .sysc_flags = SYSC_HAS_SOFTRESET, |
| 822 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 823 | }; |
| 824 | |
| 825 | static struct omap_hwmod_class i2c_class = { |
| 826 | .name = "i2c", |
| 827 | .sysc = &i2c_sysc, |
| 828 | }; |
| 829 | |
| 830 | static struct omap_i2c_dev_attr i2c_dev_attr; |
| 831 | |
| 832 | /* I2C1 */ |
| 833 | |
| 834 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
| 835 | { .irq = INT_24XX_I2C1_IRQ, }, |
| 836 | }; |
| 837 | |
| 838 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { |
| 839 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 840 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 841 | }; |
| 842 | |
| 843 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { |
| 844 | &omap2420_l4_core__i2c1, |
| 845 | }; |
| 846 | |
| 847 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 848 | .name = "i2c1", |
| 849 | .mpu_irqs = i2c1_mpu_irqs, |
| 850 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), |
| 851 | .sdma_reqs = i2c1_sdma_reqs, |
| 852 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), |
| 853 | .main_clk = "i2c1_fck", |
| 854 | .prcm = { |
| 855 | .omap2 = { |
| 856 | .module_offs = CORE_MOD, |
| 857 | .prcm_reg_id = 1, |
| 858 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 859 | .idlest_reg_id = 1, |
| 860 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 861 | }, |
| 862 | }, |
| 863 | .slaves = omap2420_i2c1_slaves, |
| 864 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), |
| 865 | .class = &i2c_class, |
| 866 | .dev_attr = &i2c_dev_attr, |
| 867 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 868 | .flags = HWMOD_16BIT_REG, |
| 869 | }; |
| 870 | |
| 871 | /* I2C2 */ |
| 872 | |
| 873 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
| 874 | { .irq = INT_24XX_I2C2_IRQ, }, |
| 875 | }; |
| 876 | |
| 877 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { |
| 878 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 879 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 880 | }; |
| 881 | |
| 882 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { |
| 883 | &omap2420_l4_core__i2c2, |
| 884 | }; |
| 885 | |
| 886 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 887 | .name = "i2c2", |
| 888 | .mpu_irqs = i2c2_mpu_irqs, |
| 889 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), |
| 890 | .sdma_reqs = i2c2_sdma_reqs, |
| 891 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), |
| 892 | .main_clk = "i2c2_fck", |
| 893 | .prcm = { |
| 894 | .omap2 = { |
| 895 | .module_offs = CORE_MOD, |
| 896 | .prcm_reg_id = 1, |
| 897 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 898 | .idlest_reg_id = 1, |
| 899 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 900 | }, |
| 901 | }, |
| 902 | .slaves = omap2420_i2c2_slaves, |
| 903 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), |
| 904 | .class = &i2c_class, |
| 905 | .dev_attr = &i2c_dev_attr, |
| 906 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 907 | .flags = HWMOD_16BIT_REG, |
| 908 | }; |
| 909 | |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 910 | /* l4_wkup -> gpio1 */ |
| 911 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { |
| 912 | { |
| 913 | .pa_start = 0x48018000, |
| 914 | .pa_end = 0x480181ff, |
| 915 | .flags = ADDR_TYPE_RT |
| 916 | }, |
| 917 | }; |
| 918 | |
| 919 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { |
| 920 | .master = &omap2420_l4_wkup_hwmod, |
| 921 | .slave = &omap2420_gpio1_hwmod, |
| 922 | .clk = "gpios_ick", |
| 923 | .addr = omap2420_gpio1_addr_space, |
| 924 | .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space), |
| 925 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 926 | }; |
| 927 | |
| 928 | /* l4_wkup -> gpio2 */ |
| 929 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { |
| 930 | { |
| 931 | .pa_start = 0x4801a000, |
| 932 | .pa_end = 0x4801a1ff, |
| 933 | .flags = ADDR_TYPE_RT |
| 934 | }, |
| 935 | }; |
| 936 | |
| 937 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { |
| 938 | .master = &omap2420_l4_wkup_hwmod, |
| 939 | .slave = &omap2420_gpio2_hwmod, |
| 940 | .clk = "gpios_ick", |
| 941 | .addr = omap2420_gpio2_addr_space, |
| 942 | .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space), |
| 943 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 944 | }; |
| 945 | |
| 946 | /* l4_wkup -> gpio3 */ |
| 947 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { |
| 948 | { |
| 949 | .pa_start = 0x4801c000, |
| 950 | .pa_end = 0x4801c1ff, |
| 951 | .flags = ADDR_TYPE_RT |
| 952 | }, |
| 953 | }; |
| 954 | |
| 955 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { |
| 956 | .master = &omap2420_l4_wkup_hwmod, |
| 957 | .slave = &omap2420_gpio3_hwmod, |
| 958 | .clk = "gpios_ick", |
| 959 | .addr = omap2420_gpio3_addr_space, |
| 960 | .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space), |
| 961 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 962 | }; |
| 963 | |
| 964 | /* l4_wkup -> gpio4 */ |
| 965 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { |
| 966 | { |
| 967 | .pa_start = 0x4801e000, |
| 968 | .pa_end = 0x4801e1ff, |
| 969 | .flags = ADDR_TYPE_RT |
| 970 | }, |
| 971 | }; |
| 972 | |
| 973 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { |
| 974 | .master = &omap2420_l4_wkup_hwmod, |
| 975 | .slave = &omap2420_gpio4_hwmod, |
| 976 | .clk = "gpios_ick", |
| 977 | .addr = omap2420_gpio4_addr_space, |
| 978 | .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space), |
| 979 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 980 | }; |
| 981 | |
| 982 | /* gpio dev_attr */ |
| 983 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 984 | .bank_width = 32, |
| 985 | .dbck_flag = false, |
| 986 | }; |
| 987 | |
| 988 | static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { |
| 989 | .rev_offs = 0x0000, |
| 990 | .sysc_offs = 0x0010, |
| 991 | .syss_offs = 0x0014, |
| 992 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 993 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 994 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 995 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 996 | }; |
| 997 | |
| 998 | /* |
| 999 | * 'gpio' class |
| 1000 | * general purpose io module |
| 1001 | */ |
| 1002 | static struct omap_hwmod_class omap242x_gpio_hwmod_class = { |
| 1003 | .name = "gpio", |
| 1004 | .sysc = &omap242x_gpio_sysc, |
| 1005 | .rev = 0, |
| 1006 | }; |
| 1007 | |
| 1008 | /* gpio1 */ |
| 1009 | static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { |
| 1010 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ |
| 1011 | }; |
| 1012 | |
| 1013 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { |
| 1014 | &omap2420_l4_wkup__gpio1, |
| 1015 | }; |
| 1016 | |
| 1017 | static struct omap_hwmod omap2420_gpio1_hwmod = { |
| 1018 | .name = "gpio1", |
| 1019 | .mpu_irqs = omap242x_gpio1_irqs, |
| 1020 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), |
| 1021 | .main_clk = "gpios_fck", |
| 1022 | .prcm = { |
| 1023 | .omap2 = { |
| 1024 | .prcm_reg_id = 1, |
| 1025 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1026 | .module_offs = WKUP_MOD, |
| 1027 | .idlest_reg_id = 1, |
| 1028 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1029 | }, |
| 1030 | }, |
| 1031 | .slaves = omap2420_gpio1_slaves, |
| 1032 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), |
| 1033 | .class = &omap242x_gpio_hwmod_class, |
| 1034 | .dev_attr = &gpio_dev_attr, |
| 1035 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1036 | }; |
| 1037 | |
| 1038 | /* gpio2 */ |
| 1039 | static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { |
| 1040 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ |
| 1041 | }; |
| 1042 | |
| 1043 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { |
| 1044 | &omap2420_l4_wkup__gpio2, |
| 1045 | }; |
| 1046 | |
| 1047 | static struct omap_hwmod omap2420_gpio2_hwmod = { |
| 1048 | .name = "gpio2", |
| 1049 | .mpu_irqs = omap242x_gpio2_irqs, |
| 1050 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), |
| 1051 | .main_clk = "gpios_fck", |
| 1052 | .prcm = { |
| 1053 | .omap2 = { |
| 1054 | .prcm_reg_id = 1, |
| 1055 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1056 | .module_offs = WKUP_MOD, |
| 1057 | .idlest_reg_id = 1, |
| 1058 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1059 | }, |
| 1060 | }, |
| 1061 | .slaves = omap2420_gpio2_slaves, |
| 1062 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), |
| 1063 | .class = &omap242x_gpio_hwmod_class, |
| 1064 | .dev_attr = &gpio_dev_attr, |
| 1065 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1066 | }; |
| 1067 | |
| 1068 | /* gpio3 */ |
| 1069 | static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { |
| 1070 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ |
| 1071 | }; |
| 1072 | |
| 1073 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { |
| 1074 | &omap2420_l4_wkup__gpio3, |
| 1075 | }; |
| 1076 | |
| 1077 | static struct omap_hwmod omap2420_gpio3_hwmod = { |
| 1078 | .name = "gpio3", |
| 1079 | .mpu_irqs = omap242x_gpio3_irqs, |
| 1080 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), |
| 1081 | .main_clk = "gpios_fck", |
| 1082 | .prcm = { |
| 1083 | .omap2 = { |
| 1084 | .prcm_reg_id = 1, |
| 1085 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1086 | .module_offs = WKUP_MOD, |
| 1087 | .idlest_reg_id = 1, |
| 1088 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1089 | }, |
| 1090 | }, |
| 1091 | .slaves = omap2420_gpio3_slaves, |
| 1092 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), |
| 1093 | .class = &omap242x_gpio_hwmod_class, |
| 1094 | .dev_attr = &gpio_dev_attr, |
| 1095 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1096 | }; |
| 1097 | |
| 1098 | /* gpio4 */ |
| 1099 | static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { |
| 1100 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ |
| 1101 | }; |
| 1102 | |
| 1103 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { |
| 1104 | &omap2420_l4_wkup__gpio4, |
| 1105 | }; |
| 1106 | |
| 1107 | static struct omap_hwmod omap2420_gpio4_hwmod = { |
| 1108 | .name = "gpio4", |
| 1109 | .mpu_irqs = omap242x_gpio4_irqs, |
| 1110 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), |
| 1111 | .main_clk = "gpios_fck", |
| 1112 | .prcm = { |
| 1113 | .omap2 = { |
| 1114 | .prcm_reg_id = 1, |
| 1115 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 1116 | .module_offs = WKUP_MOD, |
| 1117 | .idlest_reg_id = 1, |
| 1118 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 1119 | }, |
| 1120 | }, |
| 1121 | .slaves = omap2420_gpio4_slaves, |
| 1122 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), |
| 1123 | .class = &omap242x_gpio_hwmod_class, |
| 1124 | .dev_attr = &gpio_dev_attr, |
| 1125 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1126 | }; |
| 1127 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1128 | /* system dma */ |
| 1129 | static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { |
| 1130 | .rev_offs = 0x0000, |
| 1131 | .sysc_offs = 0x002c, |
| 1132 | .syss_offs = 0x0028, |
| 1133 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | |
| 1134 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | |
| 1135 | SYSC_HAS_AUTOIDLE), |
| 1136 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 1137 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1138 | }; |
| 1139 | |
| 1140 | static struct omap_hwmod_class omap2420_dma_hwmod_class = { |
| 1141 | .name = "dma", |
| 1142 | .sysc = &omap2420_dma_sysc, |
| 1143 | }; |
| 1144 | |
| 1145 | /* dma attributes */ |
| 1146 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 1147 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 1148 | IS_CSSA_32 | IS_CDSA_32, |
| 1149 | .lch_count = 32, |
| 1150 | }; |
| 1151 | |
| 1152 | static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { |
| 1153 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ |
| 1154 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ |
| 1155 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ |
| 1156 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ |
| 1157 | }; |
| 1158 | |
| 1159 | static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { |
| 1160 | { |
| 1161 | .pa_start = 0x48056000, |
| 1162 | .pa_end = 0x4a0560ff, |
| 1163 | .flags = ADDR_TYPE_RT |
| 1164 | }, |
| 1165 | }; |
| 1166 | |
| 1167 | /* dma_system -> L3 */ |
| 1168 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { |
| 1169 | .master = &omap2420_dma_system_hwmod, |
| 1170 | .slave = &omap2420_l3_main_hwmod, |
| 1171 | .clk = "core_l3_ck", |
| 1172 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1173 | }; |
| 1174 | |
| 1175 | /* dma_system master ports */ |
| 1176 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { |
| 1177 | &omap2420_dma_system__l3, |
| 1178 | }; |
| 1179 | |
| 1180 | /* l4_core -> dma_system */ |
| 1181 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { |
| 1182 | .master = &omap2420_l4_core_hwmod, |
| 1183 | .slave = &omap2420_dma_system_hwmod, |
| 1184 | .clk = "sdma_ick", |
| 1185 | .addr = omap2420_dma_system_addrs, |
| 1186 | .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs), |
| 1187 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1188 | }; |
| 1189 | |
| 1190 | /* dma_system slave ports */ |
| 1191 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { |
| 1192 | &omap2420_l4_core__dma_system, |
| 1193 | }; |
| 1194 | |
| 1195 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
| 1196 | .name = "dma", |
| 1197 | .class = &omap2420_dma_hwmod_class, |
| 1198 | .mpu_irqs = omap2420_dma_system_irqs, |
| 1199 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs), |
| 1200 | .main_clk = "core_l3_ck", |
| 1201 | .slaves = omap2420_dma_system_slaves, |
| 1202 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), |
| 1203 | .masters = omap2420_dma_system_masters, |
| 1204 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), |
| 1205 | .dev_attr = &dma_dev_attr, |
| 1206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1207 | .flags = HWMOD_NO_IDLEST, |
| 1208 | }; |
| 1209 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1210 | /* |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1211 | * 'mailbox' class |
| 1212 | * mailbox module allowing communication between the on-chip processors |
| 1213 | * using a queued mailbox-interrupt mechanism. |
| 1214 | */ |
| 1215 | |
| 1216 | static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = { |
| 1217 | .rev_offs = 0x000, |
| 1218 | .sysc_offs = 0x010, |
| 1219 | .syss_offs = 0x014, |
| 1220 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1221 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 1222 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1223 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1224 | }; |
| 1225 | |
| 1226 | static struct omap_hwmod_class omap2420_mailbox_hwmod_class = { |
| 1227 | .name = "mailbox", |
| 1228 | .sysc = &omap2420_mailbox_sysc, |
| 1229 | }; |
| 1230 | |
| 1231 | /* mailbox */ |
| 1232 | static struct omap_hwmod omap2420_mailbox_hwmod; |
| 1233 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { |
| 1234 | { .name = "dsp", .irq = 26 }, |
| 1235 | { .name = "iva", .irq = 34 }, |
| 1236 | }; |
| 1237 | |
| 1238 | static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = { |
| 1239 | { |
| 1240 | .pa_start = 0x48094000, |
| 1241 | .pa_end = 0x480941ff, |
| 1242 | .flags = ADDR_TYPE_RT, |
| 1243 | }, |
| 1244 | }; |
| 1245 | |
| 1246 | /* l4_core -> mailbox */ |
| 1247 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { |
| 1248 | .master = &omap2420_l4_core_hwmod, |
| 1249 | .slave = &omap2420_mailbox_hwmod, |
| 1250 | .addr = omap2420_mailbox_addrs, |
| 1251 | .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs), |
| 1252 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1253 | }; |
| 1254 | |
| 1255 | /* mailbox slave ports */ |
| 1256 | static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { |
| 1257 | &omap2420_l4_core__mailbox, |
| 1258 | }; |
| 1259 | |
| 1260 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
| 1261 | .name = "mailbox", |
| 1262 | .class = &omap2420_mailbox_hwmod_class, |
| 1263 | .mpu_irqs = omap2420_mailbox_irqs, |
| 1264 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs), |
| 1265 | .main_clk = "mailboxes_ick", |
| 1266 | .prcm = { |
| 1267 | .omap2 = { |
| 1268 | .prcm_reg_id = 1, |
| 1269 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 1270 | .module_offs = CORE_MOD, |
| 1271 | .idlest_reg_id = 1, |
| 1272 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, |
| 1273 | }, |
| 1274 | }, |
| 1275 | .slaves = omap2420_mailbox_slaves, |
| 1276 | .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), |
| 1277 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1278 | }; |
| 1279 | |
| 1280 | /* |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1281 | * 'mcspi' class |
| 1282 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 1283 | * bus |
| 1284 | */ |
| 1285 | |
| 1286 | static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { |
| 1287 | .rev_offs = 0x0000, |
| 1288 | .sysc_offs = 0x0010, |
| 1289 | .syss_offs = 0x0014, |
| 1290 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1291 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 1292 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 1293 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1294 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1295 | }; |
| 1296 | |
| 1297 | static struct omap_hwmod_class omap2420_mcspi_class = { |
| 1298 | .name = "mcspi", |
| 1299 | .sysc = &omap2420_mcspi_sysc, |
| 1300 | .rev = OMAP2_MCSPI_REV, |
| 1301 | }; |
| 1302 | |
| 1303 | /* mcspi1 */ |
| 1304 | static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { |
| 1305 | { .irq = 65 }, |
| 1306 | }; |
| 1307 | |
| 1308 | static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { |
| 1309 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ |
| 1310 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ |
| 1311 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ |
| 1312 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ |
| 1313 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ |
| 1314 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ |
| 1315 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ |
| 1316 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ |
| 1317 | }; |
| 1318 | |
| 1319 | static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { |
| 1320 | &omap2420_l4_core__mcspi1, |
| 1321 | }; |
| 1322 | |
| 1323 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
| 1324 | .num_chipselect = 4, |
| 1325 | }; |
| 1326 | |
| 1327 | static struct omap_hwmod omap2420_mcspi1_hwmod = { |
| 1328 | .name = "mcspi1_hwmod", |
| 1329 | .mpu_irqs = omap2420_mcspi1_mpu_irqs, |
| 1330 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), |
| 1331 | .sdma_reqs = omap2420_mcspi1_sdma_reqs, |
| 1332 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), |
| 1333 | .main_clk = "mcspi1_fck", |
| 1334 | .prcm = { |
| 1335 | .omap2 = { |
| 1336 | .module_offs = CORE_MOD, |
| 1337 | .prcm_reg_id = 1, |
| 1338 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1339 | .idlest_reg_id = 1, |
| 1340 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, |
| 1341 | }, |
| 1342 | }, |
| 1343 | .slaves = omap2420_mcspi1_slaves, |
| 1344 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), |
| 1345 | .class = &omap2420_mcspi_class, |
| 1346 | .dev_attr = &omap_mcspi1_dev_attr, |
| 1347 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1348 | }; |
| 1349 | |
| 1350 | /* mcspi2 */ |
| 1351 | static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { |
| 1352 | { .irq = 66 }, |
| 1353 | }; |
| 1354 | |
| 1355 | static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { |
| 1356 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ |
| 1357 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ |
| 1358 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ |
| 1359 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ |
| 1360 | }; |
| 1361 | |
| 1362 | static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { |
| 1363 | &omap2420_l4_core__mcspi2, |
| 1364 | }; |
| 1365 | |
| 1366 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
| 1367 | .num_chipselect = 2, |
| 1368 | }; |
| 1369 | |
| 1370 | static struct omap_hwmod omap2420_mcspi2_hwmod = { |
| 1371 | .name = "mcspi2_hwmod", |
| 1372 | .mpu_irqs = omap2420_mcspi2_mpu_irqs, |
| 1373 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), |
| 1374 | .sdma_reqs = omap2420_mcspi2_sdma_reqs, |
| 1375 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), |
| 1376 | .main_clk = "mcspi2_fck", |
| 1377 | .prcm = { |
| 1378 | .omap2 = { |
| 1379 | .module_offs = CORE_MOD, |
| 1380 | .prcm_reg_id = 1, |
| 1381 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 1382 | .idlest_reg_id = 1, |
| 1383 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, |
| 1384 | }, |
| 1385 | }, |
| 1386 | .slaves = omap2420_mcspi2_slaves, |
| 1387 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), |
| 1388 | .class = &omap2420_mcspi_class, |
| 1389 | .dev_attr = &omap_mcspi2_dev_attr, |
| 1390 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 1391 | }; |
| 1392 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1393 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 1394 | &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1395 | &omap2420_l4_core_hwmod, |
| 1396 | &omap2420_l4_wkup_hwmod, |
| 1397 | &omap2420_mpu_hwmod, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 1398 | &omap2420_iva_hwmod, |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 1399 | &omap2420_wd_timer2_hwmod, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 1400 | &omap2420_uart1_hwmod, |
| 1401 | &omap2420_uart2_hwmod, |
| 1402 | &omap2420_uart3_hwmod, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 1403 | /* dss class */ |
| 1404 | &omap2420_dss_core_hwmod, |
| 1405 | &omap2420_dss_dispc_hwmod, |
| 1406 | &omap2420_dss_rfbi_hwmod, |
| 1407 | &omap2420_dss_venc_hwmod, |
| 1408 | /* i2c class */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 1409 | &omap2420_i2c1_hwmod, |
| 1410 | &omap2420_i2c2_hwmod, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 1411 | |
| 1412 | /* gpio class */ |
| 1413 | &omap2420_gpio1_hwmod, |
| 1414 | &omap2420_gpio2_hwmod, |
| 1415 | &omap2420_gpio3_hwmod, |
| 1416 | &omap2420_gpio4_hwmod, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 1417 | |
| 1418 | /* dma_system class*/ |
| 1419 | &omap2420_dma_system_hwmod, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1420 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 1421 | /* mailbox class */ |
| 1422 | &omap2420_mailbox_hwmod, |
| 1423 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 1424 | /* mcspi class */ |
| 1425 | &omap2420_mcspi1_hwmod, |
| 1426 | &omap2420_mcspi2_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1427 | NULL, |
| 1428 | }; |
| 1429 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1430 | int __init omap2420_hwmod_init(void) |
| 1431 | { |
| 1432 | return omap_hwmod_init(omap2420_hwmods); |
| 1433 | } |