Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/copypage-v4wb.c |
| 3 | * |
| 4 | * Copyright (C) 1995-1999 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #include <linux/init.h> |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 11 | #include <linux/highmem.h> |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 12 | |
| 13 | /* |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 14 | * ARMv4 optimised copy_user_highpage |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 15 | * |
| 16 | * We flush the destination cache lines just before we write the data into the |
| 17 | * corresponding address. Since the Dcache is read-allocate, this removes the |
| 18 | * Dcache aliasing issue. The writes will be forwarded to the write buffer, |
| 19 | * and merged as appropriate. |
| 20 | * |
| 21 | * Note: We rely on all ARMv4 processors implementing the "invalidate D line" |
| 22 | * instruction. If your processor does not supply this, you have to write your |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 23 | * own copy_user_highpage that does the right thing. |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 24 | */ |
Uwe Kleine-König | 446c92b | 2009-03-12 18:03:16 +0100 | [diff] [blame] | 25 | static void __naked |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 26 | v4wb_copy_user_page(void *kto, const void *kfrom) |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 27 | { |
| 28 | asm("\ |
| 29 | stmfd sp!, {r4, lr} @ 2\n\ |
Khem Raj | 9a40ac86 | 2010-06-04 04:05:15 +0100 | [diff] [blame] | 30 | mov r2, %2 @ 1\n\ |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 31 | ldmia r1!, {r3, r4, ip, lr} @ 4\n\ |
| 32 | 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ |
| 33 | stmia r0!, {r3, r4, ip, lr} @ 4\n\ |
| 34 | ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ |
| 35 | stmia r0!, {r3, r4, ip, lr} @ 4\n\ |
| 36 | ldmia r1!, {r3, r4, ip, lr} @ 4\n\ |
| 37 | mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ |
| 38 | stmia r0!, {r3, r4, ip, lr} @ 4\n\ |
| 39 | ldmia r1!, {r3, r4, ip, lr} @ 4\n\ |
| 40 | subs r2, r2, #1 @ 1\n\ |
| 41 | stmia r0!, {r3, r4, ip, lr} @ 4\n\ |
| 42 | ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ |
| 43 | bne 1b @ 1\n\ |
| 44 | mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\ |
| 45 | ldmfd sp!, {r4, pc} @ 3" |
| 46 | : |
Khem Raj | 9a40ac86 | 2010-06-04 04:05:15 +0100 | [diff] [blame] | 47 | : "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64)); |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 48 | } |
| 49 | |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 50 | void v4wb_copy_user_highpage(struct page *to, struct page *from, |
Russell King | f00a75c | 2009-10-05 15:17:45 +0100 | [diff] [blame] | 51 | unsigned long vaddr, struct vm_area_struct *vma) |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 52 | { |
| 53 | void *kto, *kfrom; |
| 54 | |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 55 | kto = kmap_atomic(to); |
| 56 | kfrom = kmap_atomic(from); |
Russell King | 2725898 | 2009-10-05 15:34:22 +0100 | [diff] [blame] | 57 | flush_cache_page(vma, vaddr, page_to_pfn(from)); |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 58 | v4wb_copy_user_page(kto, kfrom); |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 59 | kunmap_atomic(kfrom); |
| 60 | kunmap_atomic(kto); |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 61 | } |
| 62 | |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 63 | /* |
| 64 | * ARMv4 optimised clear_user_page |
| 65 | * |
| 66 | * Same story as above. |
| 67 | */ |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 68 | void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr) |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 69 | { |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 70 | void *ptr, *kaddr = kmap_atomic(page); |
Nicolas Pitre | 43ae286 | 2008-11-04 02:42:27 -0500 | [diff] [blame] | 71 | asm volatile("\ |
| 72 | mov r1, %2 @ 1\n\ |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 73 | mov r2, #0 @ 1\n\ |
| 74 | mov r3, #0 @ 1\n\ |
| 75 | mov ip, #0 @ 1\n\ |
| 76 | mov lr, #0 @ 1\n\ |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 77 | 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ |
| 78 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
| 79 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
| 80 | mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ |
| 81 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
| 82 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 83 | subs r1, r1, #1 @ 1\n\ |
| 84 | bne 1b @ 1\n\ |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 85 | mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" |
Nicolas Pitre | 43ae286 | 2008-11-04 02:42:27 -0500 | [diff] [blame] | 86 | : "=r" (ptr) |
| 87 | : "0" (kaddr), "I" (PAGE_SIZE / 64) |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 88 | : "r1", "r2", "r3", "ip", "lr"); |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 89 | kunmap_atomic(kaddr); |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | struct cpu_user_fns v4wb_user_fns __initdata = { |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 93 | .cpu_clear_user_highpage = v4wb_clear_user_highpage, |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 94 | .cpu_copy_user_highpage = v4wb_copy_user_highpage, |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 95 | }; |