blob: 28a988889319bbc335691ab3945e72ec93ac5404 [file] [log] [blame]
dmitry pervushine3178722009-04-22 23:55:23 +01001/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARCH_SYSTEM_H
17#define __ASM_ARCH_SYSTEM_H
18
19#include <asm/proc-fns.h>
dmitry pervushin98f420b2009-05-31 13:32:11 +010020#include <mach/platform.h>
dmitry pervushine3178722009-04-22 23:55:23 +010021#include <mach/regs-clkctrl.h>
22#include <mach/regs-power.h>
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30
31 cpu_do_idle();
32}
33
34static inline void arch_reset(char mode, const char *cmd)
35{
36 /* Set BATTCHRG to default value */
dmitry pervushin98f420b2009-05-31 13:32:11 +010037 __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
dmitry pervushine3178722009-04-22 23:55:23 +010038
39 /* Set MINPWR to default value */
dmitry pervushin98f420b2009-05-31 13:32:11 +010040 __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
dmitry pervushine3178722009-04-22 23:55:23 +010041
42 /* Reset digital side of chip (but not power or RTC) */
dmitry pervushin98f420b2009-05-31 13:32:11 +010043 __raw_writel(BM_CLKCTRL_RESET_DIG,
44 REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
dmitry pervushine3178722009-04-22 23:55:23 +010045
46 /* Should not return */
47}
48
49#endif