Isaku Yamahata | ed50bd6 | 2008-10-17 11:17:52 +0900 | [diff] [blame] | 1 | #ifndef _ASM_IA64_XEN_PRIVOP_H |
| 2 | #define _ASM_IA64_XEN_PRIVOP_H |
| 3 | |
| 4 | /* |
| 5 | * Copyright (C) 2005 Hewlett-Packard Co |
| 6 | * Dan Magenheimer <dan.magenheimer@hp.com> |
| 7 | * |
| 8 | * Paravirtualizations of privileged operations for Xen/ia64 |
| 9 | * |
| 10 | * |
| 11 | * inline privop and paravirt_alt support |
| 12 | * Copyright (c) 2007 Isaku Yamahata <yamahata at valinux co jp> |
| 13 | * VA Linux Systems Japan K.K. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #ifndef __ASSEMBLY__ |
| 18 | #include <linux/types.h> /* arch-ia64.h requires uint64_t */ |
| 19 | #endif |
| 20 | #include <asm/xen/interface.h> |
| 21 | |
| 22 | /* At 1 MB, before per-cpu space but still addressable using addl instead |
| 23 | of movl. */ |
| 24 | #define XSI_BASE 0xfffffffffff00000 |
| 25 | |
| 26 | /* Address of mapped regs. */ |
| 27 | #define XMAPPEDREGS_BASE (XSI_BASE + XSI_SIZE) |
| 28 | |
| 29 | #ifdef __ASSEMBLY__ |
| 30 | #define XEN_HYPER_RFI break HYPERPRIVOP_RFI |
| 31 | #define XEN_HYPER_RSM_PSR_DT break HYPERPRIVOP_RSM_DT |
| 32 | #define XEN_HYPER_SSM_PSR_DT break HYPERPRIVOP_SSM_DT |
| 33 | #define XEN_HYPER_COVER break HYPERPRIVOP_COVER |
| 34 | #define XEN_HYPER_ITC_D break HYPERPRIVOP_ITC_D |
| 35 | #define XEN_HYPER_ITC_I break HYPERPRIVOP_ITC_I |
| 36 | #define XEN_HYPER_SSM_I break HYPERPRIVOP_SSM_I |
| 37 | #define XEN_HYPER_GET_IVR break HYPERPRIVOP_GET_IVR |
| 38 | #define XEN_HYPER_THASH break HYPERPRIVOP_THASH |
| 39 | #define XEN_HYPER_ITR_D break HYPERPRIVOP_ITR_D |
| 40 | #define XEN_HYPER_SET_KR break HYPERPRIVOP_SET_KR |
| 41 | #define XEN_HYPER_GET_PSR break HYPERPRIVOP_GET_PSR |
| 42 | #define XEN_HYPER_SET_RR0_TO_RR4 break HYPERPRIVOP_SET_RR0_TO_RR4 |
| 43 | |
| 44 | #define XSI_IFS (XSI_BASE + XSI_IFS_OFS) |
| 45 | #define XSI_PRECOVER_IFS (XSI_BASE + XSI_PRECOVER_IFS_OFS) |
| 46 | #define XSI_IFA (XSI_BASE + XSI_IFA_OFS) |
| 47 | #define XSI_ISR (XSI_BASE + XSI_ISR_OFS) |
| 48 | #define XSI_IIM (XSI_BASE + XSI_IIM_OFS) |
| 49 | #define XSI_ITIR (XSI_BASE + XSI_ITIR_OFS) |
| 50 | #define XSI_PSR_I_ADDR (XSI_BASE + XSI_PSR_I_ADDR_OFS) |
| 51 | #define XSI_PSR_IC (XSI_BASE + XSI_PSR_IC_OFS) |
| 52 | #define XSI_IPSR (XSI_BASE + XSI_IPSR_OFS) |
| 53 | #define XSI_IIP (XSI_BASE + XSI_IIP_OFS) |
| 54 | #define XSI_B1NAT (XSI_BASE + XSI_B1NATS_OFS) |
| 55 | #define XSI_BANK1_R16 (XSI_BASE + XSI_BANK1_R16_OFS) |
| 56 | #define XSI_BANKNUM (XSI_BASE + XSI_BANKNUM_OFS) |
| 57 | #define XSI_IHA (XSI_BASE + XSI_IHA_OFS) |
Isaku Yamahata | 496203b | 2009-03-04 21:05:39 +0900 | [diff] [blame] | 58 | #define XSI_ITC_OFFSET (XSI_BASE + XSI_ITC_OFFSET_OFS) |
| 59 | #define XSI_ITC_LAST (XSI_BASE + XSI_ITC_LAST_OFS) |
Isaku Yamahata | ed50bd6 | 2008-10-17 11:17:52 +0900 | [diff] [blame] | 60 | #endif |
| 61 | |
| 62 | #ifndef __ASSEMBLY__ |
| 63 | |
| 64 | /************************************************/ |
| 65 | /* Instructions paravirtualized for correctness */ |
| 66 | /************************************************/ |
| 67 | |
| 68 | /* "fc" and "thash" are privilege-sensitive instructions, meaning they |
| 69 | * may have different semantics depending on whether they are executed |
| 70 | * at PL0 vs PL!=0. When paravirtualized, these instructions mustn't |
| 71 | * be allowed to execute directly, lest incorrect semantics result. */ |
Isaku Yamahata | 7120569 | 2009-03-27 15:11:57 +0900 | [diff] [blame] | 72 | extern void xen_fc(void *addr); |
Isaku Yamahata | ed50bd6 | 2008-10-17 11:17:52 +0900 | [diff] [blame] | 73 | extern unsigned long xen_thash(unsigned long addr); |
| 74 | |
| 75 | /* Note that "ttag" and "cover" are also privilege-sensitive; "ttag" |
| 76 | * is not currently used (though it may be in a long-format VHPT system!) |
| 77 | * and the semantics of cover only change if psr.ic is off which is very |
| 78 | * rare (and currently non-existent outside of assembly code */ |
| 79 | |
| 80 | /* There are also privilege-sensitive registers. These registers are |
| 81 | * readable at any privilege level but only writable at PL0. */ |
| 82 | extern unsigned long xen_get_cpuid(int index); |
| 83 | extern unsigned long xen_get_pmd(int index); |
| 84 | |
Isaku Yamahata | 0a7d324 | 2009-03-04 21:06:55 +0900 | [diff] [blame] | 85 | #ifndef ASM_SUPPORTED |
Isaku Yamahata | ed50bd6 | 2008-10-17 11:17:52 +0900 | [diff] [blame] | 86 | extern unsigned long xen_get_eflag(void); /* see xen_ia64_getreg */ |
| 87 | extern void xen_set_eflag(unsigned long); /* see xen_ia64_setreg */ |
Isaku Yamahata | 0a7d324 | 2009-03-04 21:06:55 +0900 | [diff] [blame] | 88 | #endif |
Isaku Yamahata | ed50bd6 | 2008-10-17 11:17:52 +0900 | [diff] [blame] | 89 | |
| 90 | /************************************************/ |
| 91 | /* Instructions paravirtualized for performance */ |
| 92 | /************************************************/ |
| 93 | |
| 94 | /* Xen uses memory-mapped virtual privileged registers for access to many |
| 95 | * performance-sensitive privileged registers. Some, like the processor |
| 96 | * status register (psr), are broken up into multiple memory locations. |
| 97 | * Others, like "pend", are abstractions based on privileged registers. |
| 98 | * "Pend" is guaranteed to be set if reading cr.ivr would return a |
| 99 | * (non-spurious) interrupt. */ |
| 100 | #define XEN_MAPPEDREGS ((struct mapped_regs *)XMAPPEDREGS_BASE) |
| 101 | |
| 102 | #define XSI_PSR_I \ |
| 103 | (*XEN_MAPPEDREGS->interrupt_mask_addr) |
| 104 | #define xen_get_virtual_psr_i() \ |
| 105 | (!XSI_PSR_I) |
| 106 | #define xen_set_virtual_psr_i(_val) \ |
| 107 | ({ XSI_PSR_I = (uint8_t)(_val) ? 0 : 1; }) |
| 108 | #define xen_set_virtual_psr_ic(_val) \ |
| 109 | ({ XEN_MAPPEDREGS->interrupt_collection_enabled = _val ? 1 : 0; }) |
| 110 | #define xen_get_virtual_pend() \ |
| 111 | (*(((uint8_t *)XEN_MAPPEDREGS->interrupt_mask_addr) - 1)) |
| 112 | |
Isaku Yamahata | 0a7d324 | 2009-03-04 21:06:55 +0900 | [diff] [blame] | 113 | #ifndef ASM_SUPPORTED |
Isaku Yamahata | ed50bd6 | 2008-10-17 11:17:52 +0900 | [diff] [blame] | 114 | /* Although all privileged operations can be left to trap and will |
| 115 | * be properly handled by Xen, some are frequent enough that we use |
| 116 | * hyperprivops for performance. */ |
| 117 | extern unsigned long xen_get_psr(void); |
| 118 | extern unsigned long xen_get_ivr(void); |
| 119 | extern unsigned long xen_get_tpr(void); |
| 120 | extern void xen_hyper_ssm_i(void); |
| 121 | extern void xen_set_itm(unsigned long); |
| 122 | extern void xen_set_tpr(unsigned long); |
| 123 | extern void xen_eoi(unsigned long); |
| 124 | extern unsigned long xen_get_rr(unsigned long index); |
| 125 | extern void xen_set_rr(unsigned long index, unsigned long val); |
| 126 | extern void xen_set_rr0_to_rr4(unsigned long val0, unsigned long val1, |
| 127 | unsigned long val2, unsigned long val3, |
| 128 | unsigned long val4); |
| 129 | extern void xen_set_kr(unsigned long index, unsigned long val); |
| 130 | extern void xen_ptcga(unsigned long addr, unsigned long size); |
Isaku Yamahata | 0a7d324 | 2009-03-04 21:06:55 +0900 | [diff] [blame] | 131 | #endif /* !ASM_SUPPORTED */ |
Isaku Yamahata | ed50bd6 | 2008-10-17 11:17:52 +0900 | [diff] [blame] | 132 | |
| 133 | #endif /* !__ASSEMBLY__ */ |
| 134 | |
| 135 | #endif /* _ASM_IA64_XEN_PRIVOP_H */ |