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gerrit-public.fairphone.software / kernel / msm-4.9 / 3d3b5518a35fa3c31b74224d944cbc83302c5ab4 / . / drivers / staging / rtl8192su / r8192S_firmware.h
blob: c525380e6473397027c83d8d397571614280de5f [file] [log] [blame]
Jerry Chuang5f53d8c2009-05-21 22:16:02 -0700[diff] [blame]1#ifndef __INC_FIRMWARE_H
2#define __INC_FIRMWARE_H
3
4
5//#define RTL8190_CPU_START_OFFSET 0x80
6/* TODO: this definition is TBD */
7//#define USB_HWDESC_HEADER_LEN 0
8
9/* It should be double word alignment */
10//#if DEV_BUS_TYPE==PCI_INTERFACE
11//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
12//#else
13//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
14//#endif
15
16//typedef enum _firmware_init_step{
17// FW_INIT_STEP0_BOOT = 0,
18// FW_INIT_STEP1_MAIN = 1,
19// FW_INIT_STEP2_DATA = 2,
20//}firmware_init_step_e;
21
22//typedef enum _DESC_PACKET_TYPE{
23// DESC_PACKET_TYPE_INIT = 0,
24// DESC_PACKET_TYPE_NORMAL = 1,
25//}DESC_PACKET_TYPE;
26#define RTL8192S_FW_PKT_FRAG_SIZE 0xFF00 // 64K
27
28
29#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
30#define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size.
31#define RTL8190_CPU_START_OFFSET 0x80
32
Jerry Chuang5f53d8c2009-05-21 22:16:02 -0700[diff] [blame]33#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
Jerry Chuang5f53d8c2009-05-21 22:16:02 -0700[diff] [blame]34
35//typedef enum _DESC_PACKET_TYPE{
36// DESC_PACKET_TYPE_INIT = 0,
37// DESC_PACKET_TYPE_NORMAL = 1,
38//}DESC_PACKET_TYPE;
39
40// Forward declaration.
41//typedef struct _ADAPTER ADAPTER, *PADAPTER;
42#ifdef RTL8192S
43typedef enum _firmware_init_step{
44 FW_INIT_STEP0_IMEM = 0,
45 FW_INIT_STEP1_MAIN = 1,
46 FW_INIT_STEP2_DATA = 2,
47}firmware_init_step_e;
48#else
49typedef enum _firmware_init_step{
50 FW_INIT_STEP0_BOOT = 0,
51 FW_INIT_STEP1_MAIN = 1,
52 FW_INIT_STEP2_DATA = 2,
53}firmware_init_step_e;
54#endif
55
56/* due to rtl8192 firmware */
57typedef enum _desc_packet_type_e{
58 DESC_PACKET_TYPE_INIT = 0,
59 DESC_PACKET_TYPE_NORMAL = 1,
60}desc_packet_type_e;
61
62typedef enum _firmware_source{
63 FW_SOURCE_IMG_FILE = 0,
64 FW_SOURCE_HEADER_FILE = 1,
65}firmware_source_e, *pfirmware_source_e;
66
67
68typedef enum _opt_rst_type{
69 OPT_SYSTEM_RESET = 0,
70 OPT_FIRMWARE_RESET = 1,
71}opt_rst_type_e;
72
73/*typedef enum _FIRMWARE_STATUS{
74 FW_STATUS_0_INIT = 0,
75 FW_STATUS_1_MOVE_BOOT_CODE = 1,
76 FW_STATUS_2_MOVE_MAIN_CODE = 2,
77 FW_STATUS_3_TURNON_CPU = 3,
78 FW_STATUS_4_MOVE_DATA_CODE = 4,
79 FW_STATUS_5_READY = 5,
80}FIRMWARE_STATUS;
81*/
82//--------------------------------------------------------------------------------
83// RTL8192S Firmware related, Revised by Roger, 2008.12.18.
84//--------------------------------------------------------------------------------
85typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required
86
87 //--- long word 0 ----
88 u8 signature_0; //0x12: CE product, 0x92: IT product
89 u8 signature_1; //0x87: CE product, 0x81: IT product
90 u8 hci_sel; //0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP, 0x12: 72S-U, 03:SDIO
91 u8 chip_version; //the same value as reigster value
92 u8 customer_ID_0; //customer ID low byte
93 u8 customer_ID_1; //customer ID high byte
94 u8 rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
95 u8 usb_ep_num; // 4: 4EP, 6: 6EP, 11: 11EP
96
97 //--- long word 1 ----
98 u8 regulatory_class_0; //regulatory class bit map 0
99 u8 regulatory_class_1; //regulatory class bit map 1
100 u8 regulatory_class_2; //regulatory class bit map 2
101 u8 regulatory_class_3; //regulatory class bit map 3
102 u8 rfintfs; // 0:SWSI, 1:HWSI, 2:HWPI
103 u8 def_nettype;
104 u8 rsvd010;
105 u8 rsvd011;
106
107
108 //--- long word 2 ----
109 u8 lbk_mode; //0x00: normal, 0x03: MACLBK, 0x01: PHYLBK
110 u8 mp_mode; // 1: for MP use, 0: for normal driver (to be discussed)
111 u8 rsvd020;
112 u8 rsvd021;
113 u8 rsvd022;
114 u8 rsvd023;
115 u8 rsvd024;
116 u8 rsvd025;
117
118 //--- long word 3 ----
119 u8 qos_en; // QoS enable
120 u8 bw_40MHz_en; // 40MHz BW enable
121 u8 AMSDU2AMPDU_en; // 4181 convert AMSDU to AMPDU, 0: disable
122 u8 AMPDU_en; // 11n AMPDU enable
123 u8 rate_control_offload;//FW offloads, 0: driver handles
124 u8 aggregation_offload; // FW offloads, 0: driver handles
125 u8 rsvd030;
126 u8 rsvd031;
127
128
129 //--- long word 4 ----
130 unsigned char beacon_offload; // 1. FW offloads, 0: driver handles
131 unsigned char MLME_offload; // 2. FW offloads, 0: driver handles
132 unsigned char hwpc_offload; // 3. FW offloads, 0: driver handles
133 unsigned char tcp_checksum_offload; // 4. FW offloads, 0: driver handles
134 unsigned char tcp_offload; // 5. FW offloads, 0: driver handles
135 unsigned char ps_control_offload; // 6. FW offloads, 0: driver handles
136 unsigned char WWLAN_offload; // 7. FW offloads, 0: driver handles
137 unsigned char rsvd040;
138
139 //--- long word 5 ----
140 u8 tcp_tx_frame_len_L; //tcp tx packet length low byte
141 u8 tcp_tx_frame_len_H; //tcp tx packet length high byte
142 u8 tcp_rx_frame_len_L; //tcp rx packet length low byte
143 u8 tcp_rx_frame_len_H; //tcp rx packet length high byte
144 u8 rsvd050;
145 u8 rsvd051;
146 u8 rsvd052;
147 u8 rsvd053;
148}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV;
149
150typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required
151
152 //--- LONG WORD 0 ----
153 u16 Signature;
154 u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version,
155 u32 DMEMSize; //define the size of boot loader
156
157
158 //--- LONG WORD 1 ----
159 u32 IMG_IMEM_SIZE; //define the size of FW in IMEM
160 u32 IMG_SRAM_SIZE; //define the size of FW in SRAM
161
162 //--- LONG WORD 2 ----
163 u32 FW_PRIV_SIZE; //define the size of DMEM variable
164 u32 Rsvd0;
165
166 //--- LONG WORD 3 ----
167 u32 Rsvd1;
168 u32 Rsvd2;
169
170 RT_8192S_FIRMWARE_PRIV FWPriv;
171
172}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR;
173
174#define RT_8192S_FIRMWARE_HDR_SIZE 80
175#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
176
177typedef enum _FIRMWARE_8192S_STATUS{
178 FW_STATUS_INIT = 0,
179 FW_STATUS_LOAD_IMEM = 1,
180 FW_STATUS_LOAD_EMEM = 2,
181 FW_STATUS_LOAD_DMEM = 3,
182 FW_STATUS_READY = 4,
183}FIRMWARE_8192S_STATUS;
184
185#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
186
187typedef struct _rt_firmware{
188 firmware_source_e eFWSource;
189 PRT_8192S_FIRMWARE_HDR pFwHeader;
190 FIRMWARE_8192S_STATUS FWStatus;
191 u16 FirmwareVersion;
192 u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
193 u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE];
194 u32 FwIMEMLen;
195 u32 FwEMEMLen;
196 u8 szFwTmpBuffer[164000];
197 u32 szFwTmpBufferLen;
198 u16 CmdPacketFragThresold;
199}rt_firmware, *prt_firmware;
200
201//typedef struct _RT_FIRMWARE_INFO_8192SU{
202// u8 szInfo[16];
203//}RT_FIRMWARE_INFO_8192SU, *PRT_FIRMWARE_INFO_8192SU;
204bool FirmwareDownload92S(struct net_device *dev);
205
206#endif
207