Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | |
| 3 | (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. |
| 4 | |
| 5 | Module: hal8192sphy.c |
| 6 | |
| 7 | Note: Merge 92SE/SU PHY config as below |
| 8 | 1. BB register R/W API |
| 9 | 2. RF register R/W API |
| 10 | 3. Initial BB/RF/MAC config by reading BB/MAC/RF txt. |
| 11 | 3. Power setting API |
| 12 | 4. Channel switch API |
| 13 | 5. Initial gain switch API. |
| 14 | 6. Other BB/MAC/RF API. |
| 15 | |
| 16 | Function: PHY: Extern function, phy: local function |
| 17 | |
| 18 | Export: PHY_FunctionName |
| 19 | |
| 20 | Abbrev: NONE |
| 21 | |
| 22 | History: |
| 23 | Data Who Remark |
| 24 | 08/08/2008 MHC 1. Port from 9x series phycfg.c |
| 25 | 2. Reorganize code arch and ad description. |
| 26 | 3. Collect similar function. |
| 27 | 4. Seperate extern/local API. |
| 28 | 08/12/2008 MHC We must merge or move USB PHY relative function later. |
| 29 | 10/07/2008 MHC Add IQ calibration for PHY.(Only 1T2R mode now!!!) |
| 30 | 11/06/2008 MHC Add TX Power index PG file to config in 0xExx register |
| 31 | area to map with EEPROM/EFUSE tx pwr index. |
| 32 | |
| 33 | ******************************************************************************/ |
| 34 | #include "r8192U.h" |
| 35 | #include "r8192U_dm.h" |
| 36 | #include "r8192S_rtl6052.h" |
| 37 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 38 | #include "r8192S_hw.h" |
| 39 | #include "r8192S_phy.h" |
| 40 | #include "r8192S_phyreg.h" |
| 41 | #include "r8192SU_HWImg.h" |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 42 | |
Bartlomiej Zolnierkiewicz | 2a7d71a | 2009-06-12 18:29:19 +0200 | [diff] [blame] | 43 | #include "ieee80211/dot11d.h" |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 44 | |
| 45 | /*---------------------------Define Local Constant---------------------------*/ |
| 46 | /* Channel switch:The size of command tables for switch channel*/ |
| 47 | #define MAX_PRECMD_CNT 16 |
| 48 | #define MAX_RFDEPENDCMD_CNT 16 |
| 49 | #define MAX_POSTCMD_CNT 16 |
| 50 | #define MAX_DOZE_WAITING_TIMES_9x 64 |
| 51 | |
| 52 | /*------------------------Define local variable------------------------------*/ |
| 53 | // 2004-05-11 |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 54 | |
| 55 | static u32 |
| 56 | phy_CalculateBitShift(u32 BitMask); |
| 57 | static RT_STATUS |
| 58 | phy_ConfigMACWithHeaderFile(struct net_device* dev); |
| 59 | static void |
| 60 | phy_InitBBRFRegisterDefinition(struct net_device* dev); |
| 61 | static RT_STATUS |
| 62 | phy_BB8192S_Config_ParaFile(struct net_device* dev); |
| 63 | static RT_STATUS |
| 64 | phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType); |
| 65 | static bool |
| 66 | phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState); |
| 67 | void |
| 68 | SetBWModeCallback8192SUsbWorkItem(struct net_device *dev); |
| 69 | void |
| 70 | SetBWModeCallback8192SUsbWorkItem(struct net_device *dev); |
| 71 | void |
| 72 | SwChnlCallback8192SUsbWorkItem(struct net_device *dev ); |
| 73 | static void |
| 74 | phy_FinishSwChnlNow(struct net_device* dev,u8 channel); |
| 75 | static bool |
| 76 | phy_SwChnlStepByStep( |
| 77 | struct net_device* dev, |
| 78 | u8 channel, |
| 79 | u8 *stage, |
| 80 | u8 *step, |
| 81 | u32 *delay |
| 82 | ); |
| 83 | static RT_STATUS |
| 84 | phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 85 | static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx); |
| 86 | static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm); |
| 87 | void phy_SetFwCmdIOCallback(struct net_device* dev); |
| 88 | |
| 89 | //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE)) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 90 | // |
| 91 | // Description: |
| 92 | // Base Band read by 4181 to make sure that operation could be done in unlimited cycle. |
| 93 | // |
| 94 | // Assumption: |
| 95 | // - Only use on RTL8192S USB interface. |
| 96 | // - PASSIVE LEVEL |
| 97 | // |
| 98 | // Created by Roger, 2008.09.06. |
| 99 | // |
| 100 | //use in phy only |
| 101 | u32 phy_QueryUsbBBReg(struct net_device* dev, u32 RegAddr) |
| 102 | { |
| 103 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 104 | u32 ReturnValue = 0xffffffff; |
| 105 | u8 PollingCnt = 50; |
| 106 | u8 BBWaitCounter = 0; |
| 107 | |
| 108 | |
| 109 | // |
| 110 | // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. |
| 111 | // We have to make sure that previous BB I/O has been done. |
| 112 | // 2008.08.20. |
| 113 | // |
| 114 | while(priv->bChangeBBInProgress) |
| 115 | { |
| 116 | BBWaitCounter ++; |
| 117 | RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter); |
| 118 | msleep(1); // 1 ms |
| 119 | |
| 120 | // Wait too long, return FALSE to avoid to be stuck here. |
| 121 | if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter)) |
| 122 | { |
| 123 | RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter); |
| 124 | return ReturnValue; |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | priv->bChangeBBInProgress = true; |
| 129 | |
| 130 | read_nic_dword(dev, RegAddr); |
| 131 | |
| 132 | do |
| 133 | {// Make sure that access could be done. |
| 134 | if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0) |
| 135 | break; |
| 136 | }while( --PollingCnt ); |
| 137 | |
| 138 | if(PollingCnt == 0) |
| 139 | { |
| 140 | RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue); |
| 141 | } |
| 142 | else |
| 143 | { |
| 144 | // Data FW read back. |
| 145 | ReturnValue = read_nic_dword(dev, PHY_REG_DATA); |
| 146 | RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt); |
| 147 | } |
| 148 | |
| 149 | priv->bChangeBBInProgress = false; |
| 150 | |
| 151 | return ReturnValue; |
| 152 | } |
| 153 | |
| 154 | |
| 155 | |
| 156 | // |
| 157 | // Description: |
| 158 | // Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle. |
| 159 | // |
| 160 | // Assumption: |
| 161 | // - Only use on RTL8192S USB interface. |
| 162 | // - PASSIVE LEVEL |
| 163 | // |
| 164 | // Created by Roger, 2008.09.06. |
| 165 | // |
| 166 | //use in phy only |
| 167 | void |
| 168 | phy_SetUsbBBReg(struct net_device* dev,u32 RegAddr,u32 Data) |
| 169 | { |
| 170 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 171 | u8 BBWaitCounter = 0; |
| 172 | |
| 173 | RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data); |
| 174 | |
| 175 | // |
| 176 | // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. |
| 177 | // We have to make sure that previous BB I/O has been done. |
| 178 | // 2008.08.20. |
| 179 | // |
| 180 | while(priv->bChangeBBInProgress) |
| 181 | { |
| 182 | BBWaitCounter ++; |
| 183 | RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter); |
| 184 | msleep(1); // 1 ms |
| 185 | |
| 186 | if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter)) |
| 187 | { |
| 188 | RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter); |
| 189 | return; |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | priv->bChangeBBInProgress = true; |
| 194 | //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data); |
| 195 | write_nic_dword(dev, RegAddr, Data); |
| 196 | |
| 197 | priv->bChangeBBInProgress = false; |
| 198 | } |
| 199 | |
| 200 | |
| 201 | |
| 202 | // |
| 203 | // Description: |
| 204 | // RF read by 4181 to make sure that operation could be done in unlimited cycle. |
| 205 | // |
| 206 | // Assumption: |
| 207 | // - Only use on RTL8192S USB interface. |
| 208 | // - PASSIVE LEVEL |
| 209 | // - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM |
| 210 | // |
| 211 | // Created by Roger, 2008.09.06. |
| 212 | // |
| 213 | //use in phy only |
| 214 | u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) |
| 215 | { |
| 216 | |
| 217 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 218 | //u32 value = 0, ReturnValue = 0; |
| 219 | u32 ReturnValue = 0; |
| 220 | //u32 tmplong,tmplong2; |
| 221 | u8 PollingCnt = 50; |
| 222 | u8 RFWaitCounter = 0; |
| 223 | |
| 224 | |
| 225 | // |
| 226 | // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. |
| 227 | // We have to make sure that previous RF I/O has been done. |
| 228 | // 2008.08.20. |
| 229 | // |
| 230 | while(priv->bChangeRFInProgress) |
| 231 | { |
| 232 | //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 233 | //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318 |
| 234 | down(&priv->rf_sem); |
| 235 | |
| 236 | RFWaitCounter ++; |
| 237 | RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter); |
| 238 | msleep(1); // 1 ms |
| 239 | |
| 240 | if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter)) |
| 241 | { |
| 242 | RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter); |
| 243 | return 0xffffffff; |
| 244 | } |
| 245 | else |
| 246 | { |
| 247 | //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 248 | } |
| 249 | } |
| 250 | |
| 251 | priv->bChangeRFInProgress = true; |
| 252 | //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 253 | |
| 254 | |
| 255 | Offset &= 0x3f; //RF_Offset= 0x00~0x3F |
| 256 | |
| 257 | write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002| |
| 258 | (Offset<<8)| //RF_Offset= 0x00~0x3F |
| 259 | (eRFPath<<16)); //RF_Path = 0(A) or 1(B) |
| 260 | |
| 261 | do |
| 262 | {// Make sure that access could be done. |
| 263 | if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0) |
| 264 | break; |
| 265 | }while( --PollingCnt ); |
| 266 | |
| 267 | // Data FW read back. |
| 268 | ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA); |
| 269 | |
| 270 | //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 271 | //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318 |
| 272 | up(&priv->rf_sem); |
| 273 | priv->bChangeRFInProgress = false; |
| 274 | |
| 275 | RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue); |
| 276 | |
| 277 | return ReturnValue; |
| 278 | |
| 279 | } |
| 280 | |
| 281 | |
| 282 | // |
| 283 | // Description: |
| 284 | // RF wrote by 4181 to make sure that operation could be done in unlimited cycle. |
| 285 | // |
| 286 | // Assumption: |
| 287 | // - Only use on RTL8192S USB interface. |
| 288 | // - PASSIVE LEVEL |
| 289 | // - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM |
| 290 | // |
| 291 | // Created by Roger, 2008.09.06. |
| 292 | // |
| 293 | //use in phy only |
| 294 | void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAddr,u32 Data) |
| 295 | { |
| 296 | |
| 297 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 298 | u8 PollingCnt = 50; |
| 299 | u8 RFWaitCounter = 0; |
| 300 | |
| 301 | |
| 302 | // |
| 303 | // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. |
| 304 | // We have to make sure that previous BB I/O has been done. |
| 305 | // 2008.08.20. |
| 306 | // |
| 307 | while(priv->bChangeRFInProgress) |
| 308 | { |
| 309 | //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 310 | //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318 |
| 311 | down(&priv->rf_sem); |
| 312 | |
| 313 | RFWaitCounter ++; |
| 314 | RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter); |
| 315 | msleep(1); // 1 ms |
| 316 | |
| 317 | if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter)) |
| 318 | { |
| 319 | RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter); |
| 320 | return; |
| 321 | } |
| 322 | else |
| 323 | { |
| 324 | //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | priv->bChangeRFInProgress = true; |
| 329 | //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 330 | |
| 331 | |
| 332 | RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F |
| 333 | |
| 334 | write_nic_dword(dev, RF_BB_CMD_DATA, Data); |
| 335 | write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003| |
| 336 | (RegAddr<<8)| //RF_Offset= 0x00~0x3F |
| 337 | (eRFPath<<16)); //RF_Path = 0(A) or 1(B) |
| 338 | |
| 339 | do |
| 340 | {// Make sure that access could be done. |
| 341 | if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0) |
| 342 | break; |
| 343 | }while( --PollingCnt ); |
| 344 | |
| 345 | if(PollingCnt == 0) |
| 346 | { |
| 347 | RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data); |
| 348 | } |
| 349 | |
| 350 | //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); |
| 351 | //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318 |
| 352 | up(&priv->rf_sem); |
| 353 | priv->bChangeRFInProgress = false; |
| 354 | |
| 355 | } |
| 356 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 357 | |
| 358 | /*---------------------Define local function prototype-----------------------*/ |
| 359 | |
| 360 | |
| 361 | /*----------------------------Function Body----------------------------------*/ |
| 362 | // |
| 363 | // 1. BB register R/W API |
| 364 | // |
| 365 | /** |
| 366 | * Function: PHY_QueryBBReg |
| 367 | * |
| 368 | * OverView: Read "sepcific bits" from BB register |
| 369 | * |
| 370 | * Input: |
| 371 | * PADAPTER Adapter, |
| 372 | * u32 RegAddr, //The target address to be readback |
| 373 | * u32 BitMask //The target bit position in the target address |
| 374 | * //to be readback |
| 375 | * Output: None |
| 376 | * Return: u32 Data //The readback register value |
| 377 | * Note: This function is equal to "GetRegSetting" in PHY programming guide |
| 378 | */ |
| 379 | //use phy dm core 8225 8256 6052 |
| 380 | //u32 PHY_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask) |
| 381 | u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask) |
| 382 | { |
| 383 | |
| 384 | u32 ReturnValue = 0, OriginalValue, BitShift; |
| 385 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 386 | |
| 387 | RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask); |
| 388 | |
| 389 | // |
| 390 | // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use |
| 391 | // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in |
| 392 | // infinite cycle. |
| 393 | // 2008.09.06. |
| 394 | // |
| 395 | //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE)) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 396 | if(IS_BB_REG_OFFSET_92S(RegAddr)) |
| 397 | { |
| 398 | //if(RT_USB_CANNOT_IO(Adapter)) return FALSE; |
| 399 | |
| 400 | if((RegAddr & 0x03) != 0) |
| 401 | { |
| 402 | printk("%s: Not DWORD alignment!!\n", __FUNCTION__); |
| 403 | return 0; |
| 404 | } |
| 405 | |
| 406 | OriginalValue = phy_QueryUsbBBReg(dev, RegAddr); |
| 407 | } |
| 408 | else |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 409 | { |
| 410 | OriginalValue = read_nic_dword(dev, RegAddr); |
| 411 | } |
| 412 | |
| 413 | BitShift = phy_CalculateBitShift(BitMask); |
| 414 | ReturnValue = (OriginalValue & BitMask) >> BitShift; |
| 415 | |
| 416 | //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue)); |
| 417 | RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue); |
| 418 | return (ReturnValue); |
| 419 | } |
| 420 | |
| 421 | /** |
| 422 | * Function: PHY_SetBBReg |
| 423 | * |
| 424 | * OverView: Write "Specific bits" to BB register (page 8~) |
| 425 | * |
| 426 | * Input: |
| 427 | * PADAPTER Adapter, |
| 428 | * u32 RegAddr, //The target address to be modified |
| 429 | * u32 BitMask //The target bit position in the target address |
| 430 | * //to be modified |
| 431 | * u32 Data //The new register value in the target bit position |
| 432 | * //of the target address |
| 433 | * |
| 434 | * Output: None |
| 435 | * Return: None |
| 436 | * Note: This function is equal to "PutRegSetting" in PHY programming guide |
| 437 | */ |
| 438 | //use phy dm core 8225 8256 |
| 439 | //void PHY_SetBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask, u32 Data ) |
| 440 | void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data) |
| 441 | { |
| 442 | u32 OriginalValue, BitShift, NewValue; |
| 443 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 444 | |
| 445 | RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data); |
| 446 | |
| 447 | // |
| 448 | // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use |
| 449 | // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in |
| 450 | // infinite cycle. |
| 451 | // 2008.09.06. |
| 452 | // |
| 453 | //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE)) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 454 | if(IS_BB_REG_OFFSET_92S(RegAddr)) |
| 455 | { |
| 456 | if((RegAddr & 0x03) != 0) |
| 457 | { |
| 458 | printk("%s: Not DWORD alignment!!\n", __FUNCTION__); |
| 459 | return; |
| 460 | } |
| 461 | |
| 462 | if(BitMask!= bMaskDWord) |
| 463 | {//if not "double word" write |
| 464 | OriginalValue = phy_QueryUsbBBReg(dev, RegAddr); |
| 465 | BitShift = phy_CalculateBitShift(BitMask); |
| 466 | NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift)); |
| 467 | phy_SetUsbBBReg(dev, RegAddr, NewValue); |
| 468 | }else |
| 469 | phy_SetUsbBBReg(dev, RegAddr, Data); |
| 470 | } |
| 471 | else |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 472 | { |
| 473 | if(BitMask!= bMaskDWord) |
| 474 | {//if not "double word" write |
| 475 | OriginalValue = read_nic_dword(dev, RegAddr); |
| 476 | BitShift = phy_CalculateBitShift(BitMask); |
| 477 | NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift)); |
| 478 | write_nic_dword(dev, RegAddr, NewValue); |
| 479 | }else |
| 480 | write_nic_dword(dev, RegAddr, Data); |
| 481 | } |
| 482 | |
| 483 | //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data); |
| 484 | |
| 485 | return; |
| 486 | } |
| 487 | |
| 488 | |
| 489 | // |
| 490 | // 2. RF register R/W API |
| 491 | // |
| 492 | /** |
| 493 | * Function: PHY_QueryRFReg |
| 494 | * |
| 495 | * OverView: Query "Specific bits" to RF register (page 8~) |
| 496 | * |
| 497 | * Input: |
| 498 | * PADAPTER Adapter, |
| 499 | * RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D |
| 500 | * u32 RegAddr, //The target address to be read |
| 501 | * u32 BitMask //The target bit position in the target address |
| 502 | * //to be read |
| 503 | * |
| 504 | * Output: None |
| 505 | * Return: u32 Readback value |
| 506 | * Note: This function is equal to "GetRFRegSetting" in PHY programming guide |
| 507 | */ |
| 508 | //in dm 8256 and phy |
| 509 | //u32 PHY_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) |
| 510 | u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) |
| 511 | { |
| 512 | u32 Original_Value, Readback_Value, BitShift;//, flags; |
| 513 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 514 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 515 | |
| 516 | RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask); |
| 517 | |
| 518 | if (!((priv->rf_pathmap >> eRFPath) & 0x1)) |
| 519 | { |
| 520 | printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath); |
| 521 | return 0; |
| 522 | } |
| 523 | |
| 524 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 525 | { |
| 526 | printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath); |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | /* 2008/01/17 MH We get and release spin lock when reading RF register. */ |
| 531 | //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM |
| 532 | //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113 |
| 533 | down(&priv->rf_sem); |
| 534 | // |
| 535 | // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use |
| 536 | // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in |
| 537 | // infinite cycle. |
| 538 | // 2008.09.06. |
| 539 | // |
| 540 | //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 541 | //if(RT_USB_CANNOT_IO(Adapter)) return FALSE; |
| 542 | Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 543 | |
| 544 | BitShift = phy_CalculateBitShift(BitMask); |
| 545 | Readback_Value = (Original_Value & BitMask) >> BitShift; |
| 546 | //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113 |
| 547 | up(&priv->rf_sem); |
| 548 | //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK); |
| 549 | |
| 550 | //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value)); |
| 551 | |
| 552 | return (Readback_Value); |
| 553 | } |
| 554 | |
| 555 | /** |
| 556 | * Function: PHY_SetRFReg |
| 557 | * |
| 558 | * OverView: Write "Specific bits" to RF register (page 8~) |
| 559 | * |
| 560 | * Input: |
| 561 | * PADAPTER Adapter, |
| 562 | * RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D |
| 563 | * u32 RegAddr, //The target address to be modified |
| 564 | * u32 BitMask //The target bit position in the target address |
| 565 | * //to be modified |
| 566 | * u32 Data //The new register Data in the target bit position |
| 567 | * //of the target address |
| 568 | * |
| 569 | * Output: None |
| 570 | * Return: None |
| 571 | * Note: This function is equal to "PutRFRegSetting" in PHY programming guide |
| 572 | */ |
| 573 | //use phy 8225 8256 |
| 574 | //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask,u32 Data ) |
| 575 | void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) |
| 576 | { |
| 577 | |
| 578 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 579 | u32 Original_Value, BitShift, New_Value;//, flags; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 580 | |
| 581 | RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n", |
| 582 | RegAddr, BitMask, Data, eRFPath); |
| 583 | |
| 584 | if (!((priv->rf_pathmap >> eRFPath) & 0x1)) |
| 585 | { |
| 586 | printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath); |
| 587 | return ; |
| 588 | } |
| 589 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 590 | { |
| 591 | printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath); |
| 592 | return; |
| 593 | } |
| 594 | |
| 595 | /* 2008/01/17 MH We get and release spin lock when writing RF register. */ |
| 596 | //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK); |
| 597 | //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113 |
| 598 | down(&priv->rf_sem); |
| 599 | // |
| 600 | // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use |
| 601 | // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in |
| 602 | // infinite cycle. |
| 603 | // 2008.09.06. |
| 604 | // |
| 605 | //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 606 | //if(RT_USB_CANNOT_IO(Adapter)) return; |
| 607 | |
| 608 | if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only |
| 609 | { |
| 610 | Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr); |
| 611 | BitShift = phy_CalculateBitShift(BitMask); |
| 612 | New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift)); |
| 613 | phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value); |
| 614 | } |
| 615 | else |
| 616 | phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 617 | //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK); |
| 618 | //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113 |
| 619 | up(&priv->rf_sem); |
| 620 | //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data)); |
| 621 | RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n", |
| 622 | RegAddr, BitMask, Data, eRFPath); |
| 623 | |
| 624 | } |
| 625 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 626 | /** |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 627 | * Function: phy_CalculateBitShift |
| 628 | * |
| 629 | * OverView: Get shifted position of the BitMask |
| 630 | * |
| 631 | * Input: |
| 632 | * u32 BitMask, |
| 633 | * |
| 634 | * Output: none |
| 635 | * Return: u32 Return the shift bit bit position of the mask |
| 636 | */ |
| 637 | //use in phy only |
| 638 | static u32 phy_CalculateBitShift(u32 BitMask) |
| 639 | { |
| 640 | u32 i; |
| 641 | |
| 642 | for(i=0; i<=31; i++) |
| 643 | { |
| 644 | if ( ((BitMask>>i) & 0x1 ) == 1) |
| 645 | break; |
| 646 | } |
| 647 | |
| 648 | return (i); |
| 649 | } |
| 650 | |
| 651 | |
| 652 | // |
| 653 | // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. |
| 654 | // |
| 655 | /*----------------------------------------------------------------------------- |
| 656 | * Function: PHY_MACConfig8192S |
| 657 | * |
| 658 | * Overview: Condig MAC by header file or parameter file. |
| 659 | * |
| 660 | * Input: NONE |
| 661 | * |
| 662 | * Output: NONE |
| 663 | * |
| 664 | * Return: NONE |
| 665 | * |
| 666 | * Revised History: |
| 667 | * When Who Remark |
| 668 | * 08/12/2008 MHC Create Version 0. |
| 669 | * |
| 670 | *---------------------------------------------------------------------------*/ |
| 671 | //adapter_start |
| 672 | extern bool PHY_MACConfig8192S(struct net_device* dev) |
| 673 | { |
| 674 | RT_STATUS rtStatus = RT_STATUS_SUCCESS; |
| 675 | |
| 676 | // |
| 677 | // Config MAC |
| 678 | // |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 679 | rtStatus = phy_ConfigMACWithHeaderFile(dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 680 | return (rtStatus == RT_STATUS_SUCCESS) ? true:false; |
| 681 | |
| 682 | } |
| 683 | |
| 684 | //adapter_start |
| 685 | extern bool |
| 686 | PHY_BBConfig8192S(struct net_device* dev) |
| 687 | { |
| 688 | RT_STATUS rtStatus = RT_STATUS_SUCCESS; |
| 689 | |
| 690 | u8 PathMap = 0, index = 0, rf_num = 0; |
| 691 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 692 | phy_InitBBRFRegisterDefinition(dev); |
| 693 | |
| 694 | // |
| 695 | // Config BB and AGC |
| 696 | // |
| 697 | //switch( Adapter->MgntInfo.bRegHwParaFile ) |
| 698 | //{ |
| 699 | // case 0: |
| 700 | // phy_BB8190_Config_HardCode(dev); |
| 701 | // break; |
| 702 | |
| 703 | // case 1: |
| 704 | rtStatus = phy_BB8192S_Config_ParaFile(dev); |
| 705 | // break; |
| 706 | |
| 707 | // case 2: |
| 708 | // Partial Modify. |
| 709 | // phy_BB8190_Config_HardCode(dev); |
| 710 | // phy_BB8192S_Config_ParaFile(dev); |
| 711 | // break; |
| 712 | |
| 713 | // default: |
| 714 | // phy_BB8190_Config_HardCode(dev); |
| 715 | // break; |
| 716 | //} |
| 717 | PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) | |
| 718 | rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf)); |
| 719 | priv->rf_pathmap = PathMap; |
| 720 | for(index = 0; index<4; index++) |
| 721 | { |
| 722 | if((PathMap>>index)&0x1) |
| 723 | rf_num++; |
| 724 | } |
| 725 | |
| 726 | if((priv->rf_type==RF_1T1R && rf_num!=1) || |
| 727 | (priv->rf_type==RF_1T2R && rf_num!=2) || |
| 728 | (priv->rf_type==RF_2T2R && rf_num!=2) || |
| 729 | (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) || |
| 730 | (priv->rf_type==RF_2T4R && rf_num!=4)) |
| 731 | { |
| 732 | RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num); |
| 733 | } |
| 734 | return (rtStatus == RT_STATUS_SUCCESS) ? 1:0; |
| 735 | } |
| 736 | |
| 737 | //adapter_start |
| 738 | extern bool |
| 739 | PHY_RFConfig8192S(struct net_device* dev) |
| 740 | { |
| 741 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 742 | RT_STATUS rtStatus = RT_STATUS_SUCCESS; |
| 743 | |
| 744 | //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization |
| 745 | |
| 746 | //<Roger_EXP> We assign RF type here temporally. 2008.09.12. |
| 747 | priv->rf_chip = RF_6052; |
| 748 | |
| 749 | // |
| 750 | // RF config |
| 751 | // |
| 752 | switch(priv->rf_chip) |
| 753 | { |
| 754 | case RF_8225: |
| 755 | case RF_6052: |
| 756 | rtStatus = PHY_RF6052_Config(dev); |
| 757 | break; |
| 758 | |
| 759 | case RF_8256: |
| 760 | //rtStatus = PHY_RF8256_Config(dev); |
| 761 | break; |
| 762 | |
| 763 | case RF_8258: |
| 764 | break; |
| 765 | |
| 766 | case RF_PSEUDO_11N: |
| 767 | //rtStatus = PHY_RF8225_Config(dev); |
| 768 | break; |
| 769 | default: |
| 770 | break; |
| 771 | } |
| 772 | |
| 773 | return (rtStatus == RT_STATUS_SUCCESS) ? 1:0; |
| 774 | } |
| 775 | |
| 776 | |
| 777 | // Joseph test: new initialize order!! |
| 778 | // Test only!! This part need to be re-organized. |
| 779 | // Now it is just for 8256. |
| 780 | //use in phy only |
| 781 | #ifdef TO_DO_LIST |
| 782 | static RT_STATUS |
| 783 | phy_BB8190_Config_HardCode(struct net_device* dev) |
| 784 | { |
| 785 | //RT_ASSERT(FALSE, ("This function is not implement yet!! \n")); |
| 786 | return RT_STATUS_SUCCESS; |
| 787 | } |
| 788 | #endif |
| 789 | |
| 790 | /*----------------------------------------------------------------------------- |
| 791 | * Function: phy_SetBBtoDiffRFWithHeaderFile() |
| 792 | * |
| 793 | * Overview: This function |
| 794 | * |
| 795 | * |
| 796 | * Input: PADAPTER Adapter |
| 797 | * u1Byte ConfigType 0 => PHY_CONFIG |
| 798 | * |
| 799 | * Output: NONE |
| 800 | * |
| 801 | * Return: RT_STATUS_SUCCESS: configuration file exist |
| 802 | * When Who Remark |
| 803 | * 2008/11/10 tynli |
| 804 | * use in phy only |
| 805 | *---------------------------------------------------------------------------*/ |
| 806 | static RT_STATUS |
| 807 | phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType) |
| 808 | { |
| 809 | int i; |
| 810 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 811 | u32* Rtl819XPHY_REGArraytoXTXR_Table; |
| 812 | u16 PHY_REGArraytoXTXRLen; |
| 813 | |
| 814 | //#if (HAL_CODE_BASE != RTL8192_S) |
| 815 | |
| 816 | if(priv->rf_type == RF_1T1R) |
| 817 | { |
| 818 | Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array; |
| 819 | PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength; |
| 820 | } |
| 821 | else if(priv->rf_type == RF_1T2R) |
| 822 | { |
| 823 | Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array; |
| 824 | PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength; |
| 825 | } |
| 826 | //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN) |
| 827 | //{ |
| 828 | // Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array; |
| 829 | // PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength; |
| 830 | //} |
| 831 | else |
| 832 | { |
| 833 | return RT_STATUS_FAILURE; |
| 834 | } |
| 835 | |
| 836 | if(ConfigType == BaseBand_Config_PHY_REG) |
| 837 | { |
| 838 | for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3) |
| 839 | { |
| 840 | if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe) |
| 841 | mdelay(50); |
| 842 | else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd) |
| 843 | mdelay(5); |
| 844 | else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc) |
| 845 | mdelay(1); |
| 846 | else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb) |
| 847 | udelay(50); |
| 848 | else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa) |
| 849 | udelay(5); |
| 850 | else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9) |
| 851 | udelay(1); |
| 852 | rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]); |
| 853 | //RT_TRACE(COMP_SEND, |
| 854 | //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n", |
| 855 | //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]); |
| 856 | } |
| 857 | } |
| 858 | else { |
| 859 | RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"); |
| 860 | } |
| 861 | //#endif // #if (HAL_CODE_BASE != RTL8192_S) |
| 862 | return RT_STATUS_SUCCESS; |
| 863 | } |
| 864 | |
| 865 | |
| 866 | //use in phy only |
| 867 | static RT_STATUS |
| 868 | phy_BB8192S_Config_ParaFile(struct net_device* dev) |
| 869 | { |
| 870 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 871 | RT_STATUS rtStatus = RT_STATUS_SUCCESS; |
| 872 | //u8 u2RegValue; |
| 873 | //u16 u4RegValue; |
| 874 | //char szBBRegFile[] = RTL819X_PHY_REG; |
| 875 | //char szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R; |
| 876 | //char szBBRegPgFile[] = RTL819X_PHY_REG_PG; |
| 877 | //char szAGCTableFile[] = RTL819X_AGC_TAB; |
| 878 | //char szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R; |
| 879 | //char szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R; |
| 880 | |
| 881 | RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n"); |
| 882 | |
| 883 | // |
| 884 | // 1. Read PHY_REG.TXT BB INIT!! |
| 885 | // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R |
| 886 | // |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 887 | if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R || |
| 888 | priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN) |
| 889 | { |
| 890 | rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG); |
| 891 | if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN) |
| 892 | {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R, |
| 893 | //so we should reconfig BB reg with the right PHY parameters. |
| 894 | rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG); |
| 895 | } |
| 896 | }else |
| 897 | rtStatus = RT_STATUS_FAILURE; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 898 | |
| 899 | if(rtStatus != RT_STATUS_SUCCESS){ |
| 900 | RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"); |
| 901 | goto phy_BB8190_Config_ParaFile_Fail; |
| 902 | } |
| 903 | |
| 904 | // |
| 905 | // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt |
| 906 | // |
| 907 | if (priv->AutoloadFailFlag == false) |
| 908 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 909 | rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 910 | } |
| 911 | if(rtStatus != RT_STATUS_SUCCESS){ |
| 912 | RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!"); |
| 913 | goto phy_BB8190_Config_ParaFile_Fail; |
| 914 | } |
| 915 | |
| 916 | // |
| 917 | // 3. BB AGC table Initialization |
| 918 | // |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 919 | rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 920 | |
| 921 | if(rtStatus != RT_STATUS_SUCCESS){ |
| 922 | printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n"); |
| 923 | goto phy_BB8190_Config_ParaFile_Fail; |
| 924 | } |
| 925 | |
| 926 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 927 | // Check if the CCK HighPower is turned ON. |
| 928 | // This is used to calculate PWDB. |
| 929 | priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); |
| 930 | |
| 931 | |
| 932 | phy_BB8190_Config_ParaFile_Fail: |
| 933 | return rtStatus; |
| 934 | } |
| 935 | |
| 936 | /*----------------------------------------------------------------------------- |
| 937 | * Function: phy_ConfigMACWithHeaderFile() |
| 938 | * |
| 939 | * Overview: This function read BB parameters from Header file we gen, and do register |
| 940 | * Read/Write |
| 941 | * |
| 942 | * Input: PADAPTER Adapter |
| 943 | * char* pFileName |
| 944 | * |
| 945 | * Output: NONE |
| 946 | * |
| 947 | * Return: RT_STATUS_SUCCESS: configuration file exist |
| 948 | * |
| 949 | * Note: The format of MACPHY_REG.txt is different from PHY and RF. |
| 950 | * [Register][Mask][Value] |
| 951 | *---------------------------------------------------------------------------*/ |
| 952 | //use in phy only |
| 953 | static RT_STATUS |
| 954 | phy_ConfigMACWithHeaderFile(struct net_device* dev) |
| 955 | { |
| 956 | u32 i = 0; |
| 957 | u32 ArrayLength = 0; |
| 958 | u32* ptrArray; |
| 959 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 960 | |
| 961 | //#if (HAL_CODE_BASE != RTL8192_S) |
| 962 | /*if(Adapter->bInHctTest) |
| 963 | { |
| 964 | RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n")); |
| 965 | ArrayLength = MACPHY_ArrayLengthDTM; |
| 966 | ptrArray = Rtl819XMACPHY_ArrayDTM; |
| 967 | } |
| 968 | else if(pHalData->bTXPowerDataReadFromEEPORM) |
| 969 | { |
| 970 | // RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n")); |
| 971 | // ArrayLength = MACPHY_Array_PGLength; |
| 972 | // ptrArray = Rtl819XMACPHY_Array_PG; |
| 973 | |
| 974 | }else*/ |
| 975 | { //2008.11.06 Modified by tynli. |
| 976 | RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n"); |
| 977 | ArrayLength = MAC_2T_ArrayLength; |
| 978 | ptrArray = Rtl819XMAC_Array; |
| 979 | } |
| 980 | |
| 981 | /*for(i = 0 ;i < ArrayLength;i=i+3){ |
| 982 | RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2])); |
| 983 | if(ptrArray[i] == 0x318) |
| 984 | { |
| 985 | ptrArray[i+2] = 0x00000800; |
| 986 | //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", |
| 987 | // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); |
| 988 | } |
| 989 | PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]); |
| 990 | }*/ |
| 991 | for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column |
| 992 | write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]); |
| 993 | } |
| 994 | //#endif |
| 995 | return RT_STATUS_SUCCESS; |
| 996 | } |
| 997 | |
| 998 | /*----------------------------------------------------------------------------- |
| 999 | * Function: phy_ConfigBBWithHeaderFile() |
| 1000 | * |
| 1001 | * Overview: This function read BB parameters from general file format, and do register |
| 1002 | * Read/Write |
| 1003 | * |
| 1004 | * Input: PADAPTER Adapter |
| 1005 | * u8 ConfigType 0 => PHY_CONFIG |
| 1006 | * 1 =>AGC_TAB |
| 1007 | * |
| 1008 | * Output: NONE |
| 1009 | * |
| 1010 | * Return: RT_STATUS_SUCCESS: configuration file exist |
| 1011 | * |
| 1012 | *---------------------------------------------------------------------------*/ |
| 1013 | //use in phy only |
| 1014 | static RT_STATUS |
| 1015 | phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType) |
| 1016 | { |
| 1017 | int i; |
| 1018 | //u8 ArrayLength; |
| 1019 | u32* Rtl819XPHY_REGArray_Table; |
| 1020 | u32* Rtl819XAGCTAB_Array_Table; |
| 1021 | u16 PHY_REGArrayLen, AGCTAB_ArrayLen; |
| 1022 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 1023 | //#if (HAL_CODE_BASE != RTL8192_S) |
| 1024 | /*if(Adapter->bInHctTest) |
| 1025 | { |
| 1026 | |
| 1027 | AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; |
| 1028 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; |
| 1029 | |
| 1030 | if(pHalData->RF_Type == RF_2T4R) |
| 1031 | { |
| 1032 | PHY_REGArrayLen = PHY_REGArrayLengthDTM; |
| 1033 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; |
| 1034 | } |
| 1035 | else if (pHalData->RF_Type == RF_1T2R) |
| 1036 | { |
| 1037 | PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM; |
| 1038 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM; |
| 1039 | } |
| 1040 | |
| 1041 | } |
| 1042 | else |
| 1043 | */ |
| 1044 | //{ |
| 1045 | // |
| 1046 | // 2008.11.06 Modified by tynli. |
| 1047 | // |
| 1048 | AGCTAB_ArrayLen = AGCTAB_ArrayLength; |
| 1049 | Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; |
| 1050 | PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R |
| 1051 | Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array; |
| 1052 | //} |
| 1053 | |
| 1054 | if(ConfigType == BaseBand_Config_PHY_REG) |
| 1055 | { |
| 1056 | for(i=0;i<PHY_REGArrayLen;i=i+2) |
| 1057 | { |
| 1058 | if (Rtl819XPHY_REGArray_Table[i] == 0xfe) |
| 1059 | mdelay(50); |
| 1060 | else if (Rtl819XPHY_REGArray_Table[i] == 0xfd) |
| 1061 | mdelay(5); |
| 1062 | else if (Rtl819XPHY_REGArray_Table[i] == 0xfc) |
| 1063 | mdelay(1); |
| 1064 | else if (Rtl819XPHY_REGArray_Table[i] == 0xfb) |
| 1065 | udelay(50); |
| 1066 | else if (Rtl819XPHY_REGArray_Table[i] == 0xfa) |
| 1067 | udelay(5); |
| 1068 | else if (Rtl819XPHY_REGArray_Table[i] == 0xf9) |
| 1069 | udelay(1); |
| 1070 | rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); |
| 1071 | //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); |
| 1072 | |
| 1073 | } |
| 1074 | } |
| 1075 | else if(ConfigType == BaseBand_Config_AGC_TAB){ |
| 1076 | for(i=0;i<AGCTAB_ArrayLen;i=i+2) |
| 1077 | { |
| 1078 | rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); |
| 1079 | } |
| 1080 | } |
| 1081 | //#endif // #if (HAL_CODE_BASE != RTL8192_S) |
| 1082 | return RT_STATUS_SUCCESS; |
| 1083 | } |
| 1084 | |
| 1085 | /*----------------------------------------------------------------------------- |
| 1086 | * Function: phy_ConfigBBWithPgHeaderFile |
| 1087 | * |
| 1088 | * Overview: Config PHY_REG_PG array |
| 1089 | * |
| 1090 | * Input: NONE |
| 1091 | * |
| 1092 | * Output: NONE |
| 1093 | * |
| 1094 | * Return: NONE |
| 1095 | * |
| 1096 | * Revised History: |
| 1097 | * When Who Remark |
| 1098 | * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!! |
| 1099 | * 11/10/2008 tynli Modify to mew files. |
| 1100 | //use in phy only |
| 1101 | *---------------------------------------------------------------------------*/ |
| 1102 | static RT_STATUS |
| 1103 | phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType) |
| 1104 | { |
| 1105 | int i; |
| 1106 | //u8 ArrayLength; |
| 1107 | u32* Rtl819XPHY_REGArray_Table_PG; |
| 1108 | u16 PHY_REGArrayPGLen; |
| 1109 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 1110 | //#if (HAL_CODE_BASE != RTL8192_S) |
| 1111 | // Default: pHalData->RF_Type = RF_2T2R. |
| 1112 | |
| 1113 | PHY_REGArrayPGLen = PHY_REG_Array_PGLength; |
| 1114 | Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG; |
| 1115 | |
| 1116 | if(ConfigType == BaseBand_Config_PHY_REG) |
| 1117 | { |
| 1118 | for(i=0;i<PHY_REGArrayPGLen;i=i+3) |
| 1119 | { |
| 1120 | if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe) |
| 1121 | mdelay(50); |
| 1122 | else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd) |
| 1123 | mdelay(5); |
| 1124 | else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc) |
| 1125 | mdelay(1); |
| 1126 | else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb) |
| 1127 | udelay(50); |
| 1128 | else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa) |
| 1129 | udelay(5); |
| 1130 | else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9) |
| 1131 | udelay(1); |
| 1132 | rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]); |
| 1133 | //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n", |
| 1134 | // Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]); |
| 1135 | } |
| 1136 | }else{ |
| 1137 | RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"); |
| 1138 | } |
| 1139 | return RT_STATUS_SUCCESS; |
| 1140 | |
| 1141 | } /* phy_ConfigBBWithPgHeaderFile */ |
| 1142 | |
| 1143 | /*----------------------------------------------------------------------------- |
| 1144 | * Function: PHY_ConfigRFWithHeaderFile() |
| 1145 | * |
| 1146 | * Overview: This function read RF parameters from general file format, and do RF 3-wire |
| 1147 | * |
| 1148 | * Input: PADAPTER Adapter |
| 1149 | * char* pFileName |
| 1150 | * RF90_RADIO_PATH_E eRFPath |
| 1151 | * |
| 1152 | * Output: NONE |
| 1153 | * |
| 1154 | * Return: RT_STATUS_SUCCESS: configuration file exist |
| 1155 | * |
| 1156 | * Note: Delay may be required for RF configuration |
| 1157 | *---------------------------------------------------------------------------*/ |
| 1158 | //in 8256 phy_RF8256_Config_ParaFile only |
| 1159 | //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath) |
| 1160 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) |
| 1161 | { |
| 1162 | |
| 1163 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1164 | int i; |
| 1165 | //u32* pRFArray; |
| 1166 | RT_STATUS rtStatus = RT_STATUS_SUCCESS; |
| 1167 | u32 *Rtl819XRadioA_Array_Table; |
| 1168 | u32 *Rtl819XRadioB_Array_Table; |
| 1169 | //u32* Rtl819XRadioC_Array_Table; |
| 1170 | //u32* Rtl819XRadioD_Array_Table; |
| 1171 | u16 RadioA_ArrayLen,RadioB_ArrayLen; |
| 1172 | |
| 1173 | { //2008.11.06 Modified by tynli |
| 1174 | RadioA_ArrayLen = RadioA_1T_ArrayLength; |
| 1175 | Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array; |
| 1176 | Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array; |
| 1177 | RadioB_ArrayLen = RadioB_ArrayLength; |
| 1178 | } |
| 1179 | |
| 1180 | if( priv->rf_type == RF_2T2R_GREEN ) |
| 1181 | { |
| 1182 | Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array; |
| 1183 | RadioB_ArrayLen = RadioB_GM_ArrayLength; |
| 1184 | } |
| 1185 | else |
| 1186 | { |
| 1187 | Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array; |
| 1188 | RadioB_ArrayLen = RadioB_ArrayLength; |
| 1189 | } |
| 1190 | |
| 1191 | rtStatus = RT_STATUS_SUCCESS; |
| 1192 | |
| 1193 | // When initialization, we want the delay function(mdelay(), delay_us() |
| 1194 | // ==> actually we call PlatformStallExecution()) to do NdisStallExecution() |
| 1195 | // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK |
| 1196 | // to run at Dispatch level to achive it. |
| 1197 | //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK); |
| 1198 | |
| 1199 | switch(eRFPath){ |
| 1200 | case RF90_PATH_A: |
| 1201 | for(i = 0;i<RadioA_ArrayLen; i=i+2){ |
| 1202 | if(Rtl819XRadioA_Array_Table[i] == 0xfe) |
| 1203 | { // Deay specific ms. Only RF configuration require delay. |
| 1204 | //#if (DEV_BUS_TYPE == USB_INTERFACE) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1205 | mdelay(1000); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1206 | } |
| 1207 | else if (Rtl819XRadioA_Array_Table[i] == 0xfd) |
| 1208 | mdelay(5); |
| 1209 | else if (Rtl819XRadioA_Array_Table[i] == 0xfc) |
| 1210 | mdelay(1); |
| 1211 | else if (Rtl819XRadioA_Array_Table[i] == 0xfb) |
| 1212 | udelay(50); |
| 1213 | //PlatformStallExecution(50); |
| 1214 | else if (Rtl819XRadioA_Array_Table[i] == 0xfa) |
| 1215 | udelay(5); |
| 1216 | else if (Rtl819XRadioA_Array_Table[i] == 0xf9) |
| 1217 | udelay(1); |
| 1218 | else |
| 1219 | { |
| 1220 | rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]); |
| 1221 | } |
| 1222 | } |
| 1223 | break; |
| 1224 | case RF90_PATH_B: |
| 1225 | for(i = 0;i<RadioB_ArrayLen; i=i+2){ |
| 1226 | if(Rtl819XRadioB_Array_Table[i] == 0xfe) |
| 1227 | { // Deay specific ms. Only RF configuration require delay. |
| 1228 | //#if (DEV_BUS_TYPE == USB_INTERFACE) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1229 | mdelay(1000); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1230 | } |
| 1231 | else if (Rtl819XRadioB_Array_Table[i] == 0xfd) |
| 1232 | mdelay(5); |
| 1233 | else if (Rtl819XRadioB_Array_Table[i] == 0xfc) |
| 1234 | mdelay(1); |
| 1235 | else if (Rtl819XRadioB_Array_Table[i] == 0xfb) |
| 1236 | udelay(50); |
| 1237 | else if (Rtl819XRadioB_Array_Table[i] == 0xfa) |
| 1238 | udelay(5); |
| 1239 | else if (Rtl819XRadioB_Array_Table[i] == 0xf9) |
| 1240 | udelay(1); |
| 1241 | else |
| 1242 | { |
| 1243 | rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]); |
| 1244 | } |
| 1245 | } |
| 1246 | break; |
| 1247 | case RF90_PATH_C: |
| 1248 | break; |
| 1249 | case RF90_PATH_D: |
| 1250 | break; |
| 1251 | default: |
| 1252 | break; |
| 1253 | } |
| 1254 | |
| 1255 | return rtStatus; |
| 1256 | |
| 1257 | } |
| 1258 | |
| 1259 | /*----------------------------------------------------------------------------- |
| 1260 | * Function: PHY_CheckBBAndRFOK() |
| 1261 | * |
| 1262 | * Overview: This function is write register and then readback to make sure whether |
| 1263 | * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok |
| 1264 | * |
| 1265 | * Input: PADAPTER Adapter |
| 1266 | * HW90_BLOCK_E CheckBlock |
| 1267 | * RF90_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF |
| 1268 | * |
| 1269 | * Output: NONE |
| 1270 | * |
| 1271 | * Return: RT_STATUS_SUCCESS: PHY is OK |
| 1272 | * |
| 1273 | * Note: This function may be removed in the ASIC |
| 1274 | *---------------------------------------------------------------------------*/ |
| 1275 | //in 8256 phy_RF8256_Config_HardCode |
| 1276 | //but we don't use it temp |
| 1277 | RT_STATUS |
| 1278 | PHY_CheckBBAndRFOK( |
| 1279 | struct net_device* dev, |
| 1280 | HW90_BLOCK_E CheckBlock, |
| 1281 | RF90_RADIO_PATH_E eRFPath |
| 1282 | ) |
| 1283 | { |
| 1284 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 1285 | RT_STATUS rtStatus = RT_STATUS_SUCCESS; |
| 1286 | u32 i, CheckTimes = 4,ulRegRead = 0; |
| 1287 | u32 WriteAddr[4]; |
| 1288 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; |
| 1289 | |
| 1290 | // Initialize register address offset to be checked |
| 1291 | WriteAddr[HW90_BLOCK_MAC] = 0x100; |
| 1292 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; |
| 1293 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; |
| 1294 | WriteAddr[HW90_BLOCK_RF] = 0x3; |
| 1295 | |
| 1296 | for(i=0 ; i < CheckTimes ; i++) |
| 1297 | { |
| 1298 | |
| 1299 | // |
| 1300 | // Write Data to register and readback |
| 1301 | // |
| 1302 | switch(CheckBlock) |
| 1303 | { |
| 1304 | case HW90_BLOCK_MAC: |
| 1305 | //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!")); |
| 1306 | RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); |
| 1307 | break; |
| 1308 | |
| 1309 | case HW90_BLOCK_PHY0: |
| 1310 | case HW90_BLOCK_PHY1: |
| 1311 | write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); |
| 1312 | ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); |
| 1313 | break; |
| 1314 | |
| 1315 | case HW90_BLOCK_RF: |
| 1316 | // When initialization, we want the delay function(mdelay(), delay_us() |
| 1317 | // ==> actually we call PlatformStallExecution()) to do NdisStallExecution() |
| 1318 | // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK |
| 1319 | // to run at Dispatch level to achive it. |
| 1320 | //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK); |
| 1321 | WriteData[i] &= 0xfff; |
| 1322 | rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]); |
| 1323 | // TODO: we should not delay for such a long time. Ask SD3 |
| 1324 | mdelay(10); |
| 1325 | ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); |
| 1326 | mdelay(10); |
| 1327 | //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK); |
| 1328 | break; |
| 1329 | |
| 1330 | default: |
| 1331 | rtStatus = RT_STATUS_FAILURE; |
| 1332 | break; |
| 1333 | } |
| 1334 | |
| 1335 | |
| 1336 | // |
| 1337 | // Check whether readback data is correct |
| 1338 | // |
| 1339 | if(ulRegRead != WriteData[i]) |
| 1340 | { |
| 1341 | //RT_TRACE(COMP_FPGA, ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i])); |
| 1342 | RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]); |
| 1343 | rtStatus = RT_STATUS_FAILURE; |
| 1344 | break; |
| 1345 | } |
| 1346 | } |
| 1347 | |
| 1348 | return rtStatus; |
| 1349 | } |
| 1350 | |
| 1351 | //no use temp in windows driver |
| 1352 | #ifdef TO_DO_LIST |
| 1353 | void |
| 1354 | PHY_SetRFPowerState8192SUsb( |
| 1355 | struct net_device* dev, |
| 1356 | RF_POWER_STATE RFPowerState |
| 1357 | ) |
| 1358 | { |
| 1359 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1360 | bool WaitShutDown = FALSE; |
| 1361 | u32 DWordContent; |
| 1362 | //RF90_RADIO_PATH_E eRFPath; |
| 1363 | u8 eRFPath; |
| 1364 | BB_REGISTER_DEFINITION_T *pPhyReg; |
| 1365 | |
| 1366 | if(priv->SetRFPowerStateInProgress == TRUE) |
| 1367 | return; |
| 1368 | |
| 1369 | priv->SetRFPowerStateInProgress = TRUE; |
| 1370 | |
| 1371 | // TODO: Emily, 2006.11.21, we should rewrite this function |
| 1372 | |
| 1373 | if(RFPowerState==RF_SHUT_DOWN) |
| 1374 | { |
| 1375 | RFPowerState=RF_OFF; |
| 1376 | WaitShutDown=TRUE; |
| 1377 | } |
| 1378 | |
| 1379 | |
| 1380 | priv->RFPowerState = RFPowerState; |
| 1381 | switch( priv->rf_chip ) |
| 1382 | { |
| 1383 | case RF_8225: |
| 1384 | case RF_6052: |
| 1385 | switch( RFPowerState ) |
| 1386 | { |
| 1387 | case RF_ON: |
| 1388 | break; |
| 1389 | |
| 1390 | case RF_SLEEP: |
| 1391 | break; |
| 1392 | |
| 1393 | case RF_OFF: |
| 1394 | break; |
| 1395 | } |
| 1396 | break; |
| 1397 | |
| 1398 | case RF_8256: |
| 1399 | switch( RFPowerState ) |
| 1400 | { |
| 1401 | case RF_ON: |
| 1402 | break; |
| 1403 | |
| 1404 | case RF_SLEEP: |
| 1405 | break; |
| 1406 | |
| 1407 | case RF_OFF: |
| 1408 | for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++) |
| 1409 | { |
| 1410 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 1411 | continue; |
| 1412 | |
| 1413 | pPhyReg = &priv->PHYRegDef[eRFPath]; |
| 1414 | rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV); |
| 1415 | rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0); |
| 1416 | } |
| 1417 | break; |
| 1418 | } |
| 1419 | break; |
| 1420 | |
| 1421 | case RF_8258: |
| 1422 | break; |
| 1423 | }// switch( priv->rf_chip ) |
| 1424 | |
| 1425 | priv->SetRFPowerStateInProgress = FALSE; |
| 1426 | } |
| 1427 | #endif |
| 1428 | |
| 1429 | #ifdef RTL8192U |
| 1430 | //no use temp in windows driver |
| 1431 | void |
| 1432 | PHY_UpdateInitialGain( |
| 1433 | struct net_device* dev |
| 1434 | ) |
| 1435 | { |
| 1436 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1437 | //unsigned char *IGTable; |
| 1438 | //u8 DIG_CurrentInitialGain = 4; |
| 1439 | |
| 1440 | switch(priv->rf_chip) |
| 1441 | { |
| 1442 | case RF_8225: |
| 1443 | break; |
| 1444 | case RF_8256: |
| 1445 | break; |
| 1446 | case RF_8258: |
| 1447 | break; |
| 1448 | case RF_PSEUDO_11N: |
| 1449 | break; |
| 1450 | case RF_6052: |
| 1451 | break; |
| 1452 | default: |
| 1453 | RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip); |
| 1454 | break; |
| 1455 | } |
| 1456 | } |
| 1457 | #endif |
| 1458 | |
| 1459 | //YJ,modified,090107 |
| 1460 | void PHY_GetHWRegOriginalValue(struct net_device* dev) |
| 1461 | { |
| 1462 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1463 | |
| 1464 | // read tx power offset |
| 1465 | // Simulate 8192 |
| 1466 | priv->MCSTxPowerLevelOriginalOffset[0] = |
| 1467 | rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord); |
| 1468 | priv->MCSTxPowerLevelOriginalOffset[1] = |
| 1469 | rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord); |
| 1470 | priv->MCSTxPowerLevelOriginalOffset[2] = |
| 1471 | rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord); |
| 1472 | priv->MCSTxPowerLevelOriginalOffset[3] = |
| 1473 | rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord); |
| 1474 | priv->MCSTxPowerLevelOriginalOffset[4] = |
| 1475 | rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord); |
| 1476 | priv->MCSTxPowerLevelOriginalOffset[5] = |
| 1477 | rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord); |
| 1478 | |
| 1479 | // Read CCK offset |
| 1480 | priv->MCSTxPowerLevelOriginalOffset[6] = |
| 1481 | rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord); |
| 1482 | RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n", |
| 1483 | priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] , |
| 1484 | priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] , |
| 1485 | priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] ); |
| 1486 | |
| 1487 | // read rx initial gain |
| 1488 | priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0); |
| 1489 | priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0); |
| 1490 | priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0); |
| 1491 | priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0); |
| 1492 | RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", |
| 1493 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], |
| 1494 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); |
| 1495 | |
| 1496 | // read framesync |
| 1497 | priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0); |
| 1498 | priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord); |
| 1499 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", |
| 1500 | rOFDM0_RxDetector3, priv->framesync); |
| 1501 | } |
| 1502 | //YJ,modified,090107,end |
| 1503 | |
| 1504 | |
| 1505 | |
| 1506 | /** |
| 1507 | * Function: phy_InitBBRFRegisterDefinition |
| 1508 | * |
| 1509 | * OverView: Initialize Register definition offset for Radio Path A/B/C/D |
| 1510 | * |
| 1511 | * Input: |
| 1512 | * PADAPTER Adapter, |
| 1513 | * |
| 1514 | * Output: None |
| 1515 | * Return: None |
| 1516 | * Note: The initialization value is constant and it should never be changes |
| 1517 | */ |
| 1518 | //use in phy only |
| 1519 | static void phy_InitBBRFRegisterDefinition( struct net_device* dev) |
| 1520 | { |
| 1521 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1522 | |
| 1523 | // RF Interface Sowrtware Control |
| 1524 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 |
| 1525 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) |
| 1526 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 |
| 1527 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) |
| 1528 | |
| 1529 | // RF Interface Readback Value |
| 1530 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 |
| 1531 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) |
| 1532 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 |
| 1533 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) |
| 1534 | |
| 1535 | // RF Interface Output (and Enable) |
| 1536 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 |
| 1537 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 |
| 1538 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 |
| 1539 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C |
| 1540 | |
| 1541 | // RF Interface (Output and) Enable |
| 1542 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) |
| 1543 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) |
| 1544 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) |
| 1545 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) |
| 1546 | |
| 1547 | //Addr of LSSI. Wirte RF register by driver |
| 1548 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter |
| 1549 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; |
| 1550 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; |
| 1551 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; |
| 1552 | |
| 1553 | // RF parameter |
| 1554 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select |
| 1555 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; |
| 1556 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 1557 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 1558 | |
| 1559 | // Tx AGC Gain Stage (same for all path. Should we remove this?) |
| 1560 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 1561 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 1562 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 1563 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 1564 | |
| 1565 | // Tranceiver A~D HSSI Parameter-1 |
| 1566 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 |
| 1567 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 |
| 1568 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 |
| 1569 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 |
| 1570 | |
| 1571 | // Tranceiver A~D HSSI Parameter-2 |
| 1572 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 |
| 1573 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 |
| 1574 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 |
| 1575 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 |
| 1576 | |
| 1577 | // RF switch Control |
| 1578 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control |
| 1579 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; |
| 1580 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 1581 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 1582 | |
| 1583 | // AGC control 1 |
| 1584 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; |
| 1585 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; |
| 1586 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; |
| 1587 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; |
| 1588 | |
| 1589 | // AGC control 2 |
| 1590 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; |
| 1591 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; |
| 1592 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; |
| 1593 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; |
| 1594 | |
| 1595 | // RX AFE control 1 |
| 1596 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; |
| 1597 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; |
| 1598 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; |
| 1599 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; |
| 1600 | |
| 1601 | // RX AFE control 1 |
| 1602 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; |
| 1603 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; |
| 1604 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; |
| 1605 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; |
| 1606 | |
| 1607 | // Tx AFE control 1 |
| 1608 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; |
| 1609 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; |
| 1610 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; |
| 1611 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; |
| 1612 | |
| 1613 | // Tx AFE control 2 |
| 1614 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; |
| 1615 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; |
| 1616 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; |
| 1617 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; |
| 1618 | |
| 1619 | // Tranceiver LSSI Readback SI mode |
| 1620 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; |
| 1621 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; |
| 1622 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; |
| 1623 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; |
| 1624 | |
| 1625 | // Tranceiver LSSI Readback PI mode |
| 1626 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; |
| 1627 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; |
| 1628 | //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; |
| 1629 | //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; |
| 1630 | |
| 1631 | } |
| 1632 | |
| 1633 | |
| 1634 | // |
| 1635 | // Description: Change RF power state. |
| 1636 | // |
| 1637 | // Assumption: This function must be executed in re-schdulable context, |
| 1638 | // ie. PASSIVE_LEVEL. |
| 1639 | // |
| 1640 | // 050823, by rcnjko. |
| 1641 | //not understand it seem's use in init |
| 1642 | //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler |
| 1643 | bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState) |
| 1644 | { |
| 1645 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1646 | bool bResult = FALSE; |
| 1647 | |
| 1648 | RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); |
| 1649 | |
| 1650 | if(eRFPowerState == priv->ieee80211->eRFPowerState) |
| 1651 | { |
| 1652 | RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); |
| 1653 | return bResult; |
| 1654 | } |
| 1655 | |
| 1656 | bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState); |
| 1657 | |
| 1658 | RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult); |
| 1659 | |
| 1660 | return bResult; |
| 1661 | } |
| 1662 | |
| 1663 | //use in phy only |
| 1664 | static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState) |
| 1665 | { |
| 1666 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1667 | bool bResult = TRUE; |
| 1668 | //u8 eRFPath; |
| 1669 | //u8 i, QueueID; |
| 1670 | u8 u1bTmp; |
| 1671 | |
| 1672 | if(priv->SetRFPowerStateInProgress == TRUE) |
| 1673 | return FALSE; |
| 1674 | |
| 1675 | priv->SetRFPowerStateInProgress = TRUE; |
| 1676 | |
| 1677 | switch(priv->rf_chip ) |
| 1678 | { |
| 1679 | default: |
| 1680 | switch( eRFPowerState ) |
| 1681 | { |
| 1682 | case eRfOn: |
| 1683 | write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE); |
| 1684 | write_nic_word(dev, CMDR, 0x37FC); |
| 1685 | write_nic_byte(dev, PHY_CCA, 0x3); |
| 1686 | write_nic_byte(dev, TXPAUSE, 0x00); |
| 1687 | write_nic_byte(dev, SPS1_CTRL, 0x64); |
| 1688 | break; |
| 1689 | |
| 1690 | // |
| 1691 | // In current solution, RFSleep=RFOff in order to save power under 802.11 power save. |
| 1692 | // By Bruce, 2008-01-16. |
| 1693 | // |
| 1694 | case eRfSleep: |
| 1695 | case eRfOff: |
| 1696 | if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff) |
| 1697 | break; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1698 | // |
| 1699 | //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon. |
| 1700 | // Added by Bruce, 2008-11-22. |
| 1701 | // |
| 1702 | //================================================================== |
| 1703 | // (0) Disable FW BB reset checking |
| 1704 | write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE); |
| 1705 | |
| 1706 | // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT) |
| 1707 | u1bTmp = read_nic_byte(dev, LDOV12D_CTRL); |
| 1708 | u1bTmp |= BIT0; |
| 1709 | write_nic_byte(dev, LDOV12D_CTRL, u1bTmp); |
| 1710 | |
| 1711 | write_nic_byte(dev, SPS1_CTRL, 0x0); |
| 1712 | write_nic_byte(dev, TXPAUSE, 0xFF); |
| 1713 | |
| 1714 | // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable |
| 1715 | write_nic_word(dev, CMDR, 0x77FC); |
| 1716 | write_nic_byte(dev, PHY_CCA, 0x0); |
| 1717 | udelay(100); |
| 1718 | |
| 1719 | write_nic_word(dev, CMDR, 0x37FC); |
| 1720 | udelay(10); |
| 1721 | |
| 1722 | write_nic_word(dev, CMDR, 0x77FC); |
| 1723 | udelay(10); |
| 1724 | |
| 1725 | // (3) Reset BB TRX blocks |
| 1726 | write_nic_word(dev, CMDR, 0x57FC); |
| 1727 | break; |
| 1728 | |
| 1729 | default: |
| 1730 | bResult = FALSE; |
| 1731 | //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState)); |
| 1732 | break; |
| 1733 | } |
| 1734 | break; |
| 1735 | |
| 1736 | } |
| 1737 | priv->ieee80211->eRFPowerState = eRFPowerState; |
| 1738 | #ifdef TO_DO_LIST |
| 1739 | if(bResult) |
| 1740 | { |
| 1741 | // Update current RF state variable. |
| 1742 | priv->ieee80211->eRFPowerState = eRFPowerState; |
| 1743 | |
| 1744 | switch(priv->rf_chip ) |
| 1745 | { |
| 1746 | case RF_8256: |
| 1747 | switch(priv->ieee80211->eRFPowerState) |
| 1748 | { |
| 1749 | case eRfOff: |
| 1750 | // |
| 1751 | //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 |
| 1752 | // |
| 1753 | if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS ) |
| 1754 | { |
| 1755 | dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK); |
| 1756 | } |
| 1757 | else |
| 1758 | { |
| 1759 | // Turn off LED if RF is not ON. |
| 1760 | dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF); |
| 1761 | } |
| 1762 | break; |
| 1763 | |
| 1764 | case eRfOn: |
| 1765 | // Turn on RF we are still linked, which might happen when |
| 1766 | // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. |
| 1767 | if( pMgntInfo->bMediaConnect == TRUE ) |
| 1768 | { |
| 1769 | dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK); |
| 1770 | } |
| 1771 | else |
| 1772 | { |
| 1773 | // Turn off LED if RF is not ON. |
| 1774 | dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK); |
| 1775 | } |
| 1776 | break; |
| 1777 | |
| 1778 | default: |
| 1779 | // do nothing. |
| 1780 | break; |
| 1781 | }// Switch RF state |
| 1782 | |
| 1783 | break; |
| 1784 | |
| 1785 | default: |
| 1786 | RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n"); |
| 1787 | break; |
| 1788 | }// Switch rf_chip |
| 1789 | } |
| 1790 | #endif |
| 1791 | priv->SetRFPowerStateInProgress = FALSE; |
| 1792 | |
| 1793 | return bResult; |
| 1794 | } |
| 1795 | |
| 1796 | /*----------------------------------------------------------------------------- |
| 1797 | * Function: GetTxPowerLevel8190() |
| 1798 | * |
| 1799 | * Overview: This function is export to "common" moudule |
| 1800 | * |
| 1801 | * Input: PADAPTER Adapter |
| 1802 | * psByte Power Level |
| 1803 | * |
| 1804 | * Output: NONE |
| 1805 | * |
| 1806 | * Return: NONE |
| 1807 | * |
| 1808 | *---------------------------------------------------------------------------*/ |
| 1809 | // no use temp |
| 1810 | void |
| 1811 | PHY_GetTxPowerLevel8192S( |
| 1812 | struct net_device* dev, |
| 1813 | long* powerlevel |
| 1814 | ) |
| 1815 | { |
| 1816 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1817 | u8 TxPwrLevel = 0; |
| 1818 | long TxPwrDbm; |
| 1819 | // |
| 1820 | // Because the Tx power indexes are different, we report the maximum of them to |
| 1821 | // meet the CCX TPC request. By Bruce, 2008-01-31. |
| 1822 | // |
| 1823 | |
| 1824 | // CCK |
| 1825 | TxPwrLevel = priv->CurrentCckTxPwrIdx; |
| 1826 | TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel); |
| 1827 | |
| 1828 | // Legacy OFDM |
| 1829 | TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff; |
| 1830 | |
| 1831 | // Compare with Legacy OFDM Tx power. |
| 1832 | if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm) |
| 1833 | TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel); |
| 1834 | |
| 1835 | // HT OFDM |
| 1836 | TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx; |
| 1837 | |
| 1838 | // Compare with HT OFDM Tx power. |
| 1839 | if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm) |
| 1840 | TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel); |
| 1841 | |
| 1842 | *powerlevel = TxPwrDbm; |
| 1843 | } |
| 1844 | |
| 1845 | /*----------------------------------------------------------------------------- |
| 1846 | * Function: SetTxPowerLevel8190() |
| 1847 | * |
| 1848 | * Overview: This function is export to "HalCommon" moudule |
| 1849 | * |
| 1850 | * Input: PADAPTER Adapter |
| 1851 | * u1Byte channel |
| 1852 | * |
| 1853 | * Output: NONE |
| 1854 | * |
| 1855 | * Return: NONE |
| 1856 | * 2008/11/04 MHC We remove EEPROM_93C56. |
| 1857 | * We need to move CCX relative code to independet file. |
| 1858 | * 2009/01/21 MHC Support new EEPROM format from SD3 requirement. |
| 1859 | *---------------------------------------------------------------------------*/ |
| 1860 | void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel) |
| 1861 | { |
| 1862 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1863 | //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(dev); |
| 1864 | u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10; |
| 1865 | s8 ant_pwr_diff = 0; |
| 1866 | u32 u4RegValue; |
| 1867 | u8 index = (channel -1); |
| 1868 | // 2009/01/22 MH Add for new EEPROM format from SD3 |
| 1869 | u8 pwrdiff[2] = {0}; |
| 1870 | u8 ht20pwr[2] = {0}, ht40pwr[2] = {0}; |
| 1871 | u8 rfpath = 0, rfpathnum = 2; |
| 1872 | |
| 1873 | if(priv->bTXPowerDataReadFromEEPORM == FALSE) |
| 1874 | return; |
| 1875 | |
| 1876 | // |
| 1877 | // Read predefined TX power index in EEPROM |
| 1878 | // |
| 1879 | // if(priv->epromtype == EPROM_93c46) |
| 1880 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1881 | // |
| 1882 | // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx |
| 1883 | // Power must be calculated by the antenna diff. |
| 1884 | // So we have to rewrite Antenna gain offset register here. |
| 1885 | // Please refer to BB register 0x80c |
| 1886 | // 1. For CCK. |
| 1887 | // 2. For OFDM 1T or 2T |
| 1888 | // |
| 1889 | |
| 1890 | // 1. CCK |
| 1891 | powerlevel = priv->RfTxPwrLevelCck[0][index]; |
| 1892 | |
| 1893 | if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R) |
| 1894 | { |
| 1895 | // Read HT 40 OFDM TX power |
| 1896 | powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index]; |
| 1897 | // RF B HT OFDM pwr-RFA HT OFDM pwr |
| 1898 | // Only one RF we need not to decide B <-> A pwr diff |
| 1899 | |
| 1900 | // Legacy<->HT pwr diff, we only care about path A. |
| 1901 | |
| 1902 | // We only assume 1T as RF path A |
| 1903 | rfpathnum = 1; |
| 1904 | ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index]; |
| 1905 | } |
| 1906 | else if (priv->rf_type == RF_2T2R) |
| 1907 | { |
| 1908 | // Read HT 40 OFDM TX power |
| 1909 | powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index]; |
| 1910 | // RF B HT OFDM pwr-RFA HT OFDM pwr |
| 1911 | ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] - |
| 1912 | priv->RfTxPwrLevelOfdm2T[0][index]; |
| 1913 | // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff) |
| 1914 | // We can not handle Path B&A HT/Legacy pwr diff for 92S now. |
| 1915 | |
| 1916 | //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n", |
| 1917 | //channel, priv->RfTxPwrLevelOfdm2T[0][index], |
| 1918 | //priv->RfTxPwrLevelOfdm2T[1][index], |
| 1919 | //priv->RfTxPwrLevelOfdm2T[0][index], |
| 1920 | //priv->RfTxPwrLevelOfdm2T[1][index])); |
| 1921 | |
| 1922 | ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index]; |
| 1923 | ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index]; |
| 1924 | } |
| 1925 | |
| 1926 | // |
| 1927 | // 2009/01/21 MH Support new EEPROM format from SD3 requirement |
| 1928 | // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff. |
| 1929 | // |
| 1930 | if (priv->EEPROMVersion == 2) // Defined by SD1 Jong |
| 1931 | { |
| 1932 | if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) |
| 1933 | { |
| 1934 | for (rfpath = 0; rfpath < rfpathnum; rfpath++) |
| 1935 | { |
| 1936 | // HT 20<->40 pwr diff |
| 1937 | pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index]; |
| 1938 | |
| 1939 | // Calculate Antenna pwr diff |
| 1940 | if (pwrdiff[rfpath] < 8) // 0~+7 |
| 1941 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1942 | ht20pwr[rfpath] += pwrdiff[rfpath]; |
| 1943 | } |
| 1944 | else // index8-15=-8~-1 |
| 1945 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1946 | ht20pwr[rfpath] -= (15-pwrdiff[rfpath]); |
| 1947 | } |
| 1948 | } |
| 1949 | |
| 1950 | // RF B HT OFDM pwr-RFA HT OFDM pwr |
| 1951 | if (priv->rf_type == RF_2T2R) |
| 1952 | ant_pwr_diff = ht20pwr[1] - ht20pwr[0]; |
| 1953 | |
| 1954 | //RTPRINT(FPHY, PHY_TXPWR, |
| 1955 | //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n", |
| 1956 | //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0])); |
| 1957 | } |
| 1958 | |
| 1959 | // Band Edge scheme is enabled for FCC mode |
| 1960 | if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) |
| 1961 | { |
| 1962 | for (rfpath = 0; rfpath < rfpathnum; rfpath++) |
| 1963 | { |
| 1964 | pwrdiff[rfpath] = 0; |
| 1965 | if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) |
| 1966 | { |
| 1967 | if (channel <= 3) |
| 1968 | pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0]; |
| 1969 | else if (channel >= 9) |
| 1970 | pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1]; |
| 1971 | else |
| 1972 | pwrdiff[rfpath] = 0; |
| 1973 | |
| 1974 | ht40pwr[rfpath] -= pwrdiff[rfpath]; |
| 1975 | } |
| 1976 | else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) |
| 1977 | { |
| 1978 | if (channel == 1) |
| 1979 | pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0]; |
| 1980 | else if (channel >= 11) |
| 1981 | pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1]; |
| 1982 | else |
| 1983 | pwrdiff[rfpath] = 0; |
| 1984 | |
| 1985 | ht20pwr[rfpath] -= pwrdiff[rfpath]; |
| 1986 | } |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 1987 | } |
| 1988 | |
| 1989 | if (priv->rf_type == RF_2T2R) |
| 1990 | { |
| 1991 | // HT 20/40 must decide if they need to minus BD pwr offset |
| 1992 | if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) |
| 1993 | ant_pwr_diff = ht40pwr[1] - ht40pwr[0]; |
| 1994 | else |
| 1995 | ant_pwr_diff = ht20pwr[1] - ht20pwr[0]; |
| 1996 | } |
| 1997 | if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) |
| 1998 | { |
| 1999 | if (channel <= 1 || channel >= 11) |
| 2000 | { |
| 2001 | //RTPRINT(FPHY, PHY_TXPWR, |
| 2002 | //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n", |
| 2003 | //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0])); |
| 2004 | } |
| 2005 | } |
| 2006 | else |
| 2007 | { |
| 2008 | if (channel <= 3 || channel >= 9) |
| 2009 | { |
| 2010 | //RTPRINT(FPHY, PHY_TXPWR, |
| 2011 | //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n", |
| 2012 | //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0])); |
| 2013 | } |
| 2014 | } |
| 2015 | } |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2016 | } |
| 2017 | |
| 2018 | //Cosa added for protection, the reg rFPGA0_TxGainStage |
| 2019 | // range is from 7~-8, index = 0x0~0xf |
| 2020 | if(ant_pwr_diff > 7) |
| 2021 | ant_pwr_diff = 7; |
| 2022 | if(ant_pwr_diff < -8) |
| 2023 | ant_pwr_diff = -8; |
| 2024 | |
| 2025 | //RTPRINT(FPHY, PHY_TXPWR, |
| 2026 | //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n", |
| 2027 | //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff)); |
| 2028 | |
| 2029 | ant_pwr_diff &= 0xf; |
| 2030 | |
| 2031 | // Antenna TX power difference |
| 2032 | priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care |
| 2033 | priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care |
| 2034 | priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); // RF-B |
| 2035 | |
| 2036 | // Antenna gain offset from B/C/D to A |
| 2037 | u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 | |
| 2038 | priv->AntennaTxPwDiff[1]<<4 | |
| 2039 | priv->AntennaTxPwDiff[0] ); |
| 2040 | |
| 2041 | // Notify Tx power difference for B/C/D to A!!! |
| 2042 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2043 | } |
| 2044 | |
| 2045 | // |
| 2046 | // CCX 2 S31, AP control of client transmit power: |
| 2047 | // 1. We shall not exceed Cell Power Limit as possible as we can. |
| 2048 | // 2. Tolerance is +/- 5dB. |
| 2049 | // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. |
| 2050 | // |
| 2051 | // TODO: |
| 2052 | // 1. 802.11h power contraint |
| 2053 | // |
| 2054 | // 071011, by rcnjko. |
| 2055 | // |
| 2056 | #ifdef TODO //WB, 11h has not implemented now. |
| 2057 | if( priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr && |
| 2058 | channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc ) |
| 2059 | { |
| 2060 | u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr); |
| 2061 | u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr); |
| 2062 | u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr); |
| 2063 | |
| 2064 | RT_TRACE(COMP_TXAGC, |
| 2065 | ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", |
| 2066 | priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx)); |
| 2067 | RT_TRACE(COMP_TXAGC, |
| 2068 | ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", |
| 2069 | channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G)); |
| 2070 | |
| 2071 | // CCK |
| 2072 | if(powerlevel > CckCellPwrIdx) |
| 2073 | powerlevel = CckCellPwrIdx; |
| 2074 | // Legacy OFDM, HT OFDM |
| 2075 | if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx) |
| 2076 | { |
| 2077 | if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0) |
| 2078 | { |
| 2079 | powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff; |
| 2080 | } |
| 2081 | else |
| 2082 | { |
| 2083 | powerlevelOFDM24G = 0; |
| 2084 | } |
| 2085 | } |
| 2086 | |
| 2087 | RT_TRACE(COMP_TXAGC, |
| 2088 | ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", |
| 2089 | powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G)); |
| 2090 | } |
| 2091 | #endif |
| 2092 | |
| 2093 | priv->CurrentCckTxPwrIdx = powerlevel; |
| 2094 | priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G; |
| 2095 | |
| 2096 | switch(priv->rf_chip) |
| 2097 | { |
| 2098 | case RF_8225: |
| 2099 | //PHY_SetRF8225CckTxPower(dev, powerlevel); |
| 2100 | //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G); |
| 2101 | break; |
| 2102 | |
| 2103 | case RF_8256: |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2104 | break; |
| 2105 | |
| 2106 | case RF_6052: |
| 2107 | PHY_RF6052SetCckTxPower(dev, powerlevel); |
| 2108 | PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G); |
| 2109 | break; |
| 2110 | |
| 2111 | case RF_8258: |
| 2112 | break; |
| 2113 | default: |
| 2114 | break; |
| 2115 | } |
| 2116 | |
| 2117 | } |
| 2118 | |
| 2119 | // |
| 2120 | // Description: |
| 2121 | // Update transmit power level of all channel supported. |
| 2122 | // |
| 2123 | // TODO: |
| 2124 | // A mode. |
| 2125 | // By Bruce, 2008-02-04. |
| 2126 | // no use temp |
| 2127 | bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm) |
| 2128 | { |
| 2129 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2130 | u8 idx; |
| 2131 | u8 rf_path; |
| 2132 | |
| 2133 | // TODO: A mode Tx power. |
| 2134 | u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm); |
| 2135 | u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm); |
| 2136 | |
| 2137 | if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0) |
| 2138 | OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff; |
| 2139 | else |
| 2140 | OfdmTxPwrIdx = 0; |
| 2141 | |
| 2142 | for(idx = 0; idx < 14; idx++) |
| 2143 | { |
| 2144 | priv->TxPowerLevelCCK[idx] = CckTxPwrIdx; |
| 2145 | priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx; |
| 2146 | priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx; |
| 2147 | priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx; |
| 2148 | priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx; |
| 2149 | priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx; |
| 2150 | |
| 2151 | for (rf_path = 0; rf_path < 2; rf_path++) |
| 2152 | { |
| 2153 | priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx; |
| 2154 | priv->RfTxPwrLevelOfdm1T[rf_path][idx] = \ |
| 2155 | priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx; |
| 2156 | } |
| 2157 | } |
| 2158 | |
| 2159 | PHY_SetTxPowerLevel8192S(dev, priv->chan); |
| 2160 | |
| 2161 | return TRUE; |
| 2162 | } |
| 2163 | |
| 2164 | /* |
| 2165 | Description: |
| 2166 | When beacon interval is changed, the values of the |
| 2167 | hw registers should be modified. |
| 2168 | By tynli, 2008.10.24. |
| 2169 | |
| 2170 | */ |
| 2171 | |
| 2172 | extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval) |
| 2173 | { |
| 2174 | u32 NewBeaconNum; |
| 2175 | |
| 2176 | NewBeaconNum = BeaconInterval *32 - 64; |
| 2177 | //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum); |
| 2178 | //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C); |
| 2179 | write_nic_dword(dev, WFM3+4, NewBeaconNum); |
| 2180 | write_nic_dword(dev, WFM3, 0xB026007C); |
| 2181 | } |
| 2182 | |
| 2183 | // |
| 2184 | // Description: |
| 2185 | // Map dBm into Tx power index according to |
| 2186 | // current HW model, for example, RF and PA, and |
| 2187 | // current wireless mode. |
| 2188 | // By Bruce, 2008-01-29. |
| 2189 | // use in phy only |
| 2190 | static u8 phy_DbmToTxPwrIdx( |
| 2191 | struct net_device* dev, |
| 2192 | WIRELESS_MODE WirelessMode, |
| 2193 | long PowerInDbm |
| 2194 | ) |
| 2195 | { |
| 2196 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 2197 | u8 TxPwrIdx = 0; |
| 2198 | long Offset = 0; |
| 2199 | |
| 2200 | |
| 2201 | // |
| 2202 | // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to |
| 2203 | // 3dbm, and OFDM HT equals to 0dbm repectively. |
| 2204 | // Note: |
| 2205 | // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. |
| 2206 | // By Bruce, 2008-01-29. |
| 2207 | // |
| 2208 | switch(WirelessMode) |
| 2209 | { |
| 2210 | case WIRELESS_MODE_B: |
| 2211 | Offset = -7; |
| 2212 | break; |
| 2213 | |
| 2214 | case WIRELESS_MODE_G: |
| 2215 | case WIRELESS_MODE_N_24G: |
| 2216 | Offset = -8; |
| 2217 | break; |
| 2218 | default: |
| 2219 | break; |
| 2220 | } |
| 2221 | |
| 2222 | if((PowerInDbm - Offset) > 0) |
| 2223 | { |
| 2224 | TxPwrIdx = (u8)((PowerInDbm - Offset) * 2); |
| 2225 | } |
| 2226 | else |
| 2227 | { |
| 2228 | TxPwrIdx = 0; |
| 2229 | } |
| 2230 | |
| 2231 | // Tx Power Index is too large. |
| 2232 | if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S) |
| 2233 | TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S; |
| 2234 | |
| 2235 | return TxPwrIdx; |
| 2236 | } |
| 2237 | // |
| 2238 | // Description: |
| 2239 | // Map Tx power index into dBm according to |
| 2240 | // current HW model, for example, RF and PA, and |
| 2241 | // current wireless mode. |
| 2242 | // By Bruce, 2008-01-29. |
| 2243 | // use in phy only |
| 2244 | static long phy_TxPwrIdxToDbm( |
| 2245 | struct net_device* dev, |
| 2246 | WIRELESS_MODE WirelessMode, |
| 2247 | u8 TxPwrIdx |
| 2248 | ) |
| 2249 | { |
| 2250 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 2251 | long Offset = 0; |
| 2252 | long PwrOutDbm = 0; |
| 2253 | |
| 2254 | // |
| 2255 | // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to |
| 2256 | // 3dbm, and OFDM HT equals to 0dbm repectively. |
| 2257 | // Note: |
| 2258 | // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. |
| 2259 | // By Bruce, 2008-01-29. |
| 2260 | // |
| 2261 | switch(WirelessMode) |
| 2262 | { |
| 2263 | case WIRELESS_MODE_B: |
| 2264 | Offset = -7; |
| 2265 | break; |
| 2266 | |
| 2267 | case WIRELESS_MODE_G: |
| 2268 | case WIRELESS_MODE_N_24G: |
| 2269 | Offset = -8; |
| 2270 | break; |
| 2271 | default: |
| 2272 | break; |
| 2273 | } |
| 2274 | |
| 2275 | PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part. |
| 2276 | |
| 2277 | return PwrOutDbm; |
| 2278 | } |
| 2279 | |
| 2280 | #ifdef TO_DO_LIST |
| 2281 | extern VOID |
| 2282 | PHY_ScanOperationBackup8192S( |
| 2283 | IN PADAPTER Adapter, |
| 2284 | IN u1Byte Operation |
| 2285 | ) |
| 2286 | { |
| 2287 | |
| 2288 | HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); |
| 2289 | PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); |
| 2290 | u4Byte BitMask; |
| 2291 | u1Byte initial_gain; |
| 2292 | |
| 2293 | |
| 2294 | |
| 2295 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2296 | |
| 2297 | if(!Adapter->bDriverStopped) |
| 2298 | { |
| 2299 | switch(Operation) |
| 2300 | { |
| 2301 | case SCAN_OPT_BACKUP: |
| 2302 | // |
| 2303 | // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here |
| 2304 | // and resume both two DMs while scan complete. |
| 2305 | // 2008.11.27. |
| 2306 | // |
| 2307 | Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN); |
| 2308 | break; |
| 2309 | |
| 2310 | case SCAN_OPT_RESTORE: |
| 2311 | // |
| 2312 | // <Roger_Notes> We resume DIG and enable high power both two DMs here and |
| 2313 | // recover earlier DIG settings. |
| 2314 | // 2008.11.27. |
| 2315 | // |
| 2316 | Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN); |
| 2317 | break; |
| 2318 | |
| 2319 | default: |
| 2320 | RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n")); |
| 2321 | break; |
| 2322 | } |
| 2323 | } |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2324 | } |
| 2325 | #endif |
| 2326 | |
| 2327 | //nouse temp |
| 2328 | void PHY_InitialGain8192S(struct net_device* dev,u8 Operation ) |
| 2329 | { |
| 2330 | |
| 2331 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 2332 | //u32 BitMask; |
| 2333 | //u8 initial_gain; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2334 | } |
| 2335 | |
| 2336 | /*----------------------------------------------------------------------------- |
| 2337 | * Function: SetBWModeCallback8190Pci() |
| 2338 | * |
| 2339 | * Overview: Timer callback function for SetSetBWMode |
| 2340 | * |
| 2341 | * Input: PRT_TIMER pTimer |
| 2342 | * |
| 2343 | * Output: NONE |
| 2344 | * |
| 2345 | * Return: NONE |
| 2346 | * |
| 2347 | * Note: (1) We do not take j mode into consideration now |
| 2348 | * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run |
| 2349 | * concurrently? |
| 2350 | *---------------------------------------------------------------------------*/ |
| 2351 | // use in phy only (in win it's timer) |
| 2352 | void PHY_SetBWModeCallback8192S(struct net_device *dev) |
| 2353 | { |
| 2354 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2355 | u8 regBwOpMode; |
| 2356 | |
| 2357 | //return; |
| 2358 | |
| 2359 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 2360 | //u32 NowL, NowH; |
| 2361 | //u8Byte BeginTime, EndTime; |
| 2362 | u8 regRRSR_RSC; |
| 2363 | |
| 2364 | RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \ |
| 2365 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); |
| 2366 | |
| 2367 | if(priv->rf_chip == RF_PSEUDO_11N) |
| 2368 | { |
| 2369 | priv->SetBWModeInProgress= FALSE; |
| 2370 | return; |
| 2371 | } |
| 2372 | |
| 2373 | if(!priv->up) |
| 2374 | return; |
| 2375 | |
| 2376 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 2377 | //NowL = read_nic_dword(dev, TSFR); |
| 2378 | //NowH = read_nic_dword(dev, TSFR+4); |
| 2379 | //BeginTime = ((u8Byte)NowH << 32) + NowL; |
| 2380 | |
| 2381 | //3// |
| 2382 | //3//<1>Set MAC register |
| 2383 | //3// |
| 2384 | regBwOpMode = read_nic_byte(dev, BW_OPMODE); |
| 2385 | regRRSR_RSC = read_nic_byte(dev, RRSR+2); |
| 2386 | |
| 2387 | switch(priv->CurrentChannelBW) |
| 2388 | { |
| 2389 | case HT_CHANNEL_WIDTH_20: |
| 2390 | //if(priv->card_8192_version >= VERSION_8192S_BCUT) |
| 2391 | // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58); |
| 2392 | |
| 2393 | regBwOpMode |= BW_OPMODE_20MHZ; |
| 2394 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works |
| 2395 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 2396 | break; |
| 2397 | |
| 2398 | case HT_CHANNEL_WIDTH_20_40: |
| 2399 | //if(priv->card_8192_version >= VERSION_8192S_BCUT) |
| 2400 | // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18); |
| 2401 | |
| 2402 | regBwOpMode &= ~BW_OPMODE_20MHZ; |
| 2403 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works |
| 2404 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 2405 | regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5); |
| 2406 | write_nic_byte(dev, RRSR+2, regRRSR_RSC); |
| 2407 | break; |
| 2408 | |
| 2409 | default: |
| 2410 | RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\ |
| 2411 | unknown Bandwidth: %#X\n",priv->CurrentChannelBW); |
| 2412 | break; |
| 2413 | } |
| 2414 | |
| 2415 | //3// |
| 2416 | //3//<2>Set PHY related register |
| 2417 | //3// |
| 2418 | switch(priv->CurrentChannelBW) |
| 2419 | { |
| 2420 | /* 20 MHz channel*/ |
| 2421 | case HT_CHANNEL_WIDTH_20: |
| 2422 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); |
| 2423 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); |
| 2424 | |
| 2425 | // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 |
| 2426 | // It is set in Tx descriptor for 8192x series |
| 2427 | //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); |
| 2428 | //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); |
| 2429 | //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2430 | |
| 2431 | if (priv->card_8192_version >= VERSION_8192S_BCUT) |
| 2432 | write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58); |
| 2433 | |
| 2434 | |
| 2435 | break; |
| 2436 | |
| 2437 | /* 40 MHz channel*/ |
| 2438 | case HT_CHANNEL_WIDTH_20_40: |
| 2439 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); |
| 2440 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); |
| 2441 | |
| 2442 | // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 |
| 2443 | //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); |
| 2444 | //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); |
| 2445 | //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2446 | |
| 2447 | // Set Control channel to upper or lower. These settings are required only for 40MHz |
| 2448 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); |
| 2449 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); |
| 2450 | |
| 2451 | //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3); |
| 2452 | if (priv->card_8192_version >= VERSION_8192S_BCUT) |
| 2453 | write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18); |
| 2454 | |
| 2455 | break; |
| 2456 | |
| 2457 | default: |
| 2458 | RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\ |
| 2459 | ,priv->CurrentChannelBW); |
| 2460 | break; |
| 2461 | |
| 2462 | } |
| 2463 | //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 |
| 2464 | |
| 2465 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 2466 | //NowL = read_nic_dword(dev, TSFR); |
| 2467 | //NowH = read_nic_dword(dev, TSFR+4); |
| 2468 | //EndTime = ((u8Byte)NowH << 32) + NowL; |
| 2469 | //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); |
| 2470 | |
| 2471 | //3<3>Set RF related register |
| 2472 | switch( priv->rf_chip ) |
| 2473 | { |
| 2474 | case RF_8225: |
| 2475 | //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW); |
| 2476 | break; |
| 2477 | |
| 2478 | case RF_8256: |
| 2479 | // Please implement this function in Hal8190PciPhy8256.c |
| 2480 | //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); |
| 2481 | break; |
| 2482 | |
| 2483 | case RF_8258: |
| 2484 | // Please implement this function in Hal8190PciPhy8258.c |
| 2485 | // PHY_SetRF8258Bandwidth(); |
| 2486 | break; |
| 2487 | |
| 2488 | case RF_PSEUDO_11N: |
| 2489 | // Do Nothing |
| 2490 | break; |
| 2491 | |
| 2492 | case RF_6052: |
| 2493 | PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW); |
| 2494 | break; |
| 2495 | default: |
| 2496 | printk("Unknown rf_chip: %d\n", priv->rf_chip); |
| 2497 | break; |
| 2498 | } |
| 2499 | |
| 2500 | priv->SetBWModeInProgress= FALSE; |
| 2501 | |
| 2502 | RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" ); |
| 2503 | } |
| 2504 | |
| 2505 | |
| 2506 | /*----------------------------------------------------------------------------- |
| 2507 | * Function: SetBWMode8190Pci() |
| 2508 | * |
| 2509 | * Overview: This function is export to "HalCommon" moudule |
| 2510 | * |
| 2511 | * Input: PADAPTER Adapter |
| 2512 | * HT_CHANNEL_WIDTH Bandwidth //20M or 40M |
| 2513 | * |
| 2514 | * Output: NONE |
| 2515 | * |
| 2516 | * Return: NONE |
| 2517 | * |
| 2518 | * Note: We do not take j mode into consideration now |
| 2519 | *---------------------------------------------------------------------------*/ |
| 2520 | //extern void PHY_SetBWMode8192S( struct net_device* dev, |
| 2521 | // HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M |
| 2522 | // HT_EXTCHNL_OFFSET Offset // Upper, Lower, or Don't care |
| 2523 | void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) |
| 2524 | { |
| 2525 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2526 | HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW; |
| 2527 | |
| 2528 | |
| 2529 | // Modified it for 20/40 mhz switch by guangan 070531 |
| 2530 | |
| 2531 | //return; |
| 2532 | |
| 2533 | //if(priv->SwChnlInProgress) |
| 2534 | // if(pMgntInfo->bScanInProgress) |
| 2535 | // { |
| 2536 | // RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n", |
| 2537 | // Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); |
| 2538 | // return; |
| 2539 | // } |
| 2540 | |
| 2541 | // if(priv->SetBWModeInProgress) |
| 2542 | // { |
| 2543 | // // Modified it for 20/40 mhz switch by guangan 070531 |
| 2544 | // RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n", |
| 2545 | // Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); |
| 2546 | // PlatformCancelTimer(dev, &priv->SetBWModeTimer); |
| 2547 | // //return; |
| 2548 | // } |
| 2549 | |
| 2550 | if(priv->SetBWModeInProgress) |
| 2551 | return; |
| 2552 | |
| 2553 | priv->SetBWModeInProgress= TRUE; |
| 2554 | |
| 2555 | priv->CurrentChannelBW = Bandwidth; |
| 2556 | |
| 2557 | if(Offset==HT_EXTCHNL_OFFSET_LOWER) |
| 2558 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; |
| 2559 | else if(Offset==HT_EXTCHNL_OFFSET_UPPER) |
| 2560 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; |
| 2561 | else |
| 2562 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; |
| 2563 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2564 | if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) ) |
| 2565 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2566 | SetBWModeCallback8192SUsbWorkItem(dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2567 | } |
| 2568 | else |
| 2569 | { |
| 2570 | RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n"); |
| 2571 | priv->SetBWModeInProgress= FALSE; |
| 2572 | priv->CurrentChannelBW = tmpBW; |
| 2573 | } |
| 2574 | } |
| 2575 | |
| 2576 | // use in phy only (in win it's timer) |
| 2577 | void PHY_SwChnlCallback8192S(struct net_device *dev) |
| 2578 | { |
| 2579 | |
| 2580 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2581 | u32 delay; |
| 2582 | //bool ret; |
| 2583 | |
| 2584 | RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan); |
| 2585 | |
| 2586 | if(!priv->up) |
| 2587 | return; |
| 2588 | |
| 2589 | if(priv->rf_chip == RF_PSEUDO_11N) |
| 2590 | { |
| 2591 | priv->SwChnlInProgress=FALSE; |
| 2592 | return; //return immediately if it is peudo-phy |
| 2593 | } |
| 2594 | |
| 2595 | do{ |
| 2596 | if(!priv->SwChnlInProgress) |
| 2597 | break; |
| 2598 | |
| 2599 | //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) |
| 2600 | if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) |
| 2601 | { |
| 2602 | if(delay>0) |
| 2603 | { |
| 2604 | mdelay(delay); |
| 2605 | //PlatformSetTimer(dev, &priv->SwChnlTimer, delay); |
| 2606 | //mod_timer(&priv->SwChnlTimer, jiffies + MSECS(delay)); |
| 2607 | //==>PHY_SwChnlCallback8192S(dev); for 92se |
| 2608 | //==>SwChnlCallback8192SUsb(dev) for 92su |
| 2609 | } |
| 2610 | else |
| 2611 | continue; |
| 2612 | } |
| 2613 | else |
| 2614 | { |
| 2615 | priv->SwChnlInProgress=FALSE; |
| 2616 | break; |
| 2617 | } |
| 2618 | }while(true); |
| 2619 | } |
| 2620 | |
| 2621 | // Call after initialization |
| 2622 | //extern void PHY_SwChnl8192S(struct net_device* dev, u8 channel) |
| 2623 | u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) |
| 2624 | { |
| 2625 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2626 | //u8 tmpchannel =channel; |
| 2627 | //bool bResult = false; |
| 2628 | |
| 2629 | if(!priv->up) |
| 2630 | return false; |
| 2631 | |
| 2632 | if(priv->SwChnlInProgress) |
| 2633 | return false; |
| 2634 | |
| 2635 | if(priv->SetBWModeInProgress) |
| 2636 | return false; |
| 2637 | |
| 2638 | //-------------------------------------------- |
| 2639 | switch(priv->ieee80211->mode) |
| 2640 | { |
| 2641 | case WIRELESS_MODE_A: |
| 2642 | case WIRELESS_MODE_N_5G: |
| 2643 | if (channel<=14){ |
| 2644 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); |
| 2645 | return false; |
| 2646 | } |
| 2647 | break; |
| 2648 | |
| 2649 | case WIRELESS_MODE_B: |
| 2650 | if (channel>14){ |
| 2651 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); |
| 2652 | return false; |
| 2653 | } |
| 2654 | break; |
| 2655 | |
| 2656 | case WIRELESS_MODE_G: |
| 2657 | case WIRELESS_MODE_N_24G: |
| 2658 | if (channel>14){ |
| 2659 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); |
| 2660 | return false; |
| 2661 | } |
| 2662 | break; |
| 2663 | |
| 2664 | default: |
| 2665 | ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode); |
| 2666 | break; |
| 2667 | } |
| 2668 | //-------------------------------------------- |
| 2669 | |
| 2670 | priv->SwChnlInProgress = TRUE; |
| 2671 | if( channel == 0) |
| 2672 | channel = 1; |
| 2673 | |
| 2674 | priv->chan=channel; |
| 2675 | |
| 2676 | priv->SwChnlStage=0; |
| 2677 | priv->SwChnlStep=0; |
| 2678 | |
| 2679 | if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower)) |
| 2680 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2681 | SwChnlCallback8192SUsbWorkItem(dev); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2682 | #ifdef TO_DO_LIST |
| 2683 | if(bResult) |
| 2684 | { |
| 2685 | RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n"); |
| 2686 | } |
| 2687 | else |
| 2688 | { |
| 2689 | RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n"); |
| 2690 | priv->SwChnlInProgress = false; |
| 2691 | priv->CurrentChannel = tmpchannel; |
| 2692 | } |
| 2693 | #endif |
| 2694 | } |
| 2695 | else |
| 2696 | { |
| 2697 | RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n"); |
| 2698 | priv->SwChnlInProgress = false; |
| 2699 | //priv->CurrentChannel = tmpchannel; |
| 2700 | } |
| 2701 | return true; |
| 2702 | } |
| 2703 | |
| 2704 | |
| 2705 | // |
| 2706 | // Description: |
| 2707 | // Switch channel synchronously. Called by SwChnlByDelayHandler. |
| 2708 | // |
| 2709 | // Implemented by Bruce, 2008-02-14. |
| 2710 | // The following procedure is operted according to SwChanlCallback8190Pci(). |
| 2711 | // However, this procedure is performed synchronously which should be running under |
| 2712 | // passive level. |
| 2713 | // |
| 2714 | //not understant it |
| 2715 | void PHY_SwChnlPhy8192S( // Only called during initialize |
| 2716 | struct net_device* dev, |
| 2717 | u8 channel |
| 2718 | ) |
| 2719 | { |
| 2720 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2721 | |
| 2722 | RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan); |
| 2723 | |
| 2724 | #ifdef TO_DO_LIST |
| 2725 | // Cannot IO. |
| 2726 | if(RT_CANNOT_IO(dev)) |
| 2727 | return; |
| 2728 | #endif |
| 2729 | |
| 2730 | // Channel Switching is in progress. |
| 2731 | if(priv->SwChnlInProgress) |
| 2732 | return; |
| 2733 | |
| 2734 | //return immediately if it is peudo-phy |
| 2735 | if(priv->rf_chip == RF_PSEUDO_11N) |
| 2736 | { |
| 2737 | priv->SwChnlInProgress=FALSE; |
| 2738 | return; |
| 2739 | } |
| 2740 | |
| 2741 | priv->SwChnlInProgress = TRUE; |
| 2742 | if( channel == 0) |
| 2743 | channel = 1; |
| 2744 | |
| 2745 | priv->chan=channel; |
| 2746 | |
| 2747 | priv->SwChnlStage = 0; |
| 2748 | priv->SwChnlStep = 0; |
| 2749 | |
| 2750 | phy_FinishSwChnlNow(dev,channel); |
| 2751 | |
| 2752 | priv->SwChnlInProgress = FALSE; |
| 2753 | } |
| 2754 | |
| 2755 | // use in phy only |
| 2756 | static bool |
| 2757 | phy_SetSwChnlCmdArray( |
| 2758 | SwChnlCmd* CmdTable, |
| 2759 | u32 CmdTableIdx, |
| 2760 | u32 CmdTableSz, |
| 2761 | SwChnlCmdID CmdID, |
| 2762 | u32 Para1, |
| 2763 | u32 Para2, |
| 2764 | u32 msDelay |
| 2765 | ) |
| 2766 | { |
| 2767 | SwChnlCmd* pCmd; |
| 2768 | |
| 2769 | if(CmdTable == NULL) |
| 2770 | { |
| 2771 | //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); |
| 2772 | return FALSE; |
| 2773 | } |
| 2774 | if(CmdTableIdx >= CmdTableSz) |
| 2775 | { |
| 2776 | //RT_ASSERT(FALSE, |
| 2777 | // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", |
| 2778 | //CmdTableIdx, CmdTableSz)); |
| 2779 | return FALSE; |
| 2780 | } |
| 2781 | |
| 2782 | pCmd = CmdTable + CmdTableIdx; |
| 2783 | pCmd->CmdID = CmdID; |
| 2784 | pCmd->Para1 = Para1; |
| 2785 | pCmd->Para2 = Para2; |
| 2786 | pCmd->msDelay = msDelay; |
| 2787 | |
| 2788 | return TRUE; |
| 2789 | } |
| 2790 | |
| 2791 | // use in phy only |
| 2792 | static bool |
| 2793 | phy_SwChnlStepByStep( |
| 2794 | struct net_device* dev, |
| 2795 | u8 channel, |
| 2796 | u8 *stage, |
| 2797 | u8 *step, |
| 2798 | u32 *delay |
| 2799 | ) |
| 2800 | { |
| 2801 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2802 | //PCHANNEL_ACCESS_SETTING pChnlAccessSetting; |
| 2803 | SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; |
| 2804 | u32 PreCommonCmdCnt; |
| 2805 | SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; |
| 2806 | u32 PostCommonCmdCnt; |
| 2807 | SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; |
| 2808 | u32 RfDependCmdCnt; |
| 2809 | SwChnlCmd *CurrentCmd = NULL; |
| 2810 | u8 eRFPath; |
| 2811 | |
| 2812 | //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n")); |
| 2813 | //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel)); |
| 2814 | RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step); |
| 2815 | //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n")); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2816 | if (!IsLegalChannel(priv->ieee80211, channel)) |
| 2817 | { |
| 2818 | RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); |
| 2819 | return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. |
| 2820 | } |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2821 | |
| 2822 | //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting; |
| 2823 | //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n")); |
| 2824 | |
| 2825 | //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) |
| 2826 | //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) |
| 2827 | //{ |
| 2828 | // <1> Fill up pre common command. |
| 2829 | PreCommonCmdCnt = 0; |
| 2830 | phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, |
| 2831 | CmdID_SetTxPowerLevel, 0, 0, 0); |
| 2832 | phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, |
| 2833 | CmdID_End, 0, 0, 0); |
| 2834 | |
| 2835 | // <2> Fill up post common command. |
| 2836 | PostCommonCmdCnt = 0; |
| 2837 | |
| 2838 | phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, |
| 2839 | CmdID_End, 0, 0, 0); |
| 2840 | |
| 2841 | // <3> Fill up RF dependent command. |
| 2842 | RfDependCmdCnt = 0; |
| 2843 | switch( priv->rf_chip ) |
| 2844 | { |
| 2845 | case RF_8225: |
| 2846 | if (channel < 1 || channel > 14) |
| 2847 | RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel); |
| 2848 | //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); |
| 2849 | // 2008/09/04 MH Change channel. |
| 2850 | phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 2851 | CmdID_RF_WriteReg, rRfChannel, channel, 10); |
| 2852 | phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 2853 | CmdID_End, 0, 0, 0); |
| 2854 | break; |
| 2855 | |
| 2856 | case RF_8256: |
| 2857 | if (channel < 1 || channel > 14) |
| 2858 | RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel); |
| 2859 | // TEST!! This is not the table for 8256!! |
| 2860 | //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); |
| 2861 | phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 2862 | CmdID_RF_WriteReg, rRfChannel, channel, 10); |
| 2863 | phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 2864 | CmdID_End, 0, 0, 0); |
| 2865 | break; |
| 2866 | |
| 2867 | case RF_6052: |
| 2868 | if (channel < 1 || channel > 14) |
| 2869 | RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel); |
| 2870 | phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 2871 | CmdID_RF_WriteReg, RF_CHNLBW, channel, 10); |
| 2872 | phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 2873 | CmdID_End, 0, 0, 0); |
| 2874 | break; |
| 2875 | |
| 2876 | case RF_8258: |
| 2877 | break; |
| 2878 | |
| 2879 | default: |
| 2880 | //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip)); |
| 2881 | return FALSE; |
| 2882 | break; |
| 2883 | } |
| 2884 | |
| 2885 | |
| 2886 | do{ |
| 2887 | switch(*stage) |
| 2888 | { |
| 2889 | case 0: |
| 2890 | CurrentCmd=&PreCommonCmd[*step]; |
| 2891 | break; |
| 2892 | case 1: |
| 2893 | CurrentCmd=&RfDependCmd[*step]; |
| 2894 | break; |
| 2895 | case 2: |
| 2896 | CurrentCmd=&PostCommonCmd[*step]; |
| 2897 | break; |
| 2898 | } |
| 2899 | |
| 2900 | if(CurrentCmd->CmdID==CmdID_End) |
| 2901 | { |
| 2902 | if((*stage)==2) |
| 2903 | { |
| 2904 | return TRUE; |
| 2905 | } |
| 2906 | else |
| 2907 | { |
| 2908 | (*stage)++; |
| 2909 | (*step)=0; |
| 2910 | continue; |
| 2911 | } |
| 2912 | } |
| 2913 | |
| 2914 | switch(CurrentCmd->CmdID) |
| 2915 | { |
| 2916 | case CmdID_SetTxPowerLevel: |
| 2917 | //if(priv->card_8192_version > VERSION_8190_BD) |
| 2918 | PHY_SetTxPowerLevel8192S(dev,channel); |
| 2919 | break; |
| 2920 | case CmdID_WritePortUlong: |
| 2921 | write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); |
| 2922 | break; |
| 2923 | case CmdID_WritePortUshort: |
| 2924 | write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); |
| 2925 | break; |
| 2926 | case CmdID_WritePortUchar: |
| 2927 | write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); |
| 2928 | break; |
| 2929 | case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!! |
| 2930 | for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) |
| 2931 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2932 | // For new T65 RF 0222d register 0x18 bit 0-9 = channel number. |
| 2933 | rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2)); |
| 2934 | //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f)); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 2935 | } |
| 2936 | break; |
| 2937 | default: |
| 2938 | break; |
| 2939 | } |
| 2940 | |
| 2941 | break; |
| 2942 | }while(TRUE); |
| 2943 | //cosa }/*for(Number of RF paths)*/ |
| 2944 | |
| 2945 | (*delay)=CurrentCmd->msDelay; |
| 2946 | (*step)++; |
| 2947 | RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step); |
| 2948 | return FALSE; |
| 2949 | } |
| 2950 | |
| 2951 | //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem |
| 2952 | // use in phy only |
| 2953 | static void |
| 2954 | phy_FinishSwChnlNow( // We should not call this function directly |
| 2955 | struct net_device* dev, |
| 2956 | u8 channel |
| 2957 | ) |
| 2958 | { |
| 2959 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 2960 | u32 delay; |
| 2961 | |
| 2962 | while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) |
| 2963 | { |
| 2964 | if(delay>0) |
| 2965 | mdelay(delay); |
| 2966 | if(!priv->up) |
| 2967 | break; |
| 2968 | } |
| 2969 | } |
| 2970 | |
| 2971 | |
| 2972 | /*----------------------------------------------------------------------------- |
| 2973 | * Function: PHYCheckIsLegalRfPath8190Pci() |
| 2974 | * |
| 2975 | * Overview: Check different RF type to execute legal judgement. If RF Path is illegal |
| 2976 | * We will return false. |
| 2977 | * |
| 2978 | * Input: NONE |
| 2979 | * |
| 2980 | * Output: NONE |
| 2981 | * |
| 2982 | * Return: NONE |
| 2983 | * |
| 2984 | * Revised History: |
| 2985 | * When Who Remark |
| 2986 | * 11/15/2007 MHC Create Version 0. |
| 2987 | * |
| 2988 | *---------------------------------------------------------------------------*/ |
| 2989 | //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb |
| 2990 | //extern bool |
| 2991 | //PHY_CheckIsLegalRfPath8192S( |
| 2992 | // struct net_device* dev, |
| 2993 | // u32 eRFPath) |
| 2994 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) |
| 2995 | { |
| 2996 | // struct r8192_priv *priv = ieee80211_priv(dev); |
| 2997 | bool rtValue = TRUE; |
| 2998 | |
| 2999 | // NOt check RF Path now.! |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3000 | return rtValue; |
| 3001 | |
| 3002 | } /* PHY_CheckIsLegalRfPath8192S */ |
| 3003 | |
| 3004 | |
| 3005 | |
| 3006 | /*----------------------------------------------------------------------------- |
| 3007 | * Function: PHY_IQCalibrate8192S() |
| 3008 | * |
| 3009 | * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration |
| 3010 | * to improve RF EVM!!? |
| 3011 | * |
| 3012 | * Input: IN PADAPTER pAdapter |
| 3013 | * |
| 3014 | * Output: NONE |
| 3015 | * |
| 3016 | * Return: NONE |
| 3017 | * |
| 3018 | * Revised History: |
| 3019 | * When Who Remark |
| 3020 | * 10/07/2008 MHC Create. Document from SD3 RFSI Jenyu. |
| 3021 | * |
| 3022 | *---------------------------------------------------------------------------*/ |
| 3023 | //called by InitializeAdapter8192SE |
| 3024 | void |
| 3025 | PHY_IQCalibrate( struct net_device* dev) |
| 3026 | { |
| 3027 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 3028 | u32 i, reg; |
| 3029 | u32 old_value; |
| 3030 | long X, Y, TX0[4]; |
| 3031 | u32 TXA[4]; |
| 3032 | |
| 3033 | // 1. Check QFN68 or 64 92S (Read from EEPROM) |
| 3034 | |
| 3035 | // |
| 3036 | // 2. QFN 68 |
| 3037 | // |
| 3038 | // For 1T2R IQK only now !!! |
| 3039 | for (i = 0; i < 10; i++) |
| 3040 | { |
| 3041 | // IQK |
| 3042 | rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430); |
| 3043 | //PlatformStallExecution(5); |
| 3044 | udelay(5); |
| 3045 | rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4); |
| 3046 | udelay(5); |
| 3047 | rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000); |
| 3048 | udelay(5); |
| 3049 | rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148); |
| 3050 | udelay(5); |
| 3051 | rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2); |
| 3052 | udelay(5); |
| 3053 | rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1); |
| 3054 | udelay(5); |
| 3055 | rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d); |
| 3056 | udelay(5); |
| 3057 | rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba); |
| 3058 | udelay(5); |
| 3059 | rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1); |
| 3060 | udelay(5); |
| 3061 | rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001); |
| 3062 | udelay(5); |
| 3063 | rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001); |
| 3064 | udelay(2000); |
| 3065 | rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433); |
| 3066 | udelay(5); |
| 3067 | rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4); |
| 3068 | udelay(5); |
| 3069 | rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0); |
| 3070 | |
| 3071 | |
| 3072 | reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord); |
| 3073 | |
| 3074 | // Readback IQK value and rewrite |
| 3075 | if (!(reg&(BIT27|BIT28|BIT30|BIT31))) |
| 3076 | { |
| 3077 | old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF); |
| 3078 | |
| 3079 | // Calibrate init gain for A path for TX0 |
| 3080 | X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16; |
| 3081 | TXA[RF90_PATH_A] = (X * old_value)/0x100; |
| 3082 | reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); |
| 3083 | reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A]; |
| 3084 | rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); |
| 3085 | udelay(5); |
| 3086 | |
| 3087 | // Calibrate init gain for C path for TX0 |
| 3088 | Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16; |
| 3089 | TX0[RF90_PATH_C] = ((Y * old_value)/0x100); |
| 3090 | reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); |
| 3091 | reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16); |
| 3092 | rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); |
| 3093 | reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord); |
| 3094 | reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); |
| 3095 | rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg); |
| 3096 | udelay(5); |
| 3097 | |
| 3098 | // Calibrate RX A and B for RX0 |
| 3099 | reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord); |
| 3100 | X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16; |
| 3101 | reg = (reg & 0xFFFFFC00) |X; |
| 3102 | rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); |
| 3103 | Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16; |
| 3104 | reg = (reg & 0xFFFF03FF) |Y<<10; |
| 3105 | rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); |
| 3106 | udelay(5); |
| 3107 | old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF); |
| 3108 | |
| 3109 | // Calibrate init gain for A path for TX1 !!!!!! |
| 3110 | X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16; |
| 3111 | reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); |
| 3112 | TXA[RF90_PATH_A] = (X * old_value) / 0x100; |
| 3113 | reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A]; |
| 3114 | rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); |
| 3115 | udelay(5); |
| 3116 | |
| 3117 | // Calibrate init gain for C path for TX1 |
| 3118 | Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16; |
| 3119 | TX0[RF90_PATH_C] = ((Y * old_value)/0x100); |
| 3120 | reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); |
| 3121 | reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16); |
| 3122 | rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); |
| 3123 | reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord); |
| 3124 | reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); |
| 3125 | rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg); |
| 3126 | udelay(5); |
| 3127 | |
| 3128 | // Calibrate RX A and B for RX1 |
| 3129 | reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord); |
| 3130 | X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16; |
| 3131 | reg = (reg & 0xFFFFFC00) |X; |
| 3132 | rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); |
| 3133 | |
| 3134 | Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16; |
| 3135 | reg = (reg & 0xFFFF03FF) |Y<<10; |
| 3136 | rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); |
| 3137 | udelay(5); |
| 3138 | |
| 3139 | RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n"); |
| 3140 | break; |
| 3141 | } |
| 3142 | |
| 3143 | } |
| 3144 | |
| 3145 | |
| 3146 | // |
| 3147 | // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R. |
| 3148 | // |
| 3149 | |
| 3150 | |
| 3151 | } |
| 3152 | |
| 3153 | /*----------------------------------------------------------------------------- |
| 3154 | * Function: PHY_IQCalibrateBcut() |
| 3155 | * |
| 3156 | * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration |
| 3157 | * to improve RF EVM!!? |
| 3158 | * |
| 3159 | * Input: IN PADAPTER pAdapter |
| 3160 | * |
| 3161 | * Output: NONE |
| 3162 | * |
| 3163 | * Return: NONE |
| 3164 | * |
| 3165 | * Revised History: |
| 3166 | * When Who Remark |
| 3167 | * 11/18/2008 MHC Create. Document from SD3 RFSI Jenyu. |
| 3168 | * 92S B-cut QFN 68 pin IQ calibration procedure.doc |
| 3169 | * |
| 3170 | *---------------------------------------------------------------------------*/ |
| 3171 | extern void PHY_IQCalibrateBcut(struct net_device* dev) |
| 3172 | { |
| 3173 | //struct r8192_priv *priv = ieee80211_priv(dev); |
| 3174 | //PMGNT_INFO pMgntInfo = &pAdapter->MgntInfo; |
| 3175 | u32 i, reg; |
| 3176 | u32 old_value; |
| 3177 | long X, Y, TX0[4]; |
| 3178 | u32 TXA[4]; |
| 3179 | u32 calibrate_set[13] = {0}; |
| 3180 | u32 load_value[13]; |
| 3181 | u8 RfPiEnable=0; |
| 3182 | |
| 3183 | // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE) |
| 3184 | |
| 3185 | // |
| 3186 | // 1. Save e70~ee0 register setting, and load calibration setting |
| 3187 | // |
| 3188 | /* |
| 3189 | 0xee0[31:0]=0x3fed92fb; |
| 3190 | 0xedc[31:0] =0x3fed92fb; |
| 3191 | 0xe70[31:0] =0x3fed92fb; |
| 3192 | 0xe74[31:0] =0x3fed92fb; |
| 3193 | 0xe78[31:0] =0x3fed92fb; |
| 3194 | 0xe7c[31:0]= 0x3fed92fb; |
| 3195 | 0xe80[31:0]= 0x3fed92fb; |
| 3196 | 0xe84[31:0]= 0x3fed92fb; |
| 3197 | 0xe88[31:0]= 0x3fed92fb; |
| 3198 | 0xe8c[31:0]= 0x3fed92fb; |
| 3199 | 0xed0[31:0]= 0x3fed92fb; |
| 3200 | 0xed4[31:0]= 0x3fed92fb; |
| 3201 | 0xed8[31:0]= 0x3fed92fb; |
| 3202 | */ |
| 3203 | calibrate_set [0] = 0xee0; |
| 3204 | calibrate_set [1] = 0xedc; |
| 3205 | calibrate_set [2] = 0xe70; |
| 3206 | calibrate_set [3] = 0xe74; |
| 3207 | calibrate_set [4] = 0xe78; |
| 3208 | calibrate_set [5] = 0xe7c; |
| 3209 | calibrate_set [6] = 0xe80; |
| 3210 | calibrate_set [7] = 0xe84; |
| 3211 | calibrate_set [8] = 0xe88; |
| 3212 | calibrate_set [9] = 0xe8c; |
| 3213 | calibrate_set [10] = 0xed0; |
| 3214 | calibrate_set [11] = 0xed4; |
| 3215 | calibrate_set [12] = 0xed8; |
| 3216 | //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n")); |
| 3217 | for (i = 0; i < 13; i++) |
| 3218 | { |
| 3219 | load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord); |
| 3220 | rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb); |
| 3221 | |
| 3222 | } |
| 3223 | |
| 3224 | RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8); |
| 3225 | |
| 3226 | // |
| 3227 | // 2. QFN 68 |
| 3228 | // |
| 3229 | // For 1T2R IQK only now !!! |
| 3230 | for (i = 0; i < 10; i++) |
| 3231 | { |
| 3232 | RT_TRACE(COMP_INIT, "IQK -%d\n", i); |
| 3233 | //BB switch to PI mode. If default is PI mode, ignoring 2 commands below. |
| 3234 | if (!RfPiEnable) //if original is SI mode, then switch to PI mode. |
| 3235 | { |
| 3236 | //DbgPrint("IQK Switch to PI mode\n"); |
| 3237 | rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100); |
| 3238 | rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100); |
| 3239 | } |
| 3240 | |
| 3241 | // IQK |
| 3242 | // 2. IQ calibration & LO leakage calibration |
| 3243 | rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430); |
| 3244 | udelay(5); |
| 3245 | rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4); |
| 3246 | udelay(5); |
| 3247 | rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000); |
| 3248 | udelay(5); |
| 3249 | //path-A IQ K and LO K gain setting |
| 3250 | rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102); |
| 3251 | udelay(5); |
| 3252 | rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2); |
| 3253 | udelay(5); |
| 3254 | //set LO calibration |
| 3255 | rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1); |
| 3256 | udelay(5); |
| 3257 | //path-B IQ K and LO K gain setting |
| 3258 | rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102); |
| 3259 | udelay(5); |
| 3260 | rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05); |
| 3261 | udelay(5); |
| 3262 | //K idac_I & IQ |
| 3263 | rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000); |
| 3264 | udelay(5); |
| 3265 | rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000); |
| 3266 | udelay(5); |
| 3267 | |
| 3268 | // delay 2ms |
| 3269 | udelay(2000); |
| 3270 | |
| 3271 | //idac_Q setting |
| 3272 | rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1); |
| 3273 | udelay(5); |
| 3274 | //K idac_Q & IQ |
| 3275 | rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000); |
| 3276 | udelay(5); |
| 3277 | rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000); |
| 3278 | |
| 3279 | // delay 2ms |
| 3280 | udelay(2000); |
| 3281 | |
| 3282 | rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433); |
| 3283 | udelay(5); |
| 3284 | rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4); |
| 3285 | udelay(5); |
| 3286 | rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0); |
| 3287 | |
| 3288 | if (!RfPiEnable) //if original is SI mode, then switch to PI mode. |
| 3289 | { |
| 3290 | //DbgPrint("IQK Switch back to SI mode\n"); |
| 3291 | rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000); |
| 3292 | rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000); |
| 3293 | } |
| 3294 | |
| 3295 | |
| 3296 | reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord); |
| 3297 | |
| 3298 | // 3. check fail bit, and fill BB IQ matrix |
| 3299 | // Readback IQK value and rewrite |
| 3300 | if (!(reg&(BIT27|BIT28|BIT30|BIT31))) |
| 3301 | { |
| 3302 | old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF); |
| 3303 | |
| 3304 | // Calibrate init gain for A path for TX0 |
| 3305 | X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16; |
| 3306 | TXA[RF90_PATH_A] = (X * old_value)/0x100; |
| 3307 | reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); |
| 3308 | reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A]; |
| 3309 | rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); |
| 3310 | udelay(5); |
| 3311 | |
| 3312 | // Calibrate init gain for C path for TX0 |
| 3313 | Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16; |
| 3314 | TX0[RF90_PATH_C] = ((Y * old_value)/0x100); |
| 3315 | reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); |
| 3316 | reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16); |
| 3317 | rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); |
| 3318 | reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord); |
| 3319 | reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); |
| 3320 | rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg); |
| 3321 | udelay(5); |
| 3322 | |
| 3323 | // Calibrate RX A and B for RX0 |
| 3324 | reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord); |
| 3325 | X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16; |
| 3326 | reg = (reg & 0xFFFFFC00) |X; |
| 3327 | rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); |
| 3328 | Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16; |
| 3329 | reg = (reg & 0xFFFF03FF) |Y<<10; |
| 3330 | rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); |
| 3331 | udelay(5); |
| 3332 | old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF); |
| 3333 | |
| 3334 | // Calibrate init gain for A path for TX1 !!!!!! |
| 3335 | X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16; |
| 3336 | reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); |
| 3337 | TXA[RF90_PATH_A] = (X * old_value) / 0x100; |
| 3338 | reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A]; |
| 3339 | rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); |
| 3340 | udelay(5); |
| 3341 | |
| 3342 | // Calibrate init gain for C path for TX1 |
| 3343 | Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16; |
| 3344 | TX0[RF90_PATH_C] = ((Y * old_value)/0x100); |
| 3345 | reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); |
| 3346 | reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16); |
| 3347 | rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); |
| 3348 | reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord); |
| 3349 | reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); |
| 3350 | rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg); |
| 3351 | udelay(5); |
| 3352 | |
| 3353 | // Calibrate RX A and B for RX1 |
| 3354 | reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord); |
| 3355 | X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16; |
| 3356 | reg = (reg & 0xFFFFFC00) |X; |
| 3357 | rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); |
| 3358 | |
| 3359 | Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16; |
| 3360 | reg = (reg & 0xFFFF03FF) |Y<<10; |
| 3361 | rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); |
| 3362 | udelay(5); |
| 3363 | |
| 3364 | RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n"); |
| 3365 | break; |
| 3366 | } |
| 3367 | |
| 3368 | } |
| 3369 | |
| 3370 | // |
| 3371 | // 4. Reload e70~ee0 register setting. |
| 3372 | // |
| 3373 | //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n")); |
| 3374 | for (i = 0; i < 13; i++) |
| 3375 | rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]); |
| 3376 | |
| 3377 | |
| 3378 | // |
| 3379 | // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R. |
| 3380 | // |
| 3381 | |
| 3382 | |
| 3383 | |
| 3384 | } // PHY_IQCalibrateBcut |
| 3385 | |
| 3386 | |
| 3387 | // |
| 3388 | // Move from phycfg.c to gen.c to be code independent later |
| 3389 | // |
| 3390 | //-------------------------Move to other DIR later----------------------------*/ |
| 3391 | //#if (DEV_BUS_TYPE == USB_INTERFACE) |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3392 | |
| 3393 | // use in phy only (in win it's timer) |
| 3394 | void SwChnlCallback8192SUsb(struct net_device *dev) |
| 3395 | { |
| 3396 | |
| 3397 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3398 | u32 delay; |
| 3399 | // bool ret; |
| 3400 | |
| 3401 | RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\ |
| 3402 | %d\n", priv->chan); |
| 3403 | |
| 3404 | |
| 3405 | if(!priv->up) |
| 3406 | return; |
| 3407 | |
| 3408 | if(priv->rf_chip == RF_PSEUDO_11N) |
| 3409 | { |
| 3410 | priv->SwChnlInProgress=FALSE; |
| 3411 | return; //return immediately if it is peudo-phy |
| 3412 | } |
| 3413 | |
| 3414 | do{ |
| 3415 | if(!priv->SwChnlInProgress) |
| 3416 | break; |
| 3417 | |
| 3418 | if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) |
| 3419 | { |
| 3420 | if(delay>0) |
| 3421 | { |
| 3422 | //PlatformSetTimer(dev, &priv->SwChnlTimer, delay); |
| 3423 | |
| 3424 | } |
| 3425 | else |
| 3426 | continue; |
| 3427 | } |
| 3428 | else |
| 3429 | { |
| 3430 | priv->SwChnlInProgress=FALSE; |
| 3431 | } |
| 3432 | break; |
| 3433 | }while(TRUE); |
| 3434 | } |
| 3435 | |
| 3436 | |
| 3437 | // |
| 3438 | // Callback routine of the work item for switch channel. |
| 3439 | // |
| 3440 | // use in phy only (in win it's work) |
| 3441 | void SwChnlCallback8192SUsbWorkItem(struct net_device *dev ) |
| 3442 | { |
| 3443 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3444 | |
| 3445 | RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n"); |
| 3446 | #ifdef TO_DO_LIST |
| 3447 | if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter)) |
| 3448 | { |
| 3449 | RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n")); |
| 3450 | |
| 3451 | pHalData->SwChnlInProgress = FALSE; |
| 3452 | return; |
| 3453 | } |
| 3454 | #endif |
| 3455 | phy_FinishSwChnlNow(dev, priv->chan); |
| 3456 | priv->SwChnlInProgress = FALSE; |
| 3457 | |
| 3458 | RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n"); |
| 3459 | } |
| 3460 | |
| 3461 | |
| 3462 | /*----------------------------------------------------------------------------- |
| 3463 | * Function: SetBWModeCallback8192SUsb() |
| 3464 | * |
| 3465 | * Overview: Timer callback function for SetSetBWMode |
| 3466 | * |
| 3467 | * Input: PRT_TIMER pTimer |
| 3468 | * |
| 3469 | * Output: NONE |
| 3470 | * |
| 3471 | * Return: NONE |
| 3472 | * |
| 3473 | * Note: (1) We do not take j mode into consideration now |
| 3474 | * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run |
| 3475 | * concurrently? |
| 3476 | *---------------------------------------------------------------------------*/ |
| 3477 | //====>//rtl8192_SetBWMode |
| 3478 | // use in phy only (in win it's timer) |
| 3479 | void SetBWModeCallback8192SUsb(struct net_device *dev) |
| 3480 | { |
| 3481 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3482 | u8 regBwOpMode; |
| 3483 | |
| 3484 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 3485 | //u32 NowL, NowH; |
| 3486 | //u8Byte BeginTime, EndTime; |
| 3487 | u8 regRRSR_RSC; |
| 3488 | |
| 3489 | RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \ |
| 3490 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); |
| 3491 | |
| 3492 | if(priv->rf_chip == RF_PSEUDO_11N) |
| 3493 | { |
| 3494 | priv->SetBWModeInProgress= FALSE; |
| 3495 | return; |
| 3496 | } |
| 3497 | |
| 3498 | if(!priv->up) |
| 3499 | return; |
| 3500 | |
| 3501 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 3502 | //NowL = read_nic_dword(dev, TSFR); |
| 3503 | //NowH = read_nic_dword(dev, TSFR+4); |
| 3504 | //BeginTime = ((u8Byte)NowH << 32) + NowL; |
| 3505 | |
| 3506 | //3<1>Set MAC register |
| 3507 | regBwOpMode = read_nic_byte(dev, BW_OPMODE); |
| 3508 | regRRSR_RSC = read_nic_byte(dev, RRSR+2); |
| 3509 | |
| 3510 | switch(priv->CurrentChannelBW) |
| 3511 | { |
| 3512 | case HT_CHANNEL_WIDTH_20: |
| 3513 | regBwOpMode |= BW_OPMODE_20MHZ; |
| 3514 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works |
| 3515 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 3516 | break; |
| 3517 | |
| 3518 | case HT_CHANNEL_WIDTH_20_40: |
| 3519 | regBwOpMode &= ~BW_OPMODE_20MHZ; |
| 3520 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works |
| 3521 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 3522 | |
| 3523 | regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5); |
| 3524 | write_nic_byte(dev, RRSR+2, regRRSR_RSC); |
| 3525 | break; |
| 3526 | |
| 3527 | default: |
| 3528 | RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\ |
| 3529 | unknown Bandwidth: %#X\n",priv->CurrentChannelBW); |
| 3530 | break; |
| 3531 | } |
| 3532 | |
| 3533 | //3 <2>Set PHY related register |
| 3534 | switch(priv->CurrentChannelBW) |
| 3535 | { |
| 3536 | case HT_CHANNEL_WIDTH_20: |
| 3537 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); |
| 3538 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3539 | |
| 3540 | if (priv->card_8192_version >= VERSION_8192S_BCUT) |
| 3541 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58); |
| 3542 | |
| 3543 | break; |
| 3544 | case HT_CHANNEL_WIDTH_20_40: |
| 3545 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); |
| 3546 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); |
| 3547 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); |
| 3548 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); |
| 3549 | |
| 3550 | // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 |
| 3551 | //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000); |
| 3552 | //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e); |
| 3553 | //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409); |
| 3554 | //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0); |
| 3555 | |
| 3556 | if (priv->card_8192_version >= VERSION_8192S_BCUT) |
| 3557 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18); |
| 3558 | |
| 3559 | break; |
| 3560 | default: |
| 3561 | RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\ |
| 3562 | ,priv->CurrentChannelBW); |
| 3563 | break; |
| 3564 | |
| 3565 | } |
| 3566 | //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 |
| 3567 | |
| 3568 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 3569 | //NowL = read_nic_dword(dev, TSFR); |
| 3570 | //NowH = read_nic_dword(dev, TSFR+4); |
| 3571 | //EndTime = ((u8Byte)NowH << 32) + NowL; |
| 3572 | //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); |
| 3573 | |
| 3574 | #if 1 |
| 3575 | //3<3>Set RF related register |
| 3576 | switch( priv->rf_chip ) |
| 3577 | { |
| 3578 | case RF_8225: |
| 3579 | PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW); |
| 3580 | break; |
| 3581 | |
| 3582 | case RF_8256: |
| 3583 | // Please implement this function in Hal8190PciPhy8256.c |
| 3584 | //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); |
| 3585 | break; |
| 3586 | |
| 3587 | case RF_6052: |
| 3588 | PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW); |
| 3589 | break; |
| 3590 | |
| 3591 | case RF_8258: |
| 3592 | // Please implement this function in Hal8190PciPhy8258.c |
| 3593 | // PHY_SetRF8258Bandwidth(); |
| 3594 | break; |
| 3595 | |
| 3596 | case RF_PSEUDO_11N: |
| 3597 | // Do Nothing |
| 3598 | break; |
| 3599 | |
| 3600 | default: |
| 3601 | //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip)); |
| 3602 | break; |
| 3603 | } |
| 3604 | #endif |
| 3605 | priv->SetBWModeInProgress= FALSE; |
| 3606 | |
| 3607 | RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" ); |
| 3608 | } |
| 3609 | |
| 3610 | // |
| 3611 | // Callback routine of the work item for set bandwidth mode. |
| 3612 | // |
| 3613 | // use in phy only (in win it's work) |
| 3614 | void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev) |
| 3615 | { |
| 3616 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3617 | u8 regBwOpMode; |
| 3618 | |
| 3619 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 3620 | //u32 NowL, NowH; |
| 3621 | //u8Byte BeginTime, EndTime; |
| 3622 | u8 regRRSR_RSC; |
| 3623 | |
| 3624 | RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem() Switch to %s bandwidth\n", \ |
| 3625 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); |
| 3626 | |
| 3627 | if(priv->rf_chip == RF_PSEUDO_11N) |
| 3628 | { |
| 3629 | priv->SetBWModeInProgress= FALSE; |
| 3630 | return; |
| 3631 | } |
| 3632 | |
| 3633 | if(!priv->up) |
| 3634 | return; |
| 3635 | |
| 3636 | // Added it for 20/40 mhz switch time evaluation by guangan 070531 |
| 3637 | //NowL = read_nic_dword(dev, TSFR); |
| 3638 | //NowH = read_nic_dword(dev, TSFR+4); |
| 3639 | //BeginTime = ((u8Byte)NowH << 32) + NowL; |
| 3640 | |
| 3641 | //3<1>Set MAC register |
| 3642 | regBwOpMode = read_nic_byte(dev, BW_OPMODE); |
| 3643 | regRRSR_RSC = read_nic_byte(dev, RRSR+2); |
| 3644 | |
| 3645 | switch(priv->CurrentChannelBW) |
| 3646 | { |
| 3647 | case HT_CHANNEL_WIDTH_20: |
| 3648 | regBwOpMode |= BW_OPMODE_20MHZ; |
| 3649 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works |
| 3650 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 3651 | break; |
| 3652 | |
| 3653 | case HT_CHANNEL_WIDTH_20_40: |
| 3654 | regBwOpMode &= ~BW_OPMODE_20MHZ; |
| 3655 | // 2007/02/07 Mark by Emily becasue we have not verify whether this register works |
| 3656 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 3657 | regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5); |
| 3658 | write_nic_byte(dev, RRSR+2, regRRSR_RSC); |
| 3659 | |
| 3660 | break; |
| 3661 | |
| 3662 | default: |
| 3663 | RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\ |
| 3664 | unknown Bandwidth: %#X\n",priv->CurrentChannelBW); |
| 3665 | break; |
| 3666 | } |
| 3667 | |
| 3668 | //3 <2>Set PHY related register |
| 3669 | switch(priv->CurrentChannelBW) |
| 3670 | { |
| 3671 | case HT_CHANNEL_WIDTH_20: |
| 3672 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); |
| 3673 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); |
| 3674 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3675 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58); |
| 3676 | |
| 3677 | break; |
| 3678 | case HT_CHANNEL_WIDTH_20_40: |
| 3679 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); |
| 3680 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3681 | |
| 3682 | // Set Control channel to upper or lower. These settings are required only for 40MHz |
| 3683 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); |
| 3684 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); |
| 3685 | |
| 3686 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18); |
| 3687 | |
| 3688 | break; |
| 3689 | |
| 3690 | |
| 3691 | default: |
| 3692 | RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\ |
| 3693 | ,priv->CurrentChannelBW); |
| 3694 | break; |
| 3695 | |
| 3696 | } |
| 3697 | //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 |
| 3698 | |
| 3699 | //3<3>Set RF related register |
| 3700 | switch( priv->rf_chip ) |
| 3701 | { |
| 3702 | case RF_8225: |
| 3703 | PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW); |
| 3704 | break; |
| 3705 | |
| 3706 | case RF_8256: |
| 3707 | // Please implement this function in Hal8190PciPhy8256.c |
| 3708 | //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); |
| 3709 | break; |
| 3710 | |
| 3711 | case RF_6052: |
| 3712 | PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW); |
| 3713 | break; |
| 3714 | |
| 3715 | case RF_8258: |
| 3716 | // Please implement this function in Hal8190PciPhy8258.c |
| 3717 | // PHY_SetRF8258Bandwidth(); |
| 3718 | break; |
| 3719 | |
| 3720 | case RF_PSEUDO_11N: |
| 3721 | // Do Nothing |
| 3722 | break; |
| 3723 | |
| 3724 | default: |
| 3725 | //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip)); |
| 3726 | break; |
| 3727 | } |
| 3728 | |
| 3729 | priv->SetBWModeInProgress= FALSE; |
| 3730 | |
| 3731 | RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" ); |
| 3732 | } |
| 3733 | |
| 3734 | //--------------------------Move to oter DIR later-------------------------------*/ |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3735 | void InitialGain8192S(struct net_device *dev, u8 Operation) |
| 3736 | { |
| 3737 | #ifdef TO_DO_LIST |
| 3738 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3739 | #endif |
| 3740 | |
| 3741 | } |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3742 | |
| 3743 | void InitialGain819xUsb(struct net_device *dev, u8 Operation) |
| 3744 | { |
| 3745 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3746 | |
| 3747 | priv->InitialGainOperateType = Operation; |
| 3748 | |
| 3749 | if(priv->up) |
| 3750 | { |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3751 | queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0); |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3752 | } |
| 3753 | } |
| 3754 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3755 | extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) |
| 3756 | { |
| 3757 | struct delayed_work *dwork = container_of(work,struct delayed_work,work); |
| 3758 | struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq); |
| 3759 | struct net_device *dev = priv->ieee80211->dev; |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3760 | #define SCAN_RX_INITIAL_GAIN 0x17 |
| 3761 | #define POWER_DETECTION_TH 0x08 |
| 3762 | u32 BitMask; |
| 3763 | u8 initial_gain; |
| 3764 | u8 Operation; |
| 3765 | |
| 3766 | Operation = priv->InitialGainOperateType; |
| 3767 | |
| 3768 | switch(Operation) |
| 3769 | { |
| 3770 | case IG_Backup: |
| 3771 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); |
| 3772 | initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];// |
| 3773 | BitMask = bMaskByte0; |
| 3774 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 3775 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF |
| 3776 | priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); |
| 3777 | priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); |
| 3778 | priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); |
| 3779 | priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); |
| 3780 | BitMask = bMaskByte2; |
| 3781 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); |
| 3782 | |
| 3783 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); |
| 3784 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); |
| 3785 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); |
| 3786 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); |
| 3787 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); |
| 3788 | |
| 3789 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); |
| 3790 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); |
| 3791 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); |
| 3792 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); |
| 3793 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); |
| 3794 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); |
| 3795 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); |
| 3796 | break; |
| 3797 | case IG_Restore: |
| 3798 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); |
| 3799 | BitMask = 0x7f; //Bit0~ Bit6 |
| 3800 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 3801 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF |
| 3802 | |
| 3803 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); |
| 3804 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); |
| 3805 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); |
| 3806 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); |
| 3807 | BitMask = bMaskByte2; |
| 3808 | rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); |
| 3809 | |
| 3810 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); |
| 3811 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); |
| 3812 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); |
| 3813 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); |
| 3814 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); |
| 3815 | |
| 3816 | PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel); |
| 3817 | |
| 3818 | if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
| 3819 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON |
| 3820 | break; |
| 3821 | default: |
| 3822 | RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); |
| 3823 | break; |
| 3824 | } |
| 3825 | } |
| 3826 | |
Jerry Chuang | 5f53d8c | 2009-05-21 22:16:02 -0700 | [diff] [blame] | 3827 | |
| 3828 | //----------------------------------------------------------------------------- |
| 3829 | // Description: |
| 3830 | // Schedule workitem to send specific CMD IO to FW. |
| 3831 | // Added by Roger, 2008.12.03. |
| 3832 | // |
| 3833 | //----------------------------------------------------------------------------- |
| 3834 | bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO) |
| 3835 | { |
| 3836 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3837 | u16 FwCmdWaitCounter = 0; |
| 3838 | |
| 3839 | u16 FwCmdWaitLimit = 1000; |
| 3840 | |
| 3841 | //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest) |
| 3842 | if(priv->bInHctTest) |
| 3843 | return true; |
| 3844 | |
| 3845 | RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress); |
| 3846 | |
| 3847 | // Will be done by high power respectively. |
| 3848 | if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME) |
| 3849 | { |
| 3850 | RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO); |
| 3851 | return false; |
| 3852 | } |
| 3853 | |
| 3854 | #if 1 |
| 3855 | while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit) |
| 3856 | { |
| 3857 | //if(RT_USB_CANNOT_IO(Adapter)) |
| 3858 | //{ |
| 3859 | // RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n")); |
| 3860 | // return FALSE; |
| 3861 | //} |
| 3862 | |
| 3863 | RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n"); |
| 3864 | return false; |
| 3865 | FwCmdWaitCounter ++; |
| 3866 | RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter); |
| 3867 | udelay(100); |
| 3868 | } |
| 3869 | |
| 3870 | if(FwCmdWaitCounter == FwCmdWaitLimit) |
| 3871 | { |
| 3872 | //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n")); |
| 3873 | RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n"); |
| 3874 | //return false; |
| 3875 | } |
| 3876 | #endif |
| 3877 | if (priv->SetFwCmdInProgress) |
| 3878 | { |
| 3879 | RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO); |
| 3880 | return false; |
| 3881 | } |
| 3882 | priv->SetFwCmdInProgress = TRUE; |
| 3883 | priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use. |
| 3884 | |
| 3885 | phy_SetFwCmdIOCallback(dev); |
| 3886 | return true; |
| 3887 | } |
| 3888 | void ChkFwCmdIoDone(struct net_device* dev) |
| 3889 | { |
| 3890 | u16 PollingCnt = 1000; |
| 3891 | u32 tmpValue; |
| 3892 | |
| 3893 | do |
| 3894 | {// Make sure that CMD IO has be accepted by FW. |
| 3895 | #ifdef TO_DO_LIST |
| 3896 | if(RT_USB_CANNOT_IO(Adapter)) |
| 3897 | { |
| 3898 | RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n"); |
| 3899 | return; |
| 3900 | } |
| 3901 | #endif |
| 3902 | udelay(10); // sleep 20us |
| 3903 | tmpValue = read_nic_dword(dev, WFM5); |
| 3904 | if(tmpValue == 0) |
| 3905 | { |
| 3906 | RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n"); |
| 3907 | break; |
| 3908 | } |
| 3909 | else |
| 3910 | { |
| 3911 | RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt); |
| 3912 | } |
| 3913 | }while( --PollingCnt ); |
| 3914 | |
| 3915 | if(PollingCnt == 0) |
| 3916 | { |
| 3917 | RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n"); |
| 3918 | } |
| 3919 | } |
| 3920 | // Callback routine of the timer callback for FW Cmd IO. |
| 3921 | // |
| 3922 | // Description: |
| 3923 | // This routine will send specific CMD IO to FW and check whether it is done. |
| 3924 | // |
| 3925 | void phy_SetFwCmdIOCallback(struct net_device* dev) |
| 3926 | { |
| 3927 | //struct net_device* dev = (struct net_device*) data; |
| 3928 | u32 input; |
| 3929 | static u32 ScanRegister; |
| 3930 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 3931 | if(!priv->up) |
| 3932 | { |
| 3933 | RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n"); |
| 3934 | return; |
| 3935 | } |
| 3936 | |
| 3937 | RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress); |
| 3938 | |
| 3939 | switch(priv->CurrentFwCmdIO) |
| 3940 | { |
| 3941 | case FW_CMD_HIGH_PWR_ENABLE: |
| 3942 | if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0) |
| 3943 | write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); |
| 3944 | break; |
| 3945 | |
| 3946 | case FW_CMD_HIGH_PWR_DISABLE: |
| 3947 | write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); |
| 3948 | break; |
| 3949 | |
| 3950 | case FW_CMD_DIG_RESUME: |
| 3951 | write_nic_dword(dev, WFM5, FW_DIG_RESUME); |
| 3952 | break; |
| 3953 | |
| 3954 | case FW_CMD_DIG_HALT: |
| 3955 | write_nic_dword(dev, WFM5, FW_DIG_HALT); |
| 3956 | break; |
| 3957 | |
| 3958 | // |
| 3959 | // <Roger_Notes> The following FW CMD IO was combined into single operation |
| 3960 | // (i.e., to prevent number of system workitem out of resource!!). |
| 3961 | // 2008.12.04. |
| 3962 | // |
| 3963 | case FW_CMD_RESUME_DM_BY_SCAN: |
| 3964 | RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n"); |
| 3965 | if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0) |
| 3966 | { |
| 3967 | write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break; |
| 3968 | ChkFwCmdIoDone(dev); |
| 3969 | } |
| 3970 | write_nic_dword(dev, WFM5, FW_DIG_RESUME); |
| 3971 | break; |
| 3972 | |
| 3973 | case FW_CMD_PAUSE_DM_BY_SCAN: |
| 3974 | RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n"); |
| 3975 | write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break; |
| 3976 | ChkFwCmdIoDone(dev); |
| 3977 | write_nic_dword(dev, WFM5, FW_DIG_HALT); |
| 3978 | break; |
| 3979 | |
| 3980 | // |
| 3981 | // <Roger_Notes> The following FW CMD IO should be checked |
| 3982 | // (i.e., workitem schedule timing issue!!). |
| 3983 | // 2008.12.04. |
| 3984 | // |
| 3985 | case FW_CMD_DIG_DISABLE: |
| 3986 | RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n"); |
| 3987 | write_nic_dword(dev, WFM5, FW_DIG_DISABLE); |
| 3988 | break; |
| 3989 | |
| 3990 | case FW_CMD_DIG_ENABLE: |
| 3991 | RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n"); |
| 3992 | write_nic_dword(dev, WFM5, FW_DIG_ENABLE); |
| 3993 | break; |
| 3994 | |
| 3995 | case FW_CMD_RA_RESET: |
| 3996 | write_nic_dword(dev, WFM5, FW_RA_RESET); |
| 3997 | break; |
| 3998 | |
| 3999 | case FW_CMD_RA_ACTIVE: |
| 4000 | write_nic_dword(dev, WFM5, FW_RA_ACTIVE); |
| 4001 | break; |
| 4002 | |
| 4003 | case FW_CMD_RA_REFRESH_N: |
| 4004 | RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n"); |
| 4005 | if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL) |
| 4006 | input = FW_RA_REFRESH; |
| 4007 | else |
| 4008 | input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8); |
| 4009 | write_nic_dword(dev, WFM5, input); |
| 4010 | break; |
| 4011 | case FW_CMD_RA_REFRESH_BG: |
| 4012 | RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n"); |
| 4013 | write_nic_dword(dev, WFM5, FW_RA_REFRESH); |
| 4014 | ChkFwCmdIoDone(dev); |
| 4015 | write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG); |
| 4016 | break; |
| 4017 | |
| 4018 | case FW_CMD_IQK_ENABLE: |
| 4019 | write_nic_dword(dev, WFM5, FW_IQK_ENABLE); |
| 4020 | break; |
| 4021 | |
| 4022 | case FW_CMD_TXPWR_TRACK_ENABLE: |
| 4023 | write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE); |
| 4024 | break; |
| 4025 | |
| 4026 | case FW_CMD_TXPWR_TRACK_DISABLE: |
| 4027 | write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE); |
| 4028 | break; |
| 4029 | |
| 4030 | default: |
| 4031 | RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO); |
| 4032 | break; |
| 4033 | } |
| 4034 | |
| 4035 | ChkFwCmdIoDone(dev); |
| 4036 | |
| 4037 | switch(priv->CurrentFwCmdIO) |
| 4038 | { |
| 4039 | case FW_CMD_HIGH_PWR_DISABLE: |
| 4040 | //if(pMgntInfo->bTurboScan) |
| 4041 | { |
| 4042 | //Lower initial gain |
| 4043 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17); |
| 4044 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17); |
| 4045 | // CCA threshold |
| 4046 | rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40); |
| 4047 | // Disable OFDM Part |
| 4048 | rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1); |
| 4049 | ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord); |
| 4050 | rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf); |
| 4051 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); |
| 4052 | } |
| 4053 | break; |
| 4054 | |
| 4055 | case FW_CMD_HIGH_PWR_ENABLE: |
| 4056 | //if(pMgntInfo->bTurboScan) |
| 4057 | { |
| 4058 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36); |
| 4059 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36); |
| 4060 | |
| 4061 | // CCA threshold |
| 4062 | rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83); |
| 4063 | // Enable OFDM Part |
| 4064 | rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0); |
| 4065 | |
| 4066 | //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0. |
| 4067 | if(ScanRegister != 0){ |
| 4068 | rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister); |
| 4069 | } |
| 4070 | |
| 4071 | if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R) |
| 4072 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3); |
| 4073 | else |
| 4074 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1); |
| 4075 | } |
| 4076 | break; |
| 4077 | } |
| 4078 | |
| 4079 | priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag. |
| 4080 | RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n"); |
| 4081 | |
| 4082 | } |
| 4083 | |