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Stephen Warren33918112012-01-19 08:16:35 +00001NVIDIA Tegra GPIO controller
Grant Likelydf221222011-06-15 14:54:14 -06002
3Required properties:
Stephen Warren33918112012-01-19 08:16:35 +00004- compatible : "nvidia,tegra<chip>-gpio"
Stephen Warrena38b84f2012-01-04 08:39:34 +00005- reg : Physical base address and length of the controller's registers.
Stephen Warren33918112012-01-19 08:16:35 +00006- interrupts : The interrupt outputs from the controller. For Tegra20,
7 there should be 7 interrupts specified, and for Tegra30, there should
8 be 8 interrupts specified.
Grant Likelydf221222011-06-15 14:54:14 -06009- #gpio-cells : Should be two. The first cell is the pin number and the
Olof Johanssoneb5064d2011-07-14 22:17:13 -070010 second cell is used to specify optional parameters:
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
Grant Likelydf221222011-06-15 14:54:14 -060012- gpio-controller : Marks the device node as a GPIO controller.
Stephen Warren6f74dc92012-01-04 08:39:37 +000013- #interrupt-cells : Should be 2.
14 The first cell is the GPIO number.
15 The second cell is used to specify flags:
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
20 8 = active low level-sensitive.
21 Valid combinations are 1, 2, 3, 4, 8.
22- interrupt-controller : Marks the device node as an interrupt controller.
Stephen Warrena38b84f2012-01-04 08:39:34 +000023
24Example:
25
26gpio: gpio@6000d000 {
27 compatible = "nvidia,tegra20-gpio";
28 reg = < 0x6000d000 0x1000 >;
29 interrupts = < 0 32 0x04
30 0 33 0x04
31 0 34 0x04
32 0 35 0x04
33 0 55 0x04
34 0 87 0x04
35 0 89 0x04 >;
36 #gpio-cells = <2>;
37 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +000038 #interrupt-cells = <2>;
39 interrupt-controller;
Stephen Warrena38b84f2012-01-04 08:39:34 +000040};