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Juha Yrjola4bbbc1a2006-06-26 16:16:16 -07001/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
Afzal Mohammedbc3668e2012-09-29 12:26:13 +053014#include <linux/platform_data/mtd-nand-omap2.h>
15
Paul Walmsleyfd1dc872008-10-06 15:49:17 +030016/* Maximum Number of Chip Selects */
17#define GPMC_CS_NUM 8
18
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070019#define GPMC_CS_CONFIG1 0x00
20#define GPMC_CS_CONFIG2 0x04
21#define GPMC_CS_CONFIG3 0x08
22#define GPMC_CS_CONFIG4 0x0c
23#define GPMC_CS_CONFIG5 0x10
24#define GPMC_CS_CONFIG6 0x14
25#define GPMC_CS_CONFIG7 0x18
26#define GPMC_CS_NAND_COMMAND 0x1c
27#define GPMC_CS_NAND_ADDRESS 0x20
28#define GPMC_CS_NAND_DATA 0x24
29
Sukumar Ghorai948d38e2010-07-09 09:14:44 +000030/* Control Commands */
31#define GPMC_CONFIG_RDY_BSY 0x00000001
32#define GPMC_CONFIG_DEV_SIZE 0x00000002
33#define GPMC_CONFIG_DEV_TYPE 0x00000003
34#define GPMC_SET_IRQ_STATUS 0x00000004
35#define GPMC_CONFIG_WP 0x00000005
36
Sukumar Ghoraidb97eb7d2011-01-28 15:42:05 +053037#define GPMC_ENABLE_IRQ 0x0000000d
38
Sukumar Ghorai948d38e2010-07-09 09:14:44 +000039/* ECC commands */
40#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
41#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
42#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
Tony Lindgren646e3ed2008-10-06 15:49:36 +030043
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070044#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
David Brownell1c22cc12006-12-06 17:13:55 -080045#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070046#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
47#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
David Brownell1c22cc12006-12-06 17:13:55 -080048#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070049#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
50#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
51#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
52#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
53#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
54#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
55#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
56#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
57#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
Mark Jacksonc9fb8092013-03-05 10:13:40 +000061#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070062#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
65#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
66#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
Rajendra Nayaka2d3e7b2008-09-26 17:47:33 +053067#define GPMC_CONFIG7_CSVALID (1 << 6)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070068
Sukumar Ghorai948d38e2010-07-09 09:14:44 +000069#define GPMC_DEVICETYPE_NOR 0
70#define GPMC_DEVICETYPE_NAND 2
71#define GPMC_CONFIG_WRITEPROTECT 0x00000010
Sukumar Ghorai948d38e2010-07-09 09:14:44 +000072#define WR_RD_PIN_MONITORING 0x00600000
Sukumar Ghoraidb97eb7d2011-01-28 15:42:05 +053073#define GPMC_IRQ_FIFOEVENTENABLE 0x01
74#define GPMC_IRQ_COUNT_EVENT 0x02
Sukumar Ghorai948d38e2010-07-09 09:14:44 +000075
Jon Hunteraa8d4762013-02-21 15:25:23 -060076#define GPMC_BURST_4 4 /* 4 word burst */
77#define GPMC_BURST_8 8 /* 8 word burst */
78#define GPMC_BURST_16 16 /* 16 word burst */
79#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
80#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
Jon Hunterc3be5b42013-02-21 13:46:22 -060081#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
82#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
Sukumar Ghorai317379a2011-01-28 15:42:07 +053083
Afzal Mohammed559d94b2012-05-28 17:51:37 +053084/* bool type time settings */
85struct gpmc_bool_timings {
86 bool cycle2cyclediffcsen;
87 bool cycle2cyclesamecsen;
88 bool we_extra_delay;
89 bool oe_extra_delay;
90 bool adv_extra_delay;
91 bool cs_extra_delay;
92 bool time_para_granularity;
93};
94
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070095/*
Adrian Huntera3551f52010-12-09 10:48:27 +020096 * Note that all values in this struct are in nanoseconds except sync_clk
97 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070098 */
99struct gpmc_timings {
Adrian Huntera3551f52010-12-09 10:48:27 +0200100 /* Minimum clock period for synchronous mode (in picoseconds) */
101 u32 sync_clk;
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700102
103 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
Afzal Mohammed246da262012-08-02 20:02:10 +0530104 u32 cs_on; /* Assertion time */
105 u32 cs_rd_off; /* Read deassertion time */
106 u32 cs_wr_off; /* Write deassertion time */
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700107
108 /* ADV signal timings corresponding to GPMC_CONFIG3 */
Afzal Mohammed246da262012-08-02 20:02:10 +0530109 u32 adv_on; /* Assertion time */
110 u32 adv_rd_off; /* Read deassertion time */
111 u32 adv_wr_off; /* Write deassertion time */
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700112
113 /* WE signals timings corresponding to GPMC_CONFIG4 */
Afzal Mohammed246da262012-08-02 20:02:10 +0530114 u32 we_on; /* WE assertion time */
115 u32 we_off; /* WE deassertion time */
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700116
117 /* OE signals timings corresponding to GPMC_CONFIG4 */
Afzal Mohammed246da262012-08-02 20:02:10 +0530118 u32 oe_on; /* OE assertion time */
119 u32 oe_off; /* OE deassertion time */
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700120
121 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
Afzal Mohammed246da262012-08-02 20:02:10 +0530122 u32 page_burst_access; /* Multiple access word delay */
123 u32 access; /* Start-cycle to first data valid delay */
124 u32 rd_cycle; /* Total read cycle time */
125 u32 wr_cycle; /* Total write cycle time */
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300126
Afzal Mohammed246da262012-08-02 20:02:10 +0530127 u32 bus_turnaround;
128 u32 cycle2cycle_delay;
Afzal Mohammed559d94b2012-05-28 17:51:37 +0530129
Afzal Mohammed246da262012-08-02 20:02:10 +0530130 u32 wait_monitoring;
131 u32 clk_activation;
Afzal Mohammed559d94b2012-05-28 17:51:37 +0530132
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300133 /* The following are only on OMAP3430 */
Afzal Mohammed246da262012-08-02 20:02:10 +0530134 u32 wr_access; /* WRACCESSTIME */
135 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
Afzal Mohammed559d94b2012-05-28 17:51:37 +0530136
137 struct gpmc_bool_timings bool_timings;
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700138};
139
Afzal Mohammed246da262012-08-02 20:02:10 +0530140/* Device timings in picoseconds */
141struct gpmc_device_timings {
142 u32 t_ceasu; /* address setup to CS valid */
143 u32 t_avdasu; /* address setup to ADV valid */
144 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
145 * of tusb using these timings even for sync whilst
146 * ideally for adv_rd/(wr)_off it should have considered
147 * t_avdh instead. This indirectly necessitates r/w
148 * variations of t_avdp as it is possible to have one
149 * sync & other async
150 */
151 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
152 u32 t_avdp_w;
153 u32 t_aavdh; /* address hold time */
154 u32 t_oeasu; /* address setup to OE valid */
155 u32 t_aa; /* access time from ADV assertion */
156 u32 t_iaa; /* initial access time */
157 u32 t_oe; /* access time from OE assertion */
158 u32 t_ce; /* access time from CS asertion */
159 u32 t_rd_cycle; /* read cycle time */
160 u32 t_cez_r; /* read CS deassertion to high Z */
161 u32 t_cez_w; /* write CS deassertion to high Z */
162 u32 t_oez; /* OE deassertion to high Z */
163 u32 t_weasu; /* address setup to WE valid */
164 u32 t_wpl; /* write assertion time */
165 u32 t_wph; /* write deassertion time */
166 u32 t_wr_cycle; /* write cycle time */
167
168 u32 clk;
169 u32 t_bacc; /* burst access valid clock to output delay */
170 u32 t_ces; /* CS setup time to clk */
171 u32 t_avds; /* ADV setup time to clk */
172 u32 t_avdh; /* ADV hold time from clk */
173 u32 t_ach; /* address hold time from clk */
174 u32 t_rdyo; /* clk to ready valid */
175
176 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
177 u32 t_ce_avd; /* CS on to ADV on delay */
178
179 /* XXX: check the possibility of combining
180 * cyc_aavhd_oe & cyc_aavdh_we
181 */
182 u8 cyc_aavdh_oe;/* read address hold time in cycles */
183 u8 cyc_aavdh_we;/* write address hold time in cycles */
184 u8 cyc_oe; /* access time from OE assertion in cycles */
185 u8 cyc_wpl; /* write deassertion time in cycles */
186 u32 cyc_iaa; /* initial access time in cycles */
187
Afzal Mohammed246da262012-08-02 20:02:10 +0530188 /* extra delays */
189 bool ce_xdelay;
190 bool avd_xdelay;
191 bool oe_xdelay;
192 bool we_xdelay;
193};
194
Jon Hunterc3be5b42013-02-21 13:46:22 -0600195struct gpmc_settings {
196 bool burst_wrap; /* enables wrap bursting */
197 bool burst_read; /* enables read page/burst mode */
198 bool burst_write; /* enables write page/burst mode */
199 bool device_nand; /* device is NAND */
200 bool sync_read; /* enables synchronous reads */
201 bool sync_write; /* enables synchronous writes */
202 bool wait_on_read; /* monitor wait on reads */
203 bool wait_on_write; /* monitor wait on writes */
204 u32 burst_len; /* page/burst length */
205 u32 device_width; /* device bus width (8 or 16 bit) */
206 u32 mux_add_data; /* multiplex address & data */
207 u32 wait_pin; /* wait-pin to be used */
208};
209
Afzal Mohammed246da262012-08-02 20:02:10 +0530210extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
Jon Hunterc3be5b42013-02-21 13:46:22 -0600211 struct gpmc_settings *gpmc_s,
212 struct gpmc_device_timings *dev_t);
Afzal Mohammed246da262012-08-02 20:02:10 +0530213
Afzal Mohammed52bd1382012-08-30 12:53:22 -0700214extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
Afzal Mohammed6b6c32f2012-08-30 12:53:23 -0700215extern int gpmc_get_client_irq(unsigned irq_config);
Afzal Mohammed52bd1382012-08-30 12:53:22 -0700216
Paul Walmsleyfd1dc872008-10-06 15:49:17 +0300217extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700218
219extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
Afzal Mohammed1b47ca12012-08-19 18:29:45 +0530220extern int gpmc_calc_divider(unsigned int sync_clk);
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700221extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
Jon Hunteraa8d4762013-02-21 15:25:23 -0600222extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
Imre Deakf37e4582006-09-25 12:41:33 +0300223extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
224extern void gpmc_cs_free(int cs);
Rajendra Nayaka2d3e7b2008-09-26 17:47:33 +0530225extern void omap3_gpmc_save_context(void);
226extern void omap3_gpmc_restore_context(void);
Jon Hunter3a544352013-02-21 13:00:21 -0600227extern int gpmc_configure(int cmd, int wval);
Jon Hunter8c8a77712013-02-20 15:53:12 -0600228extern void gpmc_read_settings_dt(struct device_node *np,
229 struct gpmc_settings *p);
Ivan Djelic8d602cf2012-04-26 14:17:49 +0200230
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700231#endif