David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/regmap.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/rtc.h> |
| 17 | #include <linux/pm.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/idr.h> |
| 20 | #include <linux/of_device.h> |
| 21 | #include <linux/of_irq.h> |
| 22 | #include <linux/spmi.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/spinlock.h> |
| 25 | #include <linux/alarmtimer.h> |
| 26 | |
| 27 | /* RTC/ALARM Register offsets */ |
| 28 | #define REG_OFFSET_ALARM_RW 0x40 |
| 29 | #define REG_OFFSET_ALARM_CTRL1 0x46 |
| 30 | #define REG_OFFSET_ALARM_CTRL2 0x48 |
| 31 | #define REG_OFFSET_RTC_WRITE 0x40 |
| 32 | #define REG_OFFSET_RTC_CTRL 0x46 |
| 33 | #define REG_OFFSET_RTC_READ 0x48 |
| 34 | #define REG_OFFSET_PERP_SUBTYPE 0x05 |
| 35 | |
| 36 | /* RTC_CTRL register bit fields */ |
| 37 | #define BIT_RTC_ENABLE BIT(7) |
| 38 | #define BIT_RTC_ALARM_ENABLE BIT(7) |
| 39 | #define BIT_RTC_ABORT_ENABLE BIT(0) |
| 40 | #define BIT_RTC_ALARM_CLEAR BIT(0) |
| 41 | |
| 42 | /* RTC/ALARM peripheral subtype values */ |
| 43 | #define RTC_PERPH_SUBTYPE 0x1 |
| 44 | #define ALARM_PERPH_SUBTYPE 0x3 |
| 45 | |
| 46 | #define NUM_8_BIT_RTC_REGS 0x4 |
| 47 | |
| 48 | #define TO_SECS(arr) (arr[0] | (arr[1] << 8) | (arr[2] << 16) | \ |
| 49 | (arr[3] << 24)) |
| 50 | |
| 51 | /* Module parameter to control power-on-alarm */ |
| 52 | bool poweron_alarm; |
| 53 | EXPORT_SYMBOL(poweron_alarm); |
| 54 | module_param(poweron_alarm, bool, 0644); |
| 55 | MODULE_PARM_DESC(poweron_alarm, "Enable/Disable power-on alarm"); |
| 56 | |
| 57 | /* rtc driver internal structure */ |
| 58 | struct qpnp_rtc { |
| 59 | u8 rtc_ctrl_reg; |
| 60 | u8 alarm_ctrl_reg1; |
| 61 | u16 rtc_base; |
| 62 | u16 alarm_base; |
| 63 | u32 rtc_write_enable; |
| 64 | u32 rtc_alarm_powerup; |
| 65 | int rtc_alarm_irq; |
| 66 | struct device *rtc_dev; |
| 67 | struct rtc_device *rtc; |
| 68 | struct platform_device *pdev; |
| 69 | struct regmap *regmap; |
| 70 | spinlock_t alarm_ctrl_lock; |
| 71 | }; |
| 72 | |
| 73 | static int qpnp_read_wrapper(struct qpnp_rtc *rtc_dd, u8 *rtc_val, |
| 74 | u16 base, int count) |
| 75 | { |
| 76 | int rc; |
| 77 | |
| 78 | rc = regmap_bulk_read(rtc_dd->regmap, base, rtc_val, count); |
| 79 | if (rc) { |
| 80 | dev_err(rtc_dd->rtc_dev, "SPMI read failed\n"); |
| 81 | return rc; |
| 82 | } |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | static int qpnp_write_wrapper(struct qpnp_rtc *rtc_dd, u8 *rtc_val, |
| 87 | u16 base, int count) |
| 88 | { |
| 89 | int rc; |
| 90 | |
| 91 | rc = regmap_bulk_write(rtc_dd->regmap, base, rtc_val, count); |
| 92 | if (rc) { |
| 93 | dev_err(rtc_dd->rtc_dev, "SPMI write failed\n"); |
| 94 | return rc; |
| 95 | } |
| 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static int |
| 101 | qpnp_rtc_set_time(struct device *dev, struct rtc_time *tm) |
| 102 | { |
| 103 | int rc; |
| 104 | unsigned long secs, irq_flags; |
| 105 | u8 value[4], reg = 0, alarm_enabled = 0, ctrl_reg; |
| 106 | u8 rtc_disabled = 0, rtc_ctrl_reg; |
| 107 | struct qpnp_rtc *rtc_dd = dev_get_drvdata(dev); |
| 108 | |
| 109 | rtc_tm_to_time(tm, &secs); |
| 110 | |
| 111 | value[0] = secs & 0xFF; |
| 112 | value[1] = (secs >> 8) & 0xFF; |
| 113 | value[2] = (secs >> 16) & 0xFF; |
| 114 | value[3] = (secs >> 24) & 0xFF; |
| 115 | |
| 116 | dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); |
| 117 | |
| 118 | spin_lock_irqsave(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 119 | ctrl_reg = rtc_dd->alarm_ctrl_reg1; |
| 120 | |
| 121 | if (ctrl_reg & BIT_RTC_ALARM_ENABLE) { |
| 122 | alarm_enabled = 1; |
| 123 | ctrl_reg &= ~BIT_RTC_ALARM_ENABLE; |
| 124 | rc = qpnp_write_wrapper(rtc_dd, &ctrl_reg, |
| 125 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 126 | if (rc) { |
| 127 | dev_err(dev, "Write to ALARM ctrl reg failed\n"); |
| 128 | goto rtc_rw_fail; |
| 129 | } |
| 130 | } else |
| 131 | spin_unlock_irqrestore(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 132 | |
| 133 | /* |
| 134 | * 32 bit seconds value is coverted to four 8 bit values |
| 135 | * |<------ 32 bit time value in seconds ------>| |
| 136 | * <- 8 bit ->|<- 8 bit ->|<- 8 bit ->|<- 8 bit ->| |
| 137 | * ---------------------------------------------- |
| 138 | * | BYTE[3] | BYTE[2] | BYTE[1] | BYTE[0] | |
| 139 | * ---------------------------------------------- |
| 140 | * |
| 141 | * RTC has four 8 bit registers for writing time in seconds: |
| 142 | * WDATA[3], WDATA[2], WDATA[1], WDATA[0] |
| 143 | * |
| 144 | * Write to the RTC registers should be done in following order |
| 145 | * Clear WDATA[0] register |
| 146 | * |
| 147 | * Write BYTE[1], BYTE[2] and BYTE[3] of time to |
| 148 | * RTC WDATA[3], WDATA[2], WDATA[1] registers |
| 149 | * |
| 150 | * Write BYTE[0] of time to RTC WDATA[0] register |
| 151 | * |
| 152 | * Clearing BYTE[0] and writing in the end will prevent any |
| 153 | * unintentional overflow from WDATA[0] to higher bytes during the |
| 154 | * write operation |
| 155 | */ |
| 156 | |
| 157 | /* Disable RTC H/w before writing on RTC register*/ |
| 158 | rtc_ctrl_reg = rtc_dd->rtc_ctrl_reg; |
| 159 | if (rtc_ctrl_reg & BIT_RTC_ENABLE) { |
| 160 | rtc_disabled = 1; |
| 161 | rtc_ctrl_reg &= ~BIT_RTC_ENABLE; |
| 162 | rc = qpnp_write_wrapper(rtc_dd, &rtc_ctrl_reg, |
| 163 | rtc_dd->rtc_base + REG_OFFSET_RTC_CTRL, 1); |
| 164 | if (rc) { |
| 165 | dev_err(dev, "Disabling of RTC control reg failed with error:%d\n", |
| 166 | rc); |
| 167 | goto rtc_rw_fail; |
| 168 | } |
| 169 | rtc_dd->rtc_ctrl_reg = rtc_ctrl_reg; |
| 170 | } |
| 171 | |
| 172 | /* Clear WDATA[0] */ |
| 173 | reg = 0x0; |
| 174 | rc = qpnp_write_wrapper(rtc_dd, ®, |
| 175 | rtc_dd->rtc_base + REG_OFFSET_RTC_WRITE, 1); |
| 176 | if (rc) { |
| 177 | dev_err(dev, "Write to RTC reg failed\n"); |
| 178 | goto rtc_rw_fail; |
| 179 | } |
| 180 | |
| 181 | /* Write to WDATA[3], WDATA[2] and WDATA[1] */ |
| 182 | rc = qpnp_write_wrapper(rtc_dd, &value[1], |
| 183 | rtc_dd->rtc_base + REG_OFFSET_RTC_WRITE + 1, 3); |
| 184 | if (rc) { |
| 185 | dev_err(dev, "Write to RTC reg failed\n"); |
| 186 | goto rtc_rw_fail; |
| 187 | } |
| 188 | |
| 189 | /* Write to WDATA[0] */ |
| 190 | rc = qpnp_write_wrapper(rtc_dd, value, |
| 191 | rtc_dd->rtc_base + REG_OFFSET_RTC_WRITE, 1); |
| 192 | if (rc) { |
| 193 | dev_err(dev, "Write to RTC reg failed\n"); |
| 194 | goto rtc_rw_fail; |
| 195 | } |
| 196 | |
| 197 | /* Enable RTC H/w after writing on RTC register*/ |
| 198 | if (rtc_disabled) { |
| 199 | rtc_ctrl_reg |= BIT_RTC_ENABLE; |
| 200 | rc = qpnp_write_wrapper(rtc_dd, &rtc_ctrl_reg, |
| 201 | rtc_dd->rtc_base + REG_OFFSET_RTC_CTRL, 1); |
| 202 | if (rc) { |
| 203 | dev_err(dev, "Enabling of RTC control reg failed with error:%d\n", |
| 204 | rc); |
| 205 | goto rtc_rw_fail; |
| 206 | } |
| 207 | rtc_dd->rtc_ctrl_reg = rtc_ctrl_reg; |
| 208 | } |
| 209 | |
| 210 | if (alarm_enabled) { |
| 211 | ctrl_reg |= BIT_RTC_ALARM_ENABLE; |
| 212 | rc = qpnp_write_wrapper(rtc_dd, &ctrl_reg, |
| 213 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 214 | if (rc) { |
| 215 | dev_err(dev, "Write to ALARM ctrl reg failed\n"); |
| 216 | goto rtc_rw_fail; |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | rtc_dd->alarm_ctrl_reg1 = ctrl_reg; |
| 221 | |
| 222 | rtc_rw_fail: |
| 223 | if (alarm_enabled) |
| 224 | spin_unlock_irqrestore(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 225 | |
| 226 | return rc; |
| 227 | } |
| 228 | |
| 229 | static int |
| 230 | qpnp_rtc_read_time(struct device *dev, struct rtc_time *tm) |
| 231 | { |
| 232 | int rc; |
| 233 | u8 value[4], reg; |
| 234 | unsigned long secs; |
| 235 | struct qpnp_rtc *rtc_dd = dev_get_drvdata(dev); |
| 236 | |
| 237 | rc = qpnp_read_wrapper(rtc_dd, value, |
| 238 | rtc_dd->rtc_base + REG_OFFSET_RTC_READ, |
| 239 | NUM_8_BIT_RTC_REGS); |
| 240 | if (rc) { |
| 241 | dev_err(dev, "Read from RTC reg failed\n"); |
| 242 | return rc; |
| 243 | } |
| 244 | |
| 245 | /* |
| 246 | * Read the LSB again and check if there has been a carry over |
| 247 | * If there is, redo the read operation |
| 248 | */ |
| 249 | rc = qpnp_read_wrapper(rtc_dd, ®, |
| 250 | rtc_dd->rtc_base + REG_OFFSET_RTC_READ, 1); |
| 251 | if (rc) { |
| 252 | dev_err(dev, "Read from RTC reg failed\n"); |
| 253 | return rc; |
| 254 | } |
| 255 | |
| 256 | if (reg < value[0]) { |
| 257 | rc = qpnp_read_wrapper(rtc_dd, value, |
| 258 | rtc_dd->rtc_base + REG_OFFSET_RTC_READ, |
| 259 | NUM_8_BIT_RTC_REGS); |
| 260 | if (rc) { |
| 261 | dev_err(dev, "Read from RTC reg failed\n"); |
| 262 | return rc; |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | secs = TO_SECS(value); |
| 267 | |
| 268 | rtc_time_to_tm(secs, tm); |
| 269 | |
| 270 | rc = rtc_valid_tm(tm); |
| 271 | if (rc) { |
| 272 | dev_err(dev, "Invalid time read from RTC\n"); |
| 273 | return rc; |
| 274 | } |
| 275 | |
| 276 | dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n", |
| 277 | secs, tm->tm_hour, tm->tm_min, tm->tm_sec, |
| 278 | tm->tm_mday, tm->tm_mon, tm->tm_year); |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | static int |
| 284 | qpnp_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
| 285 | { |
| 286 | int rc; |
| 287 | u8 value[4], ctrl_reg; |
| 288 | unsigned long secs, secs_rtc, irq_flags; |
| 289 | struct qpnp_rtc *rtc_dd = dev_get_drvdata(dev); |
| 290 | struct rtc_time rtc_tm; |
| 291 | |
| 292 | rtc_tm_to_time(&alarm->time, &secs); |
| 293 | |
| 294 | /* |
| 295 | * Read the current RTC time and verify if the alarm time is in the |
| 296 | * past. If yes, return invalid |
| 297 | */ |
| 298 | rc = qpnp_rtc_read_time(dev, &rtc_tm); |
| 299 | if (rc) { |
| 300 | dev_err(dev, "Unable to read RTC time\n"); |
| 301 | return -EINVAL; |
| 302 | } |
| 303 | |
| 304 | rtc_tm_to_time(&rtc_tm, &secs_rtc); |
| 305 | if (secs < secs_rtc) { |
| 306 | dev_err(dev, "Trying to set alarm in the past\n"); |
| 307 | return -EINVAL; |
| 308 | } |
| 309 | |
| 310 | value[0] = secs & 0xFF; |
| 311 | value[1] = (secs >> 8) & 0xFF; |
| 312 | value[2] = (secs >> 16) & 0xFF; |
| 313 | value[3] = (secs >> 24) & 0xFF; |
| 314 | |
| 315 | spin_lock_irqsave(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 316 | |
| 317 | rc = qpnp_write_wrapper(rtc_dd, value, |
| 318 | rtc_dd->alarm_base + REG_OFFSET_ALARM_RW, |
| 319 | NUM_8_BIT_RTC_REGS); |
| 320 | if (rc) { |
| 321 | dev_err(dev, "Write to ALARM reg failed\n"); |
| 322 | goto rtc_rw_fail; |
| 323 | } |
| 324 | |
| 325 | ctrl_reg = (alarm->enabled) ? |
| 326 | (rtc_dd->alarm_ctrl_reg1 | BIT_RTC_ALARM_ENABLE) : |
| 327 | (rtc_dd->alarm_ctrl_reg1 & ~BIT_RTC_ALARM_ENABLE); |
| 328 | |
| 329 | rc = qpnp_write_wrapper(rtc_dd, &ctrl_reg, |
| 330 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 331 | if (rc) { |
| 332 | dev_err(dev, "Write to ALARM cntrol reg failed\n"); |
| 333 | goto rtc_rw_fail; |
| 334 | } |
| 335 | |
| 336 | rtc_dd->alarm_ctrl_reg1 = ctrl_reg; |
| 337 | |
| 338 | dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", |
| 339 | alarm->time.tm_hour, alarm->time.tm_min, |
| 340 | alarm->time.tm_sec, alarm->time.tm_mday, |
| 341 | alarm->time.tm_mon, alarm->time.tm_year); |
| 342 | rtc_rw_fail: |
| 343 | spin_unlock_irqrestore(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 344 | return rc; |
| 345 | } |
| 346 | |
| 347 | static int |
| 348 | qpnp_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
| 349 | { |
| 350 | int rc; |
| 351 | u8 value[4]; |
| 352 | unsigned long secs; |
| 353 | struct qpnp_rtc *rtc_dd = dev_get_drvdata(dev); |
| 354 | |
| 355 | rc = qpnp_read_wrapper(rtc_dd, value, |
| 356 | rtc_dd->alarm_base + REG_OFFSET_ALARM_RW, |
| 357 | NUM_8_BIT_RTC_REGS); |
| 358 | if (rc) { |
| 359 | dev_err(dev, "Read from ALARM reg failed\n"); |
| 360 | return rc; |
| 361 | } |
| 362 | |
| 363 | secs = TO_SECS(value); |
| 364 | rtc_time_to_tm(secs, &alarm->time); |
| 365 | |
| 366 | rc = rtc_valid_tm(&alarm->time); |
| 367 | if (rc) { |
| 368 | dev_err(dev, "Invalid time read from RTC\n"); |
| 369 | return rc; |
| 370 | } |
| 371 | |
| 372 | dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", |
| 373 | alarm->time.tm_hour, alarm->time.tm_min, |
| 374 | alarm->time.tm_sec, alarm->time.tm_mday, |
| 375 | alarm->time.tm_mon, alarm->time.tm_year); |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | |
| 381 | static int |
| 382 | qpnp_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
| 383 | { |
| 384 | int rc; |
| 385 | unsigned long irq_flags; |
| 386 | struct qpnp_rtc *rtc_dd = dev_get_drvdata(dev); |
| 387 | u8 ctrl_reg; |
| 388 | u8 value[4] = {0}; |
| 389 | |
| 390 | spin_lock_irqsave(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 391 | ctrl_reg = rtc_dd->alarm_ctrl_reg1; |
| 392 | ctrl_reg = enabled ? (ctrl_reg | BIT_RTC_ALARM_ENABLE) : |
| 393 | (ctrl_reg & ~BIT_RTC_ALARM_ENABLE); |
| 394 | |
| 395 | rc = qpnp_write_wrapper(rtc_dd, &ctrl_reg, |
| 396 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 397 | if (rc) { |
| 398 | dev_err(dev, "Write to ALARM control reg failed\n"); |
| 399 | goto rtc_rw_fail; |
| 400 | } |
| 401 | |
| 402 | rtc_dd->alarm_ctrl_reg1 = ctrl_reg; |
| 403 | |
| 404 | /* Clear Alarm register */ |
| 405 | if (!enabled) { |
| 406 | rc = qpnp_write_wrapper(rtc_dd, value, |
| 407 | rtc_dd->alarm_base + REG_OFFSET_ALARM_RW, |
| 408 | NUM_8_BIT_RTC_REGS); |
| 409 | if (rc) |
| 410 | dev_err(dev, "Clear ALARM value reg failed\n"); |
| 411 | } |
| 412 | |
| 413 | rtc_rw_fail: |
| 414 | spin_unlock_irqrestore(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 415 | return rc; |
| 416 | } |
| 417 | |
| 418 | static const struct rtc_class_ops qpnp_rtc_ro_ops = { |
| 419 | .read_time = qpnp_rtc_read_time, |
| 420 | .set_alarm = qpnp_rtc_set_alarm, |
| 421 | .read_alarm = qpnp_rtc_read_alarm, |
| 422 | .alarm_irq_enable = qpnp_rtc_alarm_irq_enable, |
| 423 | }; |
| 424 | |
| 425 | static const struct rtc_class_ops qpnp_rtc_rw_ops = { |
| 426 | .read_time = qpnp_rtc_read_time, |
| 427 | .set_alarm = qpnp_rtc_set_alarm, |
| 428 | .read_alarm = qpnp_rtc_read_alarm, |
| 429 | .alarm_irq_enable = qpnp_rtc_alarm_irq_enable, |
| 430 | .set_time = qpnp_rtc_set_time, |
| 431 | }; |
| 432 | |
| 433 | static irqreturn_t qpnp_alarm_trigger(int irq, void *dev_id) |
| 434 | { |
| 435 | struct qpnp_rtc *rtc_dd = dev_id; |
| 436 | u8 ctrl_reg; |
| 437 | int rc; |
| 438 | unsigned long irq_flags; |
| 439 | |
| 440 | rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF); |
| 441 | |
| 442 | spin_lock_irqsave(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 443 | |
| 444 | /* Clear the alarm enable bit */ |
| 445 | ctrl_reg = rtc_dd->alarm_ctrl_reg1; |
| 446 | ctrl_reg &= ~BIT_RTC_ALARM_ENABLE; |
| 447 | |
| 448 | rc = qpnp_write_wrapper(rtc_dd, &ctrl_reg, |
| 449 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 450 | if (rc) { |
| 451 | spin_unlock_irqrestore(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 452 | dev_err(rtc_dd->rtc_dev, |
| 453 | "Write to ALARM control reg failed\n"); |
| 454 | goto rtc_alarm_handled; |
| 455 | } |
| 456 | |
| 457 | rtc_dd->alarm_ctrl_reg1 = ctrl_reg; |
| 458 | spin_unlock_irqrestore(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 459 | |
| 460 | /* Set ALARM_CLR bit */ |
| 461 | ctrl_reg = 0x1; |
| 462 | rc = qpnp_write_wrapper(rtc_dd, &ctrl_reg, |
| 463 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL2, 1); |
| 464 | if (rc) |
| 465 | dev_err(rtc_dd->rtc_dev, |
| 466 | "Write to ALARM control reg failed\n"); |
| 467 | |
| 468 | rtc_alarm_handled: |
| 469 | return IRQ_HANDLED; |
| 470 | } |
| 471 | |
| 472 | static int qpnp_rtc_probe(struct platform_device *pdev) |
| 473 | { |
| 474 | const struct rtc_class_ops *rtc_ops = &qpnp_rtc_ro_ops; |
| 475 | int rc; |
| 476 | u8 subtype; |
| 477 | struct qpnp_rtc *rtc_dd; |
| 478 | unsigned int base; |
| 479 | struct device_node *child; |
| 480 | |
| 481 | rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL); |
| 482 | if (rtc_dd == NULL) |
| 483 | return -ENOMEM; |
| 484 | |
| 485 | rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 486 | if (!rtc_dd->regmap) { |
| 487 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 488 | return -EINVAL; |
| 489 | } |
| 490 | |
| 491 | /* Get the rtc write property */ |
| 492 | rc = of_property_read_u32(pdev->dev.of_node, "qcom,qpnp-rtc-write", |
| 493 | &rtc_dd->rtc_write_enable); |
| 494 | if (rc && rc != -EINVAL) { |
| 495 | dev_err(&pdev->dev, |
| 496 | "Error reading rtc_write_enable property %d\n", rc); |
| 497 | return rc; |
| 498 | } |
| 499 | |
| 500 | rc = of_property_read_u32(pdev->dev.of_node, |
| 501 | "qcom,qpnp-rtc-alarm-pwrup", |
| 502 | &rtc_dd->rtc_alarm_powerup); |
| 503 | if (rc && rc != -EINVAL) { |
| 504 | dev_err(&pdev->dev, |
| 505 | "Error reading rtc_alarm_powerup property %d\n", rc); |
| 506 | return rc; |
| 507 | } |
| 508 | |
| 509 | /* Initialise spinlock to protect RTC control register */ |
| 510 | spin_lock_init(&rtc_dd->alarm_ctrl_lock); |
| 511 | |
| 512 | rtc_dd->rtc_dev = &(pdev->dev); |
| 513 | rtc_dd->pdev = pdev; |
| 514 | |
| 515 | |
| 516 | if (of_get_available_child_count(pdev->dev.of_node) == 0) { |
| 517 | pr_err("no child nodes\n"); |
| 518 | rc = -ENXIO; |
| 519 | goto fail_rtc_enable; |
| 520 | } |
| 521 | |
| 522 | /* Get RTC/ALARM resources */ |
| 523 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
| 524 | rc = of_property_read_u32(child, "reg", &base); |
| 525 | if (rc < 0) { |
| 526 | dev_err(&pdev->dev, |
| 527 | "Couldn't find reg in node = %s rc = %d\n", |
| 528 | child->full_name, rc); |
| 529 | goto fail_rtc_enable; |
| 530 | } |
| 531 | |
| 532 | rc = qpnp_read_wrapper(rtc_dd, &subtype, |
| 533 | base + REG_OFFSET_PERP_SUBTYPE, 1); |
| 534 | if (rc) { |
| 535 | dev_err(&pdev->dev, |
| 536 | "Peripheral subtype read failed\n"); |
| 537 | goto fail_rtc_enable; |
| 538 | } |
| 539 | |
| 540 | switch (subtype) { |
| 541 | case RTC_PERPH_SUBTYPE: |
| 542 | rtc_dd->rtc_base = base; |
| 543 | break; |
| 544 | case ALARM_PERPH_SUBTYPE: |
| 545 | rtc_dd->alarm_base = base; |
| 546 | rtc_dd->rtc_alarm_irq = of_irq_get(child, 0); |
| 547 | if (rtc_dd->rtc_alarm_irq < 0) { |
| 548 | dev_err(&pdev->dev, "ALARM IRQ absent\n"); |
| 549 | rc = -ENXIO; |
| 550 | goto fail_rtc_enable; |
| 551 | } |
| 552 | break; |
| 553 | default: |
| 554 | dev_err(&pdev->dev, "Invalid peripheral subtype\n"); |
| 555 | rc = -EINVAL; |
| 556 | goto fail_rtc_enable; |
| 557 | } |
| 558 | } |
| 559 | |
| 560 | rc = qpnp_read_wrapper(rtc_dd, &rtc_dd->rtc_ctrl_reg, |
| 561 | rtc_dd->rtc_base + REG_OFFSET_RTC_CTRL, 1); |
| 562 | if (rc) { |
| 563 | dev_err(&pdev->dev, "Read from RTC control reg failed\n"); |
| 564 | goto fail_rtc_enable; |
| 565 | } |
| 566 | |
| 567 | if (!(rtc_dd->rtc_ctrl_reg & BIT_RTC_ENABLE)) { |
| 568 | dev_err(&pdev->dev, "RTC h/w disabled, rtc not registered\n"); |
| 569 | goto fail_rtc_enable; |
| 570 | } |
| 571 | |
| 572 | rc = qpnp_read_wrapper(rtc_dd, &rtc_dd->alarm_ctrl_reg1, |
| 573 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 574 | if (rc) { |
| 575 | dev_err(&pdev->dev, "Read from Alarm control reg failed\n"); |
| 576 | goto fail_rtc_enable; |
| 577 | } |
| 578 | /* Enable abort enable feature */ |
| 579 | rtc_dd->alarm_ctrl_reg1 |= BIT_RTC_ABORT_ENABLE; |
| 580 | rc = qpnp_write_wrapper(rtc_dd, &rtc_dd->alarm_ctrl_reg1, |
| 581 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 582 | if (rc) { |
| 583 | dev_err(&pdev->dev, "SPMI write failed!\n"); |
| 584 | goto fail_rtc_enable; |
| 585 | } |
| 586 | |
| 587 | if (rtc_dd->rtc_write_enable == true) |
| 588 | rtc_ops = &qpnp_rtc_rw_ops; |
| 589 | |
| 590 | dev_set_drvdata(&pdev->dev, rtc_dd); |
| 591 | |
| 592 | /* Register the RTC device */ |
| 593 | rtc_dd->rtc = rtc_device_register("qpnp_rtc", &pdev->dev, |
| 594 | rtc_ops, THIS_MODULE); |
| 595 | if (IS_ERR(rtc_dd->rtc)) { |
| 596 | dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n", |
| 597 | __func__, PTR_ERR(rtc_dd->rtc)); |
| 598 | rc = PTR_ERR(rtc_dd->rtc); |
| 599 | goto fail_rtc_enable; |
| 600 | } |
| 601 | |
| 602 | /* Init power_on_alarm after adding rtc device */ |
| 603 | power_on_alarm_init(); |
| 604 | |
| 605 | /* Request the alarm IRQ */ |
| 606 | rc = request_any_context_irq(rtc_dd->rtc_alarm_irq, |
| 607 | qpnp_alarm_trigger, IRQF_TRIGGER_RISING, |
| 608 | "qpnp_rtc_alarm", rtc_dd); |
| 609 | if (rc) { |
| 610 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc); |
| 611 | goto fail_req_irq; |
| 612 | } |
| 613 | |
| 614 | device_init_wakeup(&pdev->dev, 1); |
| 615 | enable_irq_wake(rtc_dd->rtc_alarm_irq); |
| 616 | |
| 617 | dev_dbg(&pdev->dev, "Probe success !!\n"); |
| 618 | |
| 619 | return 0; |
| 620 | |
| 621 | fail_req_irq: |
| 622 | rtc_device_unregister(rtc_dd->rtc); |
| 623 | fail_rtc_enable: |
| 624 | dev_set_drvdata(&pdev->dev, NULL); |
| 625 | |
| 626 | return rc; |
| 627 | } |
| 628 | |
| 629 | static int qpnp_rtc_remove(struct platform_device *pdev) |
| 630 | { |
| 631 | struct qpnp_rtc *rtc_dd = dev_get_drvdata(&pdev->dev); |
| 632 | |
| 633 | device_init_wakeup(&pdev->dev, 0); |
| 634 | free_irq(rtc_dd->rtc_alarm_irq, rtc_dd); |
| 635 | rtc_device_unregister(rtc_dd->rtc); |
| 636 | dev_set_drvdata(&pdev->dev, NULL); |
| 637 | |
| 638 | return 0; |
| 639 | } |
| 640 | |
| 641 | static void qpnp_rtc_shutdown(struct platform_device *pdev) |
| 642 | { |
| 643 | u8 value[4] = {0}; |
| 644 | u8 reg; |
| 645 | int rc; |
| 646 | unsigned long irq_flags; |
| 647 | struct qpnp_rtc *rtc_dd; |
| 648 | bool rtc_alarm_powerup; |
| 649 | |
| 650 | if (!pdev) { |
| 651 | pr_err("qpnp-rtc: spmi device not found\n"); |
| 652 | return; |
| 653 | } |
| 654 | rtc_dd = dev_get_drvdata(&pdev->dev); |
| 655 | if (!rtc_dd) { |
| 656 | pr_err("qpnp-rtc: rtc driver data not found\n"); |
| 657 | return; |
| 658 | } |
| 659 | rtc_alarm_powerup = rtc_dd->rtc_alarm_powerup; |
| 660 | if (!rtc_alarm_powerup && !poweron_alarm) { |
| 661 | spin_lock_irqsave(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 662 | dev_dbg(&pdev->dev, "Disabling alarm interrupts\n"); |
| 663 | |
| 664 | /* Disable RTC alarms */ |
| 665 | reg = rtc_dd->alarm_ctrl_reg1; |
| 666 | reg &= ~BIT_RTC_ALARM_ENABLE; |
| 667 | rc = qpnp_write_wrapper(rtc_dd, ®, |
| 668 | rtc_dd->alarm_base + REG_OFFSET_ALARM_CTRL1, 1); |
| 669 | if (rc) { |
| 670 | dev_err(rtc_dd->rtc_dev, "SPMI write failed\n"); |
| 671 | goto fail_alarm_disable; |
| 672 | } |
| 673 | |
| 674 | /* Clear Alarm register */ |
| 675 | rc = qpnp_write_wrapper(rtc_dd, value, |
| 676 | rtc_dd->alarm_base + REG_OFFSET_ALARM_RW, |
| 677 | NUM_8_BIT_RTC_REGS); |
| 678 | if (rc) |
| 679 | dev_err(rtc_dd->rtc_dev, "SPMI write failed\n"); |
| 680 | |
| 681 | fail_alarm_disable: |
| 682 | spin_unlock_irqrestore(&rtc_dd->alarm_ctrl_lock, irq_flags); |
| 683 | } |
| 684 | } |
| 685 | |
| 686 | static const struct of_device_id spmi_match_table[] = { |
| 687 | { |
| 688 | .compatible = "qcom,qpnp-rtc", |
| 689 | }, |
| 690 | {} |
| 691 | }; |
| 692 | |
| 693 | static struct platform_driver qpnp_rtc_driver = { |
| 694 | .probe = qpnp_rtc_probe, |
| 695 | .remove = qpnp_rtc_remove, |
| 696 | .shutdown = qpnp_rtc_shutdown, |
| 697 | .driver = { |
| 698 | .name = "qcom,qpnp-rtc", |
| 699 | .owner = THIS_MODULE, |
| 700 | .of_match_table = spmi_match_table, |
| 701 | }, |
| 702 | }; |
| 703 | |
| 704 | static int __init qpnp_rtc_init(void) |
| 705 | { |
| 706 | return platform_driver_register(&qpnp_rtc_driver); |
| 707 | } |
| 708 | module_init(qpnp_rtc_init); |
| 709 | |
| 710 | static void __exit qpnp_rtc_exit(void) |
| 711 | { |
| 712 | platform_driver_unregister(&qpnp_rtc_driver); |
| 713 | } |
| 714 | module_exit(qpnp_rtc_exit); |
| 715 | |
| 716 | MODULE_DESCRIPTION("SMPI PMIC RTC driver"); |
| 717 | MODULE_LICENSE("GPL v2"); |