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gerrit-public.fairphone.software / kernel / msm-4.9 / 3e1839e91dfcb50cf5c1c9a7ac2ed61891400b92 / . / arch / arm / boot / dts / r8a7792.dtsi
blob: ad895f8b23531bb6f88b3484116d7e4b6c9f1808 [file] [log] [blame]
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a15";
28 reg = <0>;
29 clock-frequency = <1000000000>;
30 clocks = <&cpg_clocks R8A7792_CLK_Z>;
31 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
32 next-level-cache = <&L2_CA15>;
33 };
34
35 L2_CA15: cache-controller@0 {
36 compatible = "cache";
37 reg = <0>;
38 cache-unified;
39 cache-level = <2>;
40 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
41 };
42 };
43
44 soc {
45 compatible = "simple-bus";
46 interrupt-parent = <&gic>;
47
48 #address-cells = <2>;
49 #size-cells = <2>;
50 ranges;
51
52 gic: interrupt-controller@f1001000 {
53 compatible = "arm,gic-400";
54 #interrupt-cells = <3>;
55 interrupt-controller;
56 reg = <0 0xf1001000 0 0x1000>,
57 <0 0xf1002000 0 0x1000>,
58 <0 0xf1004000 0 0x2000>,
59 <0 0xf1006000 0 0x2000>;
60 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
61 IRQ_TYPE_LEVEL_HIGH)>;
62 };
63
Sergei Shtylyov56efdbe52016-06-13 00:12:06 +0300[diff] [blame]64 irqc: interrupt-controller@e61c0000 {
65 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
66 #interrupt-cells = <2>;
67 interrupt-controller;
68 reg = <0 0xe61c0000 0 0x200>;
69 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
73 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
74 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
75 };
76
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]77 timer {
78 compatible = "arm,armv7-timer";
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
80 IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
82 IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
84 IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
86 IRQ_TYPE_LEVEL_LOW)>;
87 };
88
89 sysc: system-controller@e6180000 {
90 compatible = "renesas,r8a7792-sysc";
91 reg = <0 0xe6180000 0 0x0200>;
92 #power-domain-cells = <1>;
93 };
94
Sergei Shtylyovfdf8ec02016-06-13 00:08:18 +0300[diff] [blame]95 dmac0: dma-controller@e6700000 {
96 compatible = "renesas,dmac-r8a7792",
97 "renesas,rcar-dmac";
98 reg = <0 0xe6700000 0 0x20000>;
99 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
102 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
103 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
104 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
105 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
111 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
112 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
113 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
114 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-names = "error",
116 "ch0", "ch1", "ch2", "ch3",
117 "ch4", "ch5", "ch6", "ch7",
118 "ch8", "ch9", "ch10", "ch11",
119 "ch12", "ch13", "ch14";
120 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
121 clock-names = "fck";
122 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
123 #dma-cells = <1>;
124 dma-channels = <15>;
125 };
126
127 dmac1: dma-controller@e6720000 {
128 compatible = "renesas,dmac-r8a7792",
129 "renesas,rcar-dmac";
130 reg = <0 0xe6720000 0 0x20000>;
131 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
132 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
133 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
134 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
135 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
136 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
138 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
145 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
146 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-names = "error",
148 "ch0", "ch1", "ch2", "ch3",
149 "ch4", "ch5", "ch6", "ch7",
150 "ch8", "ch9", "ch10", "ch11",
151 "ch12", "ch13", "ch14";
152 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
153 clock-names = "fck";
154 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
155 #dma-cells = <1>;
156 dma-channels = <15>;
157 };
158
Sergei Shtylyove66796b2016-06-13 00:09:42 +0300[diff] [blame]159 scif0: serial@e6e60000 {
160 compatible = "renesas,scif-r8a7792",
161 "renesas,rcar-gen2-scif", "renesas,scif";
162 reg = <0 0xe6e60000 0 64>;
163 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
165 <&scif_clk>;
166 clock-names = "fck", "brg_int", "scif_clk";
167 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
168 <&dmac1 0x29>, <&dmac1 0x2a>;
169 dma-names = "tx", "rx", "tx", "rx";
170 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
171 status = "disabled";
172 };
173
174 scif1: serial@e6e68000 {
175 compatible = "renesas,scif-r8a7792",
176 "renesas,rcar-gen2-scif", "renesas,scif";
177 reg = <0 0xe6e68000 0 64>;
178 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
180 <&scif_clk>;
181 clock-names = "fck", "brg_int", "scif_clk";
182 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
183 <&dmac1 0x2d>, <&dmac1 0x2e>;
184 dma-names = "tx", "rx", "tx", "rx";
185 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
186 status = "disabled";
187 };
188
189 scif2: serial@e6e58000 {
190 compatible = "renesas,scif-r8a7792",
191 "renesas,rcar-gen2-scif", "renesas,scif";
192 reg = <0 0xe6e58000 0 64>;
193 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
195 <&scif_clk>;
196 clock-names = "fck", "brg_int", "scif_clk";
197 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
198 <&dmac1 0x2b>, <&dmac1 0x2c>;
199 dma-names = "tx", "rx", "tx", "rx";
200 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
201 status = "disabled";
202 };
203
204 scif3: serial@e6ea8000 {
205 compatible = "renesas,scif-r8a7792",
206 "renesas,rcar-gen2-scif", "renesas,scif";
207 reg = <0 0xe6ea8000 0 64>;
208 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
210 <&scif_clk>;
211 clock-names = "fck", "brg_int", "scif_clk";
212 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
213 <&dmac1 0x2f>, <&dmac1 0x30>;
214 dma-names = "tx", "rx", "tx", "rx";
215 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
216 status = "disabled";
217 };
218
219 hscif0: serial@e62c0000 {
220 compatible = "renesas,hscif-r8a7792",
221 "renesas,rcar-gen2-hscif", "renesas,hscif";
222 reg = <0 0xe62c0000 0 96>;
223 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
225 <&scif_clk>;
226 clock-names = "fck", "brg_int", "scif_clk";
227 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
228 <&dmac1 0x39>, <&dmac1 0x3a>;
229 dma-names = "tx", "rx", "tx", "rx";
230 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
231 status = "disabled";
232 };
233
234 hscif1: serial@e62c8000 {
235 compatible = "renesas,hscif-r8a7792",
236 "renesas,rcar-gen2-hscif", "renesas,hscif";
237 reg = <0 0xe62c8000 0 96>;
238 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
240 <&scif_clk>;
241 clock-names = "fck", "brg_int", "scif_clk";
242 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
243 <&dmac1 0x4d>, <&dmac1 0x4e>;
244 dma-names = "tx", "rx", "tx", "rx";
245 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
246 status = "disabled";
247 };
248
Sergei Shtylyov3e1839e2016-06-17 01:03:53 +0300[diff] [blame^]249 jpu: jpeg-codec@fe980000 {
250 compatible = "renesas,jpu-r8a7792",
251 "renesas,rcar-gen2-jpu";
252 reg = <0 0xfe980000 0 0x10300>;
253 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
255 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
256 };
257
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]258 /* Special CPG clocks */
259 cpg_clocks: cpg_clocks@e6150000 {
260 compatible = "renesas,r8a7792-cpg-clocks",
261 "renesas,rcar-gen2-cpg-clocks";
262 reg = <0 0xe6150000 0 0x1000>;
263 clocks = <&extal_clk>;
264 #clock-cells = <1>;
265 clock-output-names = "main", "pll0", "pll1", "pll3",
266 "lb", "qspi", "z", "adsp";
267 #power-domain-cells = <0>;
268 };
269
270 /* Fixed factor clocks */
271 zs_clk: zs {
272 compatible = "fixed-factor-clock";
273 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
274 #clock-cells = <0>;
275 clock-div = <6>;
276 clock-mult = <1>;
277 };
278 p_clk: p {
279 compatible = "fixed-factor-clock";
280 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
281 #clock-cells = <0>;
282 clock-div = <24>;
283 clock-mult = <1>;
284 };
285 cp_clk: cp {
286 compatible = "fixed-factor-clock";
287 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
288 #clock-cells = <0>;
289 clock-div = <48>;
290 clock-mult = <1>;
291 };
Sergei Shtylyoveebc8e22016-06-17 01:02:48 +0300[diff] [blame]292 m2_clk: m2 {
293 compatible = "fixed-factor-clock";
294 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
295 #clock-cells = <0>;
296 clock-div = <8>;
297 clock-mult = <1>;
298 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]299
300 /* Gate clocks */
Sergei Shtylyoveebc8e22016-06-17 01:02:48 +0300[diff] [blame]301 mstp1_clks: mstp1_clks@e6150134 {
302 compatible = "renesas,r8a7792-mstp-clocks",
303 "renesas,cpg-mstp-clocks";
304 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
305 clocks = <&m2_clk>;
306 #clock-cells = <1>;
307 clock-indices = <R8A7792_CLK_JPU>;
308 clock-output-names = "jpu";
309 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]310 mstp2_clks: mstp2_clks@e6150138 {
311 compatible = "renesas,r8a7792-mstp-clocks",
312 "renesas,cpg-mstp-clocks";
313 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
314 clocks = <&zs_clk>, <&zs_clk>;
315 #clock-cells = <1>;
316 clock-indices = <
317 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
318 >;
319 clock-output-names = "sys-dmac1", "sys-dmac0";
320 };
321 mstp4_clks: mstp4_clks@e6150140 {
322 compatible = "renesas,r8a7792-mstp-clocks",
323 "renesas,cpg-mstp-clocks";
324 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
325 clocks = <&cp_clk>;
326 #clock-cells = <1>;
327 clock-indices = <R8A7792_CLK_IRQC>;
328 clock-output-names = "irqc";
329 };
330 mstp7_clks: mstp7_clks@e615014c {
331 compatible = "renesas,r8a7792-mstp-clocks",
332 "renesas,cpg-mstp-clocks";
333 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
334 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
335 <&p_clk>, <&p_clk>;
336 #clock-cells = <1>;
337 clock-indices = <
338 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
339 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
340 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
341 >;
342 clock-output-names = "hscif1", "hscif0", "scif3",
343 "scif2", "scif1", "scif0";
344 };
345 };
346
347 /* External root clock */
348 extal_clk: extal {
349 compatible = "fixed-clock";
350 #clock-cells = <0>;
351 /* This value must be overridden by the board. */
352 clock-frequency = <0>;
353 };
354
355 /* External SCIF clock */
356 scif_clk: scif {
357 compatible = "fixed-clock";
358 #clock-cells = <0>;
359 /* This value must be overridden by the board. */
360 clock-frequency = <0>;
361 };
362};