Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of version 2 of the GNU General Public License as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * Register definitions taken from original Realtek rtl8723au driver |
| 14 | */ |
| 15 | |
| 16 | #include <asm/byteorder.h> |
| 17 | |
| 18 | #define RTL8XXXU_DEBUG_REG_WRITE 0x01 |
| 19 | #define RTL8XXXU_DEBUG_REG_READ 0x02 |
| 20 | #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 |
| 21 | #define RTL8XXXU_DEBUG_RFREG_READ 0x08 |
| 22 | #define RTL8XXXU_DEBUG_CHANNEL 0x10 |
| 23 | #define RTL8XXXU_DEBUG_TX 0x20 |
| 24 | #define RTL8XXXU_DEBUG_TX_DUMP 0x40 |
| 25 | #define RTL8XXXU_DEBUG_RX 0x80 |
| 26 | #define RTL8XXXU_DEBUG_RX_DUMP 0x100 |
| 27 | #define RTL8XXXU_DEBUG_USB 0x200 |
| 28 | #define RTL8XXXU_DEBUG_KEY 0x400 |
| 29 | #define RTL8XXXU_DEBUG_H2C 0x800 |
| 30 | #define RTL8XXXU_DEBUG_ACTION 0x1000 |
| 31 | #define RTL8XXXU_DEBUG_EFUSE 0x2000 |
| 32 | |
| 33 | #define RTW_USB_CONTROL_MSG_TIMEOUT 500 |
| 34 | #define RTL8XXXU_MAX_REG_POLL 500 |
| 35 | #define USB_INTR_CONTENT_LENGTH 56 |
| 36 | |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 37 | #define RTL8XXXU_OUT_ENDPOINTS 4 |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 38 | |
| 39 | #define REALTEK_USB_READ 0xc0 |
| 40 | #define REALTEK_USB_WRITE 0x40 |
| 41 | #define REALTEK_USB_CMD_REQ 0x05 |
| 42 | #define REALTEK_USB_CMD_IDX 0x00 |
| 43 | |
| 44 | #define TX_TOTAL_PAGE_NUM 0xf8 |
| 45 | /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ |
| 46 | #define TX_PAGE_NUM_PUBQ 0xe7 |
| 47 | #define TX_PAGE_NUM_HI_PQ 0x0c |
| 48 | #define TX_PAGE_NUM_LO_PQ 0x02 |
| 49 | #define TX_PAGE_NUM_NORM_PQ 0x02 |
| 50 | |
| 51 | #define RTL_FW_PAGE_SIZE 4096 |
| 52 | #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 |
| 53 | |
| 54 | #define RTL8723A_CHANNEL_GROUPS 3 |
| 55 | #define RTL8723A_MAX_RF_PATHS 2 |
| 56 | #define RF6052_MAX_TX_PWR 0x3f |
| 57 | |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 58 | #define EFUSE_MAP_LEN 512 |
| 59 | #define EFUSE_MAX_SECTION_8723A 64 |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 60 | #define EFUSE_REAL_CONTENT_LEN_8723A 512 |
| 61 | #define EFUSE_BT_MAP_LEN_8723A 1024 |
| 62 | #define EFUSE_MAX_WORD_UNIT 4 |
| 63 | |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 64 | enum rtl8xxxu_rx_type { |
| 65 | RX_TYPE_DATA_PKT = 0, |
| 66 | RX_TYPE_C2H = 1, |
| 67 | RX_TYPE_ERROR = -1 |
| 68 | }; |
| 69 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 70 | struct rtl8xxxu_rx_desc { |
| 71 | #ifdef __LITTLE_ENDIAN |
| 72 | u32 pktlen:14; |
| 73 | u32 crc32:1; |
| 74 | u32 icverr:1; |
| 75 | u32 drvinfo_sz:4; |
| 76 | u32 security:3; |
| 77 | u32 qos:1; |
| 78 | u32 shift:2; |
| 79 | u32 phy_stats:1; |
| 80 | u32 swdec:1; |
| 81 | u32 ls:1; |
| 82 | u32 fs:1; |
| 83 | u32 eor:1; |
| 84 | u32 own:1; |
| 85 | |
| 86 | u32 macid:5; |
| 87 | u32 tid:4; |
| 88 | u32 hwrsvd:4; |
| 89 | u32 amsdu:1; |
| 90 | u32 paggr:1; |
| 91 | u32 faggr:1; |
| 92 | u32 a1fit:4; |
| 93 | u32 a2fit:4; |
| 94 | u32 pam:1; |
| 95 | u32 pwr:1; |
| 96 | u32 md:1; |
| 97 | u32 mf:1; |
| 98 | u32 type:2; |
| 99 | u32 mc:1; |
| 100 | u32 bc:1; |
| 101 | |
| 102 | u32 seq:12; |
| 103 | u32 frag:4; |
| 104 | u32 nextpktlen:14; |
| 105 | u32 nextind:1; |
| 106 | u32 reserved0:1; |
| 107 | |
| 108 | u32 rxmcs:6; |
| 109 | u32 rxht:1; |
| 110 | u32 gf:1; |
| 111 | u32 splcp:1; |
| 112 | u32 bw:1; |
| 113 | u32 htc:1; |
| 114 | u32 eosp:1; |
| 115 | u32 bssidfit:2; |
| 116 | u32 reserved1:16; |
| 117 | u32 unicastwake:1; |
| 118 | u32 magicwake:1; |
| 119 | |
| 120 | u32 pattern0match:1; |
| 121 | u32 pattern1match:1; |
| 122 | u32 pattern2match:1; |
| 123 | u32 pattern3match:1; |
| 124 | u32 pattern4match:1; |
| 125 | u32 pattern5match:1; |
| 126 | u32 pattern6match:1; |
| 127 | u32 pattern7match:1; |
| 128 | u32 pattern8match:1; |
| 129 | u32 pattern9match:1; |
| 130 | u32 patternamatch:1; |
| 131 | u32 patternbmatch:1; |
| 132 | u32 patterncmatch:1; |
| 133 | u32 reserved2:19; |
| 134 | #else |
| 135 | u32 own:1; |
| 136 | u32 eor:1; |
| 137 | u32 fs:1; |
| 138 | u32 ls:1; |
| 139 | u32 swdec:1; |
| 140 | u32 phy_stats:1; |
| 141 | u32 shift:2; |
| 142 | u32 qos:1; |
| 143 | u32 security:3; |
| 144 | u32 drvinfo_sz:4; |
| 145 | u32 icverr:1; |
| 146 | u32 crc32:1; |
| 147 | u32 pktlen:14; |
| 148 | |
| 149 | u32 bc:1; |
| 150 | u32 mc:1; |
| 151 | u32 type:2; |
| 152 | u32 mf:1; |
| 153 | u32 md:1; |
| 154 | u32 pwr:1; |
| 155 | u32 pam:1; |
| 156 | u32 a2fit:4; |
| 157 | u32 a1fit:4; |
| 158 | u32 faggr:1; |
| 159 | u32 paggr:1; |
| 160 | u32 amsdu:1; |
| 161 | u32 hwrsvd:4; |
| 162 | u32 tid:4; |
| 163 | u32 macid:5; |
| 164 | |
| 165 | u32 reserved0:1; |
| 166 | u32 nextind:1; |
| 167 | u32 nextpktlen:14; |
| 168 | u32 frag:4; |
| 169 | u32 seq:12; |
| 170 | |
| 171 | u32 magicwake:1; |
| 172 | u32 unicastwake:1; |
| 173 | u32 reserved1:16; |
| 174 | u32 bssidfit:2; |
| 175 | u32 eosp:1; |
| 176 | u32 htc:1; |
| 177 | u32 bw:1; |
| 178 | u32 splcp:1; |
| 179 | u32 gf:1; |
| 180 | u32 rxht:1; |
| 181 | u32 rxmcs:6; |
| 182 | |
| 183 | u32 reserved2:19; |
| 184 | u32 patterncmatch:1; |
| 185 | u32 patternbmatch:1; |
| 186 | u32 patternamatch:1; |
| 187 | u32 pattern9match:1; |
| 188 | u32 pattern8match:1; |
| 189 | u32 pattern7match:1; |
| 190 | u32 pattern6match:1; |
| 191 | u32 pattern5match:1; |
| 192 | u32 pattern4match:1; |
| 193 | u32 pattern3match:1; |
| 194 | u32 pattern2match:1; |
| 195 | u32 pattern1match:1; |
| 196 | u32 pattern0match:1; |
| 197 | #endif |
| 198 | __le32 tsfl; |
| 199 | #if 0 |
| 200 | u32 bassn:12; |
| 201 | u32 bavld:1; |
| 202 | u32 reserved3:19; |
| 203 | #endif |
| 204 | }; |
| 205 | |
Jes Sorensen | a6c80d2 | 2016-02-29 17:04:46 -0500 | [diff] [blame] | 206 | struct rtl8723bu_rx_desc { |
| 207 | #ifdef __LITTLE_ENDIAN |
| 208 | u32 pktlen:14; |
| 209 | u32 crc32:1; |
| 210 | u32 icverr:1; |
| 211 | u32 drvinfo_sz:4; |
| 212 | u32 security:3; |
| 213 | u32 qos:1; |
| 214 | u32 shift:2; |
| 215 | u32 phy_stats:1; |
| 216 | u32 swdec:1; |
| 217 | u32 ls:1; |
| 218 | u32 fs:1; |
| 219 | u32 eor:1; |
| 220 | u32 own:1; |
| 221 | |
| 222 | u32 macid:7; |
| 223 | u32 dummy1_0:1; |
| 224 | u32 tid:4; |
| 225 | u32 dummy1_1:1; |
| 226 | u32 amsdu:1; |
| 227 | u32 rxid_match:1; |
| 228 | u32 paggr:1; |
| 229 | u32 a1fit:4; /* 16 */ |
| 230 | u32 chkerr:1; |
| 231 | u32 ipver:1; |
| 232 | u32 tcpudp:1; |
| 233 | u32 chkvld:1; |
| 234 | u32 pam:1; |
| 235 | u32 pwr:1; |
| 236 | u32 more_data:1; |
| 237 | u32 more_frag:1; |
| 238 | u32 type:2; |
| 239 | u32 mc:1; |
| 240 | u32 bc:1; |
| 241 | |
| 242 | u32 seq:12; |
| 243 | u32 frag:4; |
| 244 | u32 rx_is_qos:1; /* 16 */ |
| 245 | u32 dummy2_0:1; |
| 246 | u32 wlanhd_iv_len:6; |
| 247 | u32 dummy2_1:4; |
| 248 | u32 rpt_sel:1; |
| 249 | u32 dummy2_2:3; |
| 250 | |
| 251 | u32 rxmcs:7; |
| 252 | u32 dummy3_0:3; |
| 253 | u32 htc:1; |
| 254 | u32 eosp:1; |
| 255 | u32 bssidfit:2; |
| 256 | u32 dummy3_1:2; |
| 257 | u32 usb_agg_pktnum:8; /* 16 */ |
| 258 | u32 dummy3_2:5; |
| 259 | u32 pattern_match:1; |
| 260 | u32 unicast_match:1; |
| 261 | u32 magic_match:1; |
| 262 | |
| 263 | u32 splcp:1; |
| 264 | u32 ldcp:1; |
| 265 | u32 stbc:1; |
| 266 | u32 dummy4_0:1; |
| 267 | u32 bw:2; |
| 268 | u32 dummy4_1:26; |
| 269 | #else |
| 270 | u32 own:1; |
| 271 | u32 eor:1; |
| 272 | u32 fs:1; |
| 273 | u32 ls:1; |
| 274 | u32 swdec:1; |
| 275 | u32 phy_stats:1; |
| 276 | u32 shift:2; |
| 277 | u32 qos:1; |
| 278 | u32 security:3; |
| 279 | u32 drvinfo_sz:4; |
| 280 | u32 icverr:1; |
| 281 | u32 crc32:1; |
| 282 | u32 pktlen:14; |
| 283 | |
| 284 | u32 bc:1; |
| 285 | u32 mc:1; |
| 286 | u32 type:2; |
| 287 | u32 mf:1; |
| 288 | u32 md:1; |
| 289 | u32 pwr:1; |
| 290 | u32 pam:1; |
| 291 | u32 a2fit:4; |
| 292 | u32 a1fit:4; |
| 293 | u32 faggr:1; |
| 294 | u32 paggr:1; |
| 295 | u32 amsdu:1; |
| 296 | u32 hwrsvd:4; |
| 297 | u32 tid:4; |
| 298 | u32 macid:5; |
| 299 | |
| 300 | u32 dummy2_2:3; |
| 301 | u32 rpt_sel:1; |
| 302 | u32 dummy2_1:4; |
| 303 | u32 wlanhd_iv_len:6; |
| 304 | u32 dummy2_0:1; |
| 305 | u32 rx_is_qos:1; |
| 306 | u32 frag:4; /* 16 */ |
| 307 | u32 seq:12; |
| 308 | |
| 309 | u32 magic_match:1; |
| 310 | u32 unicast_match:1; |
| 311 | u32 pattern_match:1; |
| 312 | u32 dummy3_2:5; |
| 313 | u32 usb_agg_pktnum:8; |
| 314 | u32 dummy3_1:2; /* 16 */ |
| 315 | u32 bssidfit:2; |
| 316 | u32 eosp:1; |
| 317 | u32 htc:1; |
| 318 | u32 dummy3_0:3; |
| 319 | u32 rxmcs:7; |
| 320 | |
| 321 | u32 dumm4_1:26; |
| 322 | u32 bw:2; |
| 323 | u32 dummy4_0:1; |
| 324 | u32 stbc:1; |
| 325 | u32 ldcp:1; |
| 326 | u32 splcp:1; |
| 327 | #endif |
| 328 | __le32 tsfl; |
| 329 | }; |
| 330 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 331 | struct rtl8xxxu_tx_desc { |
| 332 | __le16 pkt_size; |
| 333 | u8 pkt_offset; |
| 334 | u8 txdw0; |
| 335 | __le32 txdw1; |
| 336 | __le32 txdw2; |
| 337 | __le32 txdw3; |
| 338 | __le32 txdw4; |
| 339 | __le32 txdw5; |
| 340 | __le32 txdw6; |
| 341 | __le16 csum; |
| 342 | __le16 txdw7; |
| 343 | }; |
| 344 | |
| 345 | /* CCK Rates, TxHT = 0 */ |
| 346 | #define DESC_RATE_1M 0x00 |
| 347 | #define DESC_RATE_2M 0x01 |
| 348 | #define DESC_RATE_5_5M 0x02 |
| 349 | #define DESC_RATE_11M 0x03 |
| 350 | |
| 351 | /* OFDM Rates, TxHT = 0 */ |
| 352 | #define DESC_RATE_6M 0x04 |
| 353 | #define DESC_RATE_9M 0x05 |
| 354 | #define DESC_RATE_12M 0x06 |
| 355 | #define DESC_RATE_18M 0x07 |
| 356 | #define DESC_RATE_24M 0x08 |
| 357 | #define DESC_RATE_36M 0x09 |
| 358 | #define DESC_RATE_48M 0x0a |
| 359 | #define DESC_RATE_54M 0x0b |
| 360 | |
| 361 | /* MCS Rates, TxHT = 1 */ |
| 362 | #define DESC_RATE_MCS0 0x0c |
| 363 | #define DESC_RATE_MCS1 0x0d |
| 364 | #define DESC_RATE_MCS2 0x0e |
| 365 | #define DESC_RATE_MCS3 0x0f |
| 366 | #define DESC_RATE_MCS4 0x10 |
| 367 | #define DESC_RATE_MCS5 0x11 |
| 368 | #define DESC_RATE_MCS6 0x12 |
| 369 | #define DESC_RATE_MCS7 0x13 |
| 370 | #define DESC_RATE_MCS8 0x14 |
| 371 | #define DESC_RATE_MCS9 0x15 |
| 372 | #define DESC_RATE_MCS10 0x16 |
| 373 | #define DESC_RATE_MCS11 0x17 |
| 374 | #define DESC_RATE_MCS12 0x18 |
| 375 | #define DESC_RATE_MCS13 0x19 |
| 376 | #define DESC_RATE_MCS14 0x1a |
| 377 | #define DESC_RATE_MCS15 0x1b |
| 378 | #define DESC_RATE_MCS15_SG 0x1c |
| 379 | #define DESC_RATE_MCS32 0x20 |
| 380 | |
| 381 | #define TXDESC_OFFSET_SZ 0 |
| 382 | #define TXDESC_OFFSET_SHT 16 |
| 383 | #if 0 |
| 384 | #define TXDESC_BMC BIT(24) |
| 385 | #define TXDESC_LSG BIT(26) |
| 386 | #define TXDESC_FSG BIT(27) |
| 387 | #define TXDESC_OWN BIT(31) |
| 388 | #else |
| 389 | #define TXDESC_BROADMULTICAST BIT(0) |
| 390 | #define TXDESC_LAST_SEGMENT BIT(2) |
| 391 | #define TXDESC_FIRST_SEGMENT BIT(3) |
| 392 | #define TXDESC_OWN BIT(7) |
| 393 | #endif |
| 394 | |
| 395 | /* Word 1 */ |
| 396 | #define TXDESC_PKT_OFFSET_SZ 0 |
| 397 | #define TXDESC_AGG_ENABLE BIT(5) |
| 398 | #define TXDESC_BK BIT(6) |
| 399 | #define TXDESC_QUEUE_SHIFT 8 |
| 400 | #define TXDESC_QUEUE_MASK 0x1f00 |
| 401 | #define TXDESC_QUEUE_BK 0x2 |
| 402 | #define TXDESC_QUEUE_BE 0x0 |
| 403 | #define TXDESC_QUEUE_VI 0x5 |
| 404 | #define TXDESC_QUEUE_VO 0x7 |
| 405 | #define TXDESC_QUEUE_BEACON 0x10 |
| 406 | #define TXDESC_QUEUE_HIGH 0x11 |
| 407 | #define TXDESC_QUEUE_MGNT 0x12 |
| 408 | #define TXDESC_QUEUE_CMD 0x13 |
| 409 | #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) |
| 410 | |
| 411 | #define DESC_RATE_ID_SHIFT 16 |
| 412 | #define DESC_RATE_ID_MASK 0xf |
| 413 | #define TXDESC_NAVUSEHDR BIT(20) |
| 414 | #define TXDESC_SEC_RC4 0x00400000 |
| 415 | #define TXDESC_SEC_AES 0x00c00000 |
| 416 | #define TXDESC_PKT_OFFSET_SHIFT 26 |
| 417 | #define TXDESC_AGG_EN BIT(29) |
| 418 | #define TXDESC_HWPC BIT(31) |
| 419 | |
| 420 | /* Word 2 */ |
| 421 | #define TXDESC_ACK_REPORT BIT(19) |
| 422 | #define TXDESC_AMPDU_DENSITY_SHIFT 20 |
| 423 | |
| 424 | /* Word 3 */ |
| 425 | #define TXDESC_SEQ_SHIFT 16 |
| 426 | #define TXDESC_SEQ_MASK 0x0fff0000 |
| 427 | |
| 428 | /* Word 4 */ |
| 429 | #define TXDESC_QOS BIT(6) |
| 430 | #define TXDESC_HW_SEQ_ENABLE BIT(7) |
| 431 | #define TXDESC_USE_DRIVER_RATE BIT(8) |
| 432 | #define TXDESC_DISABLE_DATA_FB BIT(10) |
| 433 | #define TXDESC_CTS_SELF_ENABLE BIT(11) |
| 434 | #define TXDESC_RTS_CTS_ENABLE BIT(12) |
| 435 | #define TXDESC_HW_RTS_ENABLE BIT(13) |
| 436 | #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) |
| 437 | #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) |
| 438 | #define TXDESC_SHORT_PREAMBLE BIT(24) |
| 439 | #define TXDESC_DATA_BW BIT(25) |
| 440 | #define TXDESC_RTS_DATA_BW BIT(27) |
| 441 | #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) |
| 442 | #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) |
| 443 | |
| 444 | /* Word 5 */ |
| 445 | #define TXDESC_RTS_RATE_SHIFT 0 |
| 446 | #define TXDESC_RTS_RATE_MASK 0x3f |
| 447 | #define TXDESC_SHORT_GI BIT(6) |
| 448 | #define TXDESC_CCX_TAG BIT(7) |
| 449 | #define TXDESC_RETRY_LIMIT_ENABLE BIT(17) |
| 450 | #define TXDESC_RETRY_LIMIT_SHIFT 18 |
| 451 | #define TXDESC_RETRY_LIMIT_MASK 0x00fc0000 |
| 452 | |
| 453 | /* Word 6 */ |
| 454 | #define TXDESC_MAX_AGG_SHIFT 11 |
| 455 | |
| 456 | struct phy_rx_agc_info { |
| 457 | #ifdef __LITTLE_ENDIAN |
| 458 | u8 gain:7, trsw:1; |
| 459 | #else |
| 460 | u8 trsw:1, gain:7; |
| 461 | #endif |
| 462 | }; |
| 463 | |
| 464 | struct rtl8723au_phy_stats { |
| 465 | struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; |
| 466 | u8 ch_corr[RTL8723A_MAX_RF_PATHS]; |
| 467 | u8 cck_sig_qual_ofdm_pwdb_all; |
| 468 | u8 cck_agc_rpt_ofdm_cfosho_a; |
| 469 | u8 cck_rpt_b_ofdm_cfosho_b; |
| 470 | u8 reserved_1; |
| 471 | u8 noise_power_db_msb; |
| 472 | u8 path_cfotail[RTL8723A_MAX_RF_PATHS]; |
| 473 | u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; |
| 474 | s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; |
| 475 | u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; |
| 476 | u8 noise_power_db_lsb; |
| 477 | u8 reserved_2[3]; |
| 478 | u8 stream_csi[RTL8723A_MAX_RF_PATHS]; |
| 479 | u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; |
| 480 | s8 sig_evm; |
| 481 | u8 reserved_3; |
| 482 | |
| 483 | #ifdef __LITTLE_ENDIAN |
| 484 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ |
| 485 | u8 sgi_en:1; |
| 486 | u8 rxsc:2; |
| 487 | u8 idle_long:1; |
| 488 | u8 r_ant_train_en:1; |
| 489 | u8 antenna_select_b:1; |
| 490 | u8 antenna_select:1; |
| 491 | #else /* _BIG_ENDIAN_ */ |
| 492 | u8 antenna_select:1; |
| 493 | u8 antenna_select_b:1; |
| 494 | u8 r_ant_train_en:1; |
| 495 | u8 idle_long:1; |
| 496 | u8 rxsc:2; |
| 497 | u8 sgi_en:1; |
| 498 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ |
| 499 | #endif |
| 500 | }; |
| 501 | |
| 502 | /* |
| 503 | * Regs to backup |
| 504 | */ |
| 505 | #define RTL8XXXU_ADDA_REGS 16 |
| 506 | #define RTL8XXXU_MAC_REGS 4 |
| 507 | #define RTL8XXXU_BB_REGS 9 |
| 508 | |
| 509 | struct rtl8xxxu_firmware_header { |
| 510 | __le16 signature; /* 92C0: test chip; 92C, |
| 511 | 88C0: test chip; |
| 512 | 88C1: MP A-cut; |
| 513 | 92C1: MP A-cut */ |
| 514 | u8 category; /* AP/NIC and USB/PCI */ |
| 515 | u8 function; |
| 516 | |
| 517 | __le16 major_version; /* FW Version */ |
| 518 | u8 minor_version; /* FW Subversion, default 0x00 */ |
| 519 | u8 reserved1; |
| 520 | |
| 521 | u8 month; /* Release time Month field */ |
| 522 | u8 date; /* Release time Date field */ |
| 523 | u8 hour; /* Release time Hour field */ |
| 524 | u8 minute; /* Release time Minute field */ |
| 525 | |
| 526 | __le16 ramcodesize; /* Size of RAM code */ |
| 527 | u16 reserved2; |
| 528 | |
| 529 | __le32 svn_idx; /* SVN entry index */ |
| 530 | u32 reserved3; |
| 531 | |
| 532 | u32 reserved4; |
| 533 | u32 reserved5; |
| 534 | |
| 535 | u8 data[0]; |
| 536 | }; |
| 537 | |
| 538 | /* |
| 539 | * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 |
| 540 | */ |
| 541 | struct rtl8723au_idx { |
| 542 | #ifdef __LITTLE_ENDIAN |
| 543 | int a:4; |
| 544 | int b:4; |
| 545 | #else |
| 546 | int b:4; |
| 547 | int a:4; |
| 548 | #endif |
| 549 | } __attribute__((packed)); |
| 550 | |
| 551 | struct rtl8723au_efuse { |
| 552 | __le16 rtl_id; |
| 553 | u8 res0[0xe]; |
| 554 | u8 cck_tx_power_index_A[3]; /* 0x10 */ |
| 555 | u8 cck_tx_power_index_B[3]; |
| 556 | u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ |
| 557 | u8 ht40_1s_tx_power_index_B[3]; |
| 558 | /* |
| 559 | * The following entries are half-bytes split as: |
| 560 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed |
| 561 | */ |
| 562 | struct rtl8723au_idx ht20_tx_power_index_diff[3]; |
| 563 | struct rtl8723au_idx ofdm_tx_power_index_diff[3]; |
| 564 | struct rtl8723au_idx ht40_max_power_offset[3]; |
| 565 | struct rtl8723au_idx ht20_max_power_offset[3]; |
| 566 | u8 channel_plan; /* 0x28 */ |
| 567 | u8 tssi_a; |
| 568 | u8 thermal_meter; |
| 569 | u8 rf_regulatory; |
| 570 | u8 rf_option_2; |
| 571 | u8 rf_option_3; |
| 572 | u8 rf_option_4; |
| 573 | u8 res7; |
| 574 | u8 version /* 0x30 */; |
| 575 | u8 customer_id_major; |
| 576 | u8 customer_id_minor; |
| 577 | u8 xtal_k; |
| 578 | u8 chipset; /* 0x34 */ |
| 579 | u8 res8[0x82]; |
| 580 | u8 vid; /* 0xb7 */ |
| 581 | u8 res9; |
| 582 | u8 pid; /* 0xb9 */ |
| 583 | u8 res10[0x0c]; |
| 584 | u8 mac_addr[ETH_ALEN]; /* 0xc6 */ |
| 585 | u8 res11[2]; |
| 586 | u8 vendor_name[7]; |
| 587 | u8 res12[2]; |
| 588 | u8 device_name[0x29]; /* 0xd7 */ |
| 589 | }; |
| 590 | |
| 591 | struct rtl8192cu_efuse { |
| 592 | __le16 rtl_id; |
| 593 | __le16 hpon; |
| 594 | u8 res0[2]; |
| 595 | __le16 clk; |
| 596 | __le16 testr; |
| 597 | __le16 vid; |
| 598 | __le16 did; |
| 599 | __le16 svid; |
| 600 | __le16 smid; /* 0x10 */ |
| 601 | u8 res1[4]; |
| 602 | u8 mac_addr[ETH_ALEN]; /* 0x16 */ |
| 603 | u8 res2[2]; |
| 604 | u8 vendor_name[7]; |
| 605 | u8 res3[3]; |
| 606 | u8 device_name[0x14]; /* 0x28 */ |
| 607 | u8 res4[0x1e]; /* 0x3c */ |
| 608 | u8 cck_tx_power_index_A[3]; /* 0x5a */ |
| 609 | u8 cck_tx_power_index_B[3]; |
| 610 | u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ |
| 611 | u8 ht40_1s_tx_power_index_B[3]; |
| 612 | /* |
| 613 | * The following entries are half-bytes split as: |
| 614 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed |
| 615 | */ |
| 616 | struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; |
| 617 | struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ |
| 618 | struct rtl8723au_idx ofdm_tx_power_index_diff[3]; |
| 619 | struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ |
| 620 | struct rtl8723au_idx ht20_max_power_offset[3]; |
| 621 | u8 channel_plan; /* 0x75 */ |
| 622 | u8 tssi_a; |
| 623 | u8 tssi_b; |
| 624 | u8 thermal_meter; /* xtal_k */ /* 0x78 */ |
| 625 | u8 rf_regulatory; |
| 626 | u8 rf_option_2; |
| 627 | u8 rf_option_3; |
| 628 | u8 rf_option_4; |
| 629 | u8 res5[1]; /* 0x7d */ |
| 630 | u8 version; |
| 631 | u8 customer_id; |
| 632 | }; |
| 633 | |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 634 | struct rtl8723bu_efuse { |
| 635 | __le16 rtl_id; |
| 636 | u8 res0[0x0e]; |
| 637 | u8 cck_tx_power_index_A[3]; /* 0x10 */ |
| 638 | u8 cck_tx_power_index_B[3]; |
| 639 | u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ |
| 640 | u8 ht40_1s_tx_power_index_B[3]; |
| 641 | u8 res1[0x9c]; |
| 642 | u8 channel_plan; /* 0xb8 */ |
| 643 | u8 xtal_k; |
| 644 | u8 thermal_meter; |
| 645 | u8 iqk_lck; |
| 646 | u8 pa_type; /* 0xbc */ |
| 647 | u8 lna_type_2g; /* 0xbd */ |
| 648 | u8 res2[3]; |
| 649 | u8 rf_board_option; |
| 650 | u8 rf_feature_option; |
| 651 | u8 rf_bt_setting; |
| 652 | u8 eeprom_version; |
| 653 | u8 eeprom_customer_id; |
| 654 | u8 res3[2]; |
| 655 | u8 tx_pwr_calibrate_rate; |
| 656 | u8 rf_antenna_option; /* 0xc9 */ |
| 657 | u8 rfe_option; |
| 658 | u8 res4[9]; |
| 659 | u8 usb_optional_function; |
| 660 | u8 res5[0x1e]; |
| 661 | u8 res6[2]; |
| 662 | u8 serial[0x0b]; /* 0xf5 */ |
| 663 | u8 vid; /* 0x100 */ |
| 664 | u8 res7; |
| 665 | u8 pid; |
| 666 | u8 res8[4]; |
| 667 | u8 mac_addr[ETH_ALEN]; /* 0x107 */ |
| 668 | u8 res9[2]; |
| 669 | u8 vendor_name[0x07]; |
| 670 | u8 res10[2]; |
Jes Sorensen | 22a31d4 | 2016-02-29 17:04:15 -0500 | [diff] [blame] | 671 | u8 device_name[0x14]; |
| 672 | u8 res11[0xcf]; |
| 673 | u8 package_type; /* 0x1fb */ |
| 674 | u8 res12[0x4]; |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 675 | }; |
| 676 | |
Jakub Sitnicki | e6f9a9c | 2016-02-29 17:04:39 -0500 | [diff] [blame] | 677 | struct rtl8192eu_efuse_tx_power { |
| 678 | u8 cck_base[6]; |
| 679 | u8 ht40_base[5]; |
| 680 | struct rtl8723au_idx ht20_ofdm_1s_diff; |
| 681 | struct rtl8723au_idx ht40_ht20_2s_diff; |
| 682 | struct rtl8723au_idx ofdm_cck_2s_diff; /* not used */ |
| 683 | struct rtl8723au_idx ht40_ht20_3s_diff; |
| 684 | struct rtl8723au_idx ofdm_cck_3s_diff; /* not used */ |
| 685 | struct rtl8723au_idx ht40_ht20_4s_diff; |
| 686 | struct rtl8723au_idx ofdm_cck_4s_diff; /* not used */ |
| 687 | }; |
| 688 | |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 689 | struct rtl8192eu_efuse { |
| 690 | __le16 rtl_id; |
| 691 | u8 res0[0x0e]; |
Jakub Sitnicki | e6f9a9c | 2016-02-29 17:04:39 -0500 | [diff] [blame] | 692 | struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ |
| 693 | struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x22 */ |
| 694 | struct rtl8192eu_efuse_tx_power tx_power_index_C; /* 0x34 */ |
| 695 | struct rtl8192eu_efuse_tx_power tx_power_index_D; /* 0x46 */ |
| 696 | u8 res1[0x60]; |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 697 | u8 channel_plan; /* 0xb8 */ |
| 698 | u8 xtal_k; |
| 699 | u8 thermal_meter; |
| 700 | u8 iqk_lck; |
| 701 | u8 pa_type; /* 0xbc */ |
| 702 | u8 lna_type_2g; /* 0xbd */ |
| 703 | u8 res2[1]; |
| 704 | u8 lna_type_5g; /* 0xbf */ |
| 705 | u8 res13[1]; |
| 706 | u8 rf_board_option; |
| 707 | u8 rf_feature_option; |
| 708 | u8 rf_bt_setting; |
| 709 | u8 eeprom_version; |
| 710 | u8 eeprom_customer_id; |
| 711 | u8 res3[3]; |
| 712 | u8 rf_antenna_option; /* 0xc9 */ |
| 713 | u8 res4[6]; |
| 714 | u8 vid; /* 0xd0 */ |
| 715 | u8 res5[1]; |
| 716 | u8 pid; /* 0xd2 */ |
| 717 | u8 res6[1]; |
| 718 | u8 usb_optional_function; |
| 719 | u8 res7[2]; |
| 720 | u8 mac_addr[ETH_ALEN]; /* 0xd7 */ |
| 721 | u8 res8[2]; |
| 722 | u8 vendor_name[7]; |
| 723 | u8 res9[2]; |
| 724 | u8 device_name[0x0b]; /* 0xe8 */ |
| 725 | u8 res10[2]; |
| 726 | u8 serial[0x0b]; /* 0xf5 */ |
| 727 | u8 res11[0x30]; |
| 728 | u8 unknown[0x0d]; /* 0x130 */ |
| 729 | u8 res12[0xc3]; |
| 730 | }; |
| 731 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 732 | struct rtl8xxxu_reg8val { |
| 733 | u16 reg; |
| 734 | u8 val; |
| 735 | }; |
| 736 | |
| 737 | struct rtl8xxxu_reg32val { |
| 738 | u16 reg; |
| 739 | u32 val; |
| 740 | }; |
| 741 | |
| 742 | struct rtl8xxxu_rfregval { |
| 743 | u8 reg; |
| 744 | u32 val; |
| 745 | }; |
| 746 | |
| 747 | enum rtl8xxxu_rfpath { |
| 748 | RF_A = 0, |
| 749 | RF_B = 1, |
| 750 | }; |
| 751 | |
| 752 | struct rtl8xxxu_rfregs { |
| 753 | u16 hssiparm1; |
| 754 | u16 hssiparm2; |
| 755 | u16 lssiparm; |
| 756 | u16 hspiread; |
| 757 | u16 lssiread; |
| 758 | u16 rf_sw_ctrl; |
| 759 | }; |
| 760 | |
| 761 | #define H2C_MAX_MBOX 4 |
| 762 | #define H2C_EXT BIT(7) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 763 | #define H2C_JOIN_BSS_DISCONNECT 0 |
| 764 | #define H2C_JOIN_BSS_CONNECT 1 |
Jes Sorensen | d940c24 | 2016-02-29 17:04:22 -0500 | [diff] [blame] | 765 | |
| 766 | /* |
| 767 | * H2C (firmware) commands differ between the older generation chips |
| 768 | * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, |
| 769 | * 8192[de]u, 8192eu, and 8812. |
| 770 | */ |
| 771 | enum h2c_cmd_8723a { |
| 772 | H2C_SET_POWER_MODE = 1, |
| 773 | H2C_JOIN_BSS_REPORT = 2, |
| 774 | H2C_SET_RSSI = 5, |
| 775 | H2C_SET_RATE_MASK = (6 | H2C_EXT), |
| 776 | }; |
| 777 | |
| 778 | enum h2c_cmd_8723b { |
| 779 | /* |
| 780 | * Common Class: 000 |
| 781 | */ |
| 782 | H2C_8723B_RSVD_PAGE = 0x00, |
| 783 | H2C_8723B_MEDIA_STATUS_RPT = 0x01, |
| 784 | H2C_8723B_SCAN_ENABLE = 0x02, |
| 785 | H2C_8723B_KEEP_ALIVE = 0x03, |
| 786 | H2C_8723B_DISCON_DECISION = 0x04, |
| 787 | H2C_8723B_PSD_OFFLOAD = 0x05, |
| 788 | H2C_8723B_AP_OFFLOAD = 0x08, |
| 789 | H2C_8723B_BCN_RSVDPAGE = 0x09, |
| 790 | H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, |
| 791 | H2C_8723B_FCS_RSVDPAGE = 0x10, |
| 792 | H2C_8723B_FCS_INFO = 0x11, |
| 793 | H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, |
| 794 | |
| 795 | /* |
| 796 | * PoweSave Class: 001 |
| 797 | */ |
| 798 | H2C_8723B_SET_PWR_MODE = 0x20, |
| 799 | H2C_8723B_PS_TUNING_PARA = 0x21, |
| 800 | H2C_8723B_PS_TUNING_PARA2 = 0x22, |
| 801 | H2C_8723B_P2P_LPS_PARAM = 0x23, |
| 802 | H2C_8723B_P2P_PS_OFFLOAD = 0x24, |
| 803 | H2C_8723B_PS_SCAN_ENABLE = 0x25, |
| 804 | H2C_8723B_SAP_PS_ = 0x26, |
| 805 | H2C_8723B_INACTIVE_PS_ = 0x27, |
| 806 | H2C_8723B_FWLPS_IN_IPS_ = 0x28, |
| 807 | |
| 808 | /* |
| 809 | * Dynamic Mechanism Class: 010 |
| 810 | */ |
| 811 | H2C_8723B_MACID_CFG = 0x40, |
| 812 | H2C_8723B_TXBF = 0x41, |
| 813 | H2C_8723B_RSSI_SETTING = 0x42, |
| 814 | H2C_8723B_AP_REQ_TXRPT = 0x43, |
| 815 | H2C_8723B_INIT_RATE_COLLECT = 0x44, |
| 816 | |
| 817 | /* |
| 818 | * BT Class: 011 |
| 819 | */ |
| 820 | H2C_8723B_B_TYPE_TDMA = 0x60, |
| 821 | H2C_8723B_BT_INFO = 0x61, |
| 822 | H2C_8723B_FORCE_BT_TXPWR = 0x62, |
| 823 | H2C_8723B_BT_IGNORE_WLANACT = 0x63, |
| 824 | H2C_8723B_DAC_SWING_VALUE = 0x64, |
| 825 | H2C_8723B_ANT_SEL_RSV = 0x65, |
| 826 | H2C_8723B_WL_OPMODE = 0x66, |
| 827 | H2C_8723B_BT_MP_OPER = 0x67, |
| 828 | H2C_8723B_BT_CONTROL = 0x68, |
| 829 | H2C_8723B_BT_WIFI_CTRL = 0x69, |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 830 | H2C_8723B_BT_FW_PATCH = 0x6a, |
| 831 | H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, |
| 832 | H2C_8723B_BT_GRANT = 0x6e, |
Jes Sorensen | d940c24 | 2016-02-29 17:04:22 -0500 | [diff] [blame] | 833 | |
| 834 | /* |
| 835 | * WOWLAN Class: 100 |
| 836 | */ |
| 837 | H2C_8723B_WOWLAN = 0x80, |
| 838 | H2C_8723B_REMOTE_WAKE_CTRL = 0x81, |
| 839 | H2C_8723B_AOAC_GLOBAL_INFO = 0x82, |
| 840 | H2C_8723B_AOAC_RSVD_PAGE = 0x83, |
| 841 | H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, |
| 842 | H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, |
| 843 | H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, |
| 844 | H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, |
| 845 | |
| 846 | H2C_8723B_RESET_TSF = 0xC0, |
| 847 | }; |
| 848 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 849 | |
| 850 | struct h2c_cmd { |
| 851 | union { |
| 852 | struct { |
| 853 | u8 cmd; |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 854 | u8 data[7]; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 855 | } __packed cmd; |
| 856 | struct { |
| 857 | __le32 data; |
| 858 | __le16 ext; |
| 859 | } __packed raw; |
| 860 | struct { |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 861 | __le32 data; |
| 862 | __le32 ext; |
| 863 | } __packed raw_wide; |
| 864 | struct { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 865 | u8 cmd; |
| 866 | u8 data; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 867 | } __packed joinbss; |
| 868 | struct { |
| 869 | u8 cmd; |
| 870 | __le16 mask_hi; |
| 871 | u8 arg; |
| 872 | __le16 mask_lo; |
| 873 | } __packed ramask; |
Jes Sorensen | c7a5a19 | 2016-02-29 17:04:30 -0500 | [diff] [blame] | 874 | struct { |
| 875 | u8 cmd; |
Jes Sorensen | 3ca7b32 | 2016-02-29 17:04:43 -0500 | [diff] [blame] | 876 | u8 data1; |
| 877 | u8 data2; |
| 878 | u8 data3; |
| 879 | u8 data4; |
| 880 | u8 data5; |
| 881 | } __packed b_type_dma; |
| 882 | struct { |
| 883 | u8 cmd; |
Jes Sorensen | 6b9eae0 | 2016-02-29 17:04:50 -0500 | [diff] [blame] | 884 | u8 data; |
| 885 | } __packed bt_info; |
| 886 | struct { |
| 887 | u8 cmd; |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 888 | u8 operreq; |
| 889 | u8 opcode; |
| 890 | u8 data; |
| 891 | u8 addr; |
| 892 | } __packed bt_mp_oper; |
| 893 | struct { |
| 894 | u8 cmd; |
Jes Sorensen | c7a5a19 | 2016-02-29 17:04:30 -0500 | [diff] [blame] | 895 | u8 data; |
| 896 | } __packed bt_wlan_calibration; |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 897 | struct { |
| 898 | u8 cmd; |
Jes Sorensen | 7297f49 | 2016-02-29 17:04:44 -0500 | [diff] [blame] | 899 | u8 data; |
| 900 | } __packed ignore_wlan; |
| 901 | struct { |
| 902 | u8 cmd; |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 903 | u8 ant_inverse; |
| 904 | u8 int_switch_type; |
| 905 | } __packed ant_sel_rsv; |
| 906 | struct { |
| 907 | u8 cmd; |
| 908 | u8 data; |
| 909 | } __packed bt_grant; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 910 | }; |
| 911 | }; |
| 912 | |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 913 | enum c2h_evt_8723b { |
| 914 | C2H_8723B_DEBUG = 0, |
| 915 | C2H_8723B_TSF = 1, |
| 916 | C2H_8723B_AP_RPT_RSP = 2, |
| 917 | C2H_8723B_CCX_TX_RPT = 3, |
| 918 | C2H_8723B_BT_RSSI = 4, |
| 919 | C2H_8723B_BT_OP_MODE = 5, |
| 920 | C2H_8723B_EXT_RA_RPT = 6, |
| 921 | C2H_8723B_BT_INFO = 9, |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 922 | C2H_8723B_HW_INFO_EXCH = 0x0a, |
| 923 | C2H_8723B_BT_MP_INFO = 0x0b, |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 924 | C2H_8723B_FW_DEBUG = 0xff, |
| 925 | }; |
| 926 | |
| 927 | enum bt_info_src_8723b { |
| 928 | BT_INFO_SRC_8723B_WIFI_FW = 0x0, |
| 929 | BT_INFO_SRC_8723B_BT_RSP = 0x1, |
| 930 | BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, |
| 931 | }; |
| 932 | |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 933 | enum bt_mp_oper_opcode_8723b { |
| 934 | BT_MP_OP_GET_BT_VERSION = 0x00, |
| 935 | BT_MP_OP_RESET = 0x01, |
| 936 | BT_MP_OP_TEST_CTRL = 0x02, |
| 937 | BT_MP_OP_SET_BT_MODE = 0x03, |
| 938 | BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, |
| 939 | BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, |
| 940 | BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, |
| 941 | BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, |
| 942 | BT_MP_OP_SET_PKT_HEADER = 0x08, |
| 943 | BT_MP_OP_SET_WHITENCOEFF = 0x09, |
| 944 | BT_MP_OP_SET_BD_ADDR_L = 0x0a, |
| 945 | BT_MP_OP_SET_BD_ADDR_H = 0x0b, |
| 946 | BT_MP_OP_WRITE_REG_ADDR = 0x0c, |
| 947 | BT_MP_OP_WRITE_REG_VALUE = 0x0d, |
| 948 | BT_MP_OP_GET_BT_STATUS = 0x0e, |
| 949 | BT_MP_OP_GET_BD_ADDR_L = 0x0f, |
| 950 | BT_MP_OP_GET_BD_ADDR_H = 0x10, |
| 951 | BT_MP_OP_READ_REG = 0x11, |
| 952 | BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, |
| 953 | BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, |
| 954 | BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, |
| 955 | BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, |
| 956 | BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, |
| 957 | BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, |
| 958 | BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, |
| 959 | BT_MP_OP_GET_RSSI = 0x19, |
| 960 | BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, |
| 961 | BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, |
| 962 | BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, |
| 963 | BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, |
| 964 | BT_MP_OP_GET_AFH_MAP_L = 0x1e, |
| 965 | BT_MP_OP_GET_AFH_MAP_M = 0x1f, |
| 966 | BT_MP_OP_GET_AFH_MAP_H = 0x20, |
| 967 | BT_MP_OP_GET_AFH_STATUS = 0x21, |
| 968 | BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, |
| 969 | BT_MP_OP_SET_THERMAL_METER = 0x23, |
| 970 | BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, |
| 971 | }; |
| 972 | |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 973 | struct rtl8723bu_c2h { |
| 974 | u8 id; |
| 975 | u8 seq; |
| 976 | union { |
| 977 | struct { |
| 978 | u8 payload[0]; |
| 979 | } __packed raw; |
| 980 | struct { |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 981 | u8 ext_id; |
| 982 | u8 status:4; |
| 983 | u8 retlen:4; |
| 984 | u8 opcode_ver:4; |
| 985 | u8 req_num:4; |
| 986 | u8 payload[2]; |
| 987 | } __packed bt_mp_info; |
| 988 | struct { |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 989 | u8 response_source:4; |
| 990 | u8 dummy0_0:4; |
| 991 | |
| 992 | u8 bt_info; |
| 993 | |
| 994 | u8 retry_count:4; |
| 995 | u8 dummy2_0:1; |
| 996 | u8 bt_page:1; |
| 997 | u8 tx_rx_mask:1; |
| 998 | u8 dummy2_2:1; |
| 999 | |
| 1000 | u8 rssi; |
| 1001 | |
| 1002 | u8 basic_rate:1; |
| 1003 | u8 bt_has_reset:1; |
| 1004 | u8 dummy4_1:1;; |
| 1005 | u8 ignore_wlan:1; |
| 1006 | u8 auto_report:1; |
| 1007 | u8 dummy4_2:3; |
| 1008 | |
| 1009 | u8 a4; |
| 1010 | u8 a5; |
| 1011 | } __packed bt_info; |
| 1012 | }; |
| 1013 | }; |
| 1014 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1015 | struct rtl8xxxu_fileops; |
| 1016 | |
| 1017 | struct rtl8xxxu_priv { |
| 1018 | struct ieee80211_hw *hw; |
| 1019 | struct usb_device *udev; |
| 1020 | struct rtl8xxxu_fileops *fops; |
| 1021 | |
| 1022 | spinlock_t tx_urb_lock; |
| 1023 | struct list_head tx_urb_free_list; |
| 1024 | int tx_urb_free_count; |
| 1025 | bool tx_stopped; |
| 1026 | |
| 1027 | spinlock_t rx_urb_lock; |
| 1028 | struct list_head rx_urb_pending_list; |
| 1029 | int rx_urb_pending_count; |
| 1030 | bool shutdown; |
| 1031 | struct work_struct rx_urb_wq; |
| 1032 | |
| 1033 | u8 mac_addr[ETH_ALEN]; |
| 1034 | char chip_name[8]; |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 1035 | char chip_vendor[8]; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1036 | u8 cck_tx_power_index_A[3]; /* 0x10 */ |
| 1037 | u8 cck_tx_power_index_B[3]; |
| 1038 | u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ |
| 1039 | u8 ht40_1s_tx_power_index_B[3]; |
| 1040 | /* |
| 1041 | * The following entries are half-bytes split as: |
| 1042 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed |
| 1043 | */ |
| 1044 | struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; |
| 1045 | struct rtl8723au_idx ht20_tx_power_index_diff[3]; |
| 1046 | struct rtl8723au_idx ofdm_tx_power_index_diff[3]; |
| 1047 | struct rtl8723au_idx ht40_max_power_offset[3]; |
| 1048 | struct rtl8723au_idx ht20_max_power_offset[3]; |
| 1049 | u32 chip_cut:4; |
| 1050 | u32 rom_rev:4; |
Jakub Sitnicki | 3845199 | 2016-02-03 13:39:49 -0500 | [diff] [blame] | 1051 | u32 is_multi_func:1; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1052 | u32 has_wifi:1; |
| 1053 | u32 has_bluetooth:1; |
| 1054 | u32 enable_bluetooth:1; |
| 1055 | u32 has_gps:1; |
| 1056 | u32 hi_pa:1; |
| 1057 | u32 vendor_umc:1; |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 1058 | u32 vendor_smic:1; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1059 | u32 has_polarity_ctrl:1; |
| 1060 | u32 has_eeprom:1; |
| 1061 | u32 boot_eeprom:1; |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 1062 | u32 usb_interrupts:1; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1063 | u32 ep_tx_high_queue:1; |
| 1064 | u32 ep_tx_normal_queue:1; |
| 1065 | u32 ep_tx_low_queue:1; |
Jes Sorensen | 4ef22eb | 2016-02-29 17:04:55 -0500 | [diff] [blame] | 1066 | u32 has_xtalk:1; |
| 1067 | u8 xtalk; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1068 | unsigned int pipe_interrupt; |
| 1069 | unsigned int pipe_in; |
| 1070 | unsigned int pipe_out[TXDESC_QUEUE_MAX]; |
| 1071 | u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1072 | u8 ep_tx_count; |
| 1073 | u8 rf_paths; |
| 1074 | u8 rx_paths; |
| 1075 | u8 tx_paths; |
| 1076 | u32 rf_mode_ag[2]; |
| 1077 | u32 rege94; |
| 1078 | u32 rege9c; |
| 1079 | u32 regeb4; |
| 1080 | u32 regebc; |
| 1081 | int next_mbox; |
| 1082 | int nr_out_eps; |
| 1083 | |
| 1084 | struct mutex h2c_mutex; |
| 1085 | |
| 1086 | struct usb_anchor rx_anchor; |
| 1087 | struct usb_anchor tx_anchor; |
| 1088 | struct usb_anchor int_anchor; |
| 1089 | struct rtl8xxxu_firmware_header *fw_data; |
| 1090 | size_t fw_size; |
| 1091 | struct mutex usb_buf_mutex; |
| 1092 | union { |
| 1093 | __le32 val32; |
| 1094 | __le16 val16; |
| 1095 | u8 val8; |
| 1096 | } usb_buf; |
| 1097 | union { |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 1098 | u8 raw[EFUSE_MAP_LEN]; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1099 | struct rtl8723au_efuse efuse8723; |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 1100 | struct rtl8723bu_efuse efuse8723bu; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1101 | struct rtl8192cu_efuse efuse8192; |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 1102 | struct rtl8192eu_efuse efuse8192eu; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1103 | } efuse_wifi; |
| 1104 | u32 adda_backup[RTL8XXXU_ADDA_REGS]; |
| 1105 | u32 mac_backup[RTL8XXXU_MAC_REGS]; |
| 1106 | u32 bb_backup[RTL8XXXU_BB_REGS]; |
| 1107 | u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; |
| 1108 | u32 rtlchip; |
| 1109 | u8 pi_enabled:1; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1110 | u8 int_buf[USB_INTR_CONTENT_LENGTH]; |
| 1111 | }; |
| 1112 | |
| 1113 | struct rtl8xxxu_rx_urb { |
| 1114 | struct urb urb; |
| 1115 | struct ieee80211_hw *hw; |
| 1116 | struct list_head list; |
| 1117 | }; |
| 1118 | |
| 1119 | struct rtl8xxxu_tx_urb { |
| 1120 | struct urb urb; |
| 1121 | struct ieee80211_hw *hw; |
| 1122 | struct list_head list; |
| 1123 | }; |
| 1124 | |
| 1125 | struct rtl8xxxu_fileops { |
| 1126 | int (*parse_efuse) (struct rtl8xxxu_priv *priv); |
| 1127 | int (*load_firmware) (struct rtl8xxxu_priv *priv); |
| 1128 | int (*power_on) (struct rtl8xxxu_priv *priv); |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 1129 | int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 1130 | void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 1131 | void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); |
Jes Sorensen | c3f9506 | 2016-02-29 17:04:40 -0500 | [diff] [blame] | 1132 | void (*config_channel) (struct ieee80211_hw *hw); |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 1133 | void (*init_bt) (struct rtl8xxxu_priv *priv); |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 1134 | int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb, |
| 1135 | struct ieee80211_rx_status *rx_status); |
Jes Sorensen | 3e88ca4 | 2016-02-29 17:05:08 -0500 | [diff] [blame^] | 1136 | void (*init_aggregation) (struct rtl8xxxu_priv *priv); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1137 | int writeN_block_size; |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 1138 | u16 mbox_ext_reg; |
| 1139 | char mbox_ext_width; |
Jes Sorensen | 0d698de | 2016-02-29 17:04:36 -0500 | [diff] [blame] | 1140 | char has_s0s1; |
Jes Sorensen | 8634af5 | 2016-02-29 17:04:33 -0500 | [diff] [blame] | 1141 | u32 adda_1t_init; |
| 1142 | u32 adda_1t_path_on; |
| 1143 | u32 adda_2t_path_on_a; |
| 1144 | u32 adda_2t_path_on_b; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1145 | }; |