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Rajendra Nayak234f0c42009-12-08 18:24:52 -07001/*
2 * OMAP44xx Power Management register bits
3 *
Rajendra Nayak568997c2010-09-27 14:02:55 -06004 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
Rajendra Nayak234f0c42009-12-08 18:24:52 -07006 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
24
Rajendra Nayak234f0c42009-12-08 18:24:52 -070025
26/*
27 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
28 * PRM_LDO_SRAM_MPU_SETUP
29 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070030#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -060031#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070032
33/*
34 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
35 * PRM_LDO_SRAM_MPU_SETUP
36 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070037#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -060038#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070039
40/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070041#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31
Rajendra Nayak568997c2010-09-27 14:02:55 -060042#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070043
44/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070045#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31
Rajendra Nayak568997c2010-09-27 14:02:55 -060046#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070047
48/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070049#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -060050#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070051
52/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070053#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -060054#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070055
56/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070057#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -060058#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070059
60/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070061#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -060062#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070063
64/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070065#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -060066#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070067
68/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070069#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -060070#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070071
72/* Used by PM_ABE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070073#define OMAP4430_AESSMEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -060074#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070075
76/*
77 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
78 * PRM_LDO_SRAM_MPU_SETUP
79 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070080#define OMAP4430_AIPOFF_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -060081#define OMAP4430_AIPOFF_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070082
83/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070084#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -060085#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070086
87/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070088#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -060089#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -070090
91/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -070092#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -060093#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
94
95/* Used by PRM_VC_ERRST */
96#define OMAP4430_BYPS_RA_ERR_SHIFT 25
97#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25)
98
99/* Used by PRM_VC_ERRST */
100#define OMAP4430_BYPS_SA_ERR_SHIFT 24
101#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24)
102
103/* Used by PRM_VC_ERRST */
104#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26
105#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26)
106
107/* Used by PRM_RSTST */
108#define OMAP4430_C2C_RST_SHIFT 10
109#define OMAP4430_C2C_RST_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700110
111/* Used by PM_CAM_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700112#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600113#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700114
115/* Used by PM_CAM_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700116#define OMAP4430_CAM_MEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600117#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700118
119/* Used by PRM_CLKREQCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700120#define OMAP4430_CLKREQ_COND_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600121#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700122
123/* Used by PRM_VC_VAL_SMPS_RA_CMD */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700124#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600125#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700126
127/* Used by PRM_VC_VAL_SMPS_RA_CMD */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700128#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600129#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700130
131/* Used by PRM_VC_VAL_SMPS_RA_CMD */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700132#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600133#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700134
135/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700136#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600137#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700138
139/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700140#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600141#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700142
143/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700144#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17
Rajendra Nayak568997c2010-09-27 14:02:55 -0600145#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700146
147/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700148#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600149#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700150
151/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700152#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600153#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700154
155/* Used by PM_CORE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700156#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600157#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700158
159/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700160#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600161#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700162
163/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700164#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600165#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700166
167/* Used by PM_CORE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700168#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600169#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
170
171/* Used by REVISION_PRM */
172#define OMAP4430_CUSTOM_SHIFT 6
173#define OMAP4430_CUSTOM_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700174
175/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700176#define OMAP4430_DATA_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600177#define OMAP4430_DATA_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700178
179/* Used by PRM_DEVICE_OFF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700180#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600181#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700182
183/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700184#define OMAP4430_DFILTEREN_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600185#define OMAP4430_DFILTEREN_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700186
187/*
188 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
189 * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
190 */
Rajendra Nayak568997c2010-09-27 14:02:55 -0600191#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0
192#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0)
193
194/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
195#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4
196#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4)
197
198/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
199#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4
200#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4)
201
202/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
203#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0
204#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0)
205
206/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
207#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0
208#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0)
209
210/* Used by PRM_IRQENABLE_MPU */
211#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6
212#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6)
213
214/* Used by PRM_IRQSTATUS_MPU */
215#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6
216#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6)
217
218/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
219#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2
220#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2)
221
222/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
223#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2
224#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2)
225
226/* Used by PRM_IRQENABLE_MPU */
227#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1
228#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1)
229
230/* Used by PRM_IRQSTATUS_MPU */
231#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1
232#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1)
233
234/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
235#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3
236#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3)
237
238/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
239#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3
240#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3)
241
242/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
243#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
244#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7)
245
246/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
247#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7
248#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7)
249
250/* Used by PM_DSS_PWRSTCTRL */
251#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16
252#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16)
253
254/* Used by PM_DSS_PWRSTCTRL */
255#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8
256#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8)
257
258/* Used by PM_DSS_PWRSTST */
259#define OMAP4430_DSS_MEM_STATEST_SHIFT 4
260#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4)
261
262/* Used by PM_CORE_PWRSTCTRL */
263#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20
264#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20)
265
266/* Used by PM_CORE_PWRSTCTRL */
267#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10
268#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10)
269
270/* Used by PM_CORE_PWRSTST */
271#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8
272#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8)
273
274/* Used by PM_CORE_PWRSTCTRL */
275#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22
276#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22)
277
278/* Used by PM_CORE_PWRSTCTRL */
279#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11
280#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11)
281
282/* Used by PM_CORE_PWRSTST */
283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
285
286/* Used by RM_MPU_RSTST */
287#define OMAP4430_EMULATION_RST_SHIFT 0
288#define OMAP4430_EMULATION_RST_MASK (1 << 0)
289
290/* Used by RM_DUCATI_RSTST */
291#define OMAP4430_EMULATION_RST1ST_SHIFT 3
292#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3)
293
294/* Used by RM_DUCATI_RSTST */
295#define OMAP4430_EMULATION_RST2ST_SHIFT 4
296#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4)
297
298/* Used by RM_IVAHD_RSTST */
299#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3
300#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3)
301
302/* Used by RM_IVAHD_RSTST */
303#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4
304#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4)
305
306/* Used by PM_EMU_PWRSTCTRL */
307#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16
308#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16)
309
310/* Used by PM_EMU_PWRSTST */
311#define OMAP4430_EMU_BANK_STATEST_SHIFT 4
312#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700313
314/*
315 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
316 * PRM_LDO_SRAM_MPU_SETUP
317 */
Rajendra Nayak568997c2010-09-27 14:02:55 -0600318#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3
319#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700320
321/*
322 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
323 * PRM_LDO_SRAM_MPU_SETUP
324 */
Rajendra Nayak568997c2010-09-27 14:02:55 -0600325#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5
326#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700327
328/*
329 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
330 * PRM_LDO_SRAM_MPU_SETUP
331 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700332#define OMAP4430_ENFUNC4_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600333#define OMAP4430_ENFUNC4_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700334
335/*
336 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
337 * PRM_LDO_SRAM_MPU_SETUP
338 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700339#define OMAP4430_ENFUNC5_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -0600340#define OMAP4430_ENFUNC5_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700341
342/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700343#define OMAP4430_ERRORGAIN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600344#define OMAP4430_ERRORGAIN_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700345
346/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700347#define OMAP4430_ERROROFFSET_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600348#define OMAP4430_ERROROFFSET_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700349
350/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700351#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600352#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700353
354/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700355#define OMAP4430_FORCEUPDATE_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600356#define OMAP4430_FORCEUPDATE_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700357
358/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700359#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600360#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700361
362/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700363#define OMAP4430_FORCEWKUP_EN_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600364#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700365
366/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700367#define OMAP4430_FORCEWKUP_ST_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600368#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10)
369
370/* Used by REVISION_PRM */
371#define OMAP4430_FUNC_SHIFT 16
372#define OMAP4430_FUNC_MASK (0xfff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700373
374/* Used by PM_GFX_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700375#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600376#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700377
378/* Used by PM_GFX_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700379#define OMAP4430_GFX_MEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600380#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700381
382/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700383#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600384#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700385
386/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700387#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600388#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700389
390/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700391#define OMAP4430_GLOBAL_WUEN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600392#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700393
394/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700395#define OMAP4430_HSMCODE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600396#define OMAP4430_HSMCODE_MASK (0x7 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700397
398/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700399#define OMAP4430_HSMODEEN_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600400#define OMAP4430_HSMODEEN_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700401
402/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700403#define OMAP4430_HSSCLH_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600404#define OMAP4430_HSSCLH_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700405
406/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700407#define OMAP4430_HSSCLL_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600408#define OMAP4430_HSSCLL_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700409
410/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700411#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600412#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700413
414/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700415#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600416#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700417
418/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700419#define OMAP4430_HWA_MEM_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600420#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700421
422/* Used by RM_MPU_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700423#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600424#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700425
426/* Used by RM_DUCATI_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700427#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600428#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700429
430/* Used by RM_DUCATI_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700431#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600432#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700433
434/* Used by RM_IVAHD_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700435#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600436#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700437
438/* Used by RM_IVAHD_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700439#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600440#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700441
442/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700443#define OMAP4430_ICEPICK_RST_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600444#define OMAP4430_ICEPICK_RST_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700445
446/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700447#define OMAP4430_INITVDD_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600448#define OMAP4430_INITVDD_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700449
450/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700451#define OMAP4430_INITVOLTAGE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600452#define OMAP4430_INITVOLTAGE_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700453
454/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600455 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
456 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
457 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700458 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700459#define OMAP4430_INTRANSITION_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600460#define OMAP4430_INTRANSITION_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700461
462/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700463#define OMAP4430_IO_EN_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600464#define OMAP4430_IO_EN_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700465
466/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700467#define OMAP4430_IO_ON_STATUS_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -0600468#define OMAP4430_IO_ON_STATUS_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700469
470/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700471#define OMAP4430_IO_ST_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600472#define OMAP4430_IO_ST_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700473
474/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700475#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600476#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700477
478/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700479#define OMAP4430_ISOCLK_STATUS_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600480#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700481
482/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700483#define OMAP4430_ISOOVR_EXTEND_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600484#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700485
486/* Used by PRM_IO_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700487#define OMAP4430_ISO_2_ON_TIME_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600488#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700489
490/* Used by PM_L3INIT_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700491#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600492#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700493
494/* Used by PM_L3INIT_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700495#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600496#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700497
498/* Used by PM_L3INIT_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700499#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600500#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700501
502/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600503 * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
504 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
505 */
506#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24
507#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
508
509/*
510 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
511 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
512 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700513 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700514#define OMAP4430_LOGICRETSTATE_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600515#define OMAP4430_LOGICRETSTATE_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700516
517/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600518 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
519 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
520 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700521 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700522#define OMAP4430_LOGICSTATEST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600523#define OMAP4430_LOGICSTATEST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700524
525/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600526 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700527 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
528 * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
529 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
Rajendra Nayak568997c2010-09-27 14:02:55 -0600530 * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
531 * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
532 * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
533 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
534 * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
535 * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
536 * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
537 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
538 * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
539 * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
540 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
541 * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
542 * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
543 * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
544 * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
545 * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
546 * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
547 * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
548 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
549 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
550 * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
551 * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
552 * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
553 * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
554 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
555 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
556 * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
557 * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
558 * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
559 * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700560 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700561#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600562#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700563
564/*
565 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
Rajendra Nayak568997c2010-09-27 14:02:55 -0600566 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
567 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
568 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
569 * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
570 * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700571 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
572 * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
Rajendra Nayak568997c2010-09-27 14:02:55 -0600573 * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
574 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
575 * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
576 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
577 * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
578 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
579 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
580 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
581 * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700582 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700583#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600584#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700585
586/* Used by RM_ABE_AESS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700587#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600588#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700589
590/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700591#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600592#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700593
594/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700595#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600596#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700597
598/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700599#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600600#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700601
602/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700603#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600604#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700605
606/*
607 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
608 * RM_SDMA_SDMA_CONTEXT
609 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700610#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600611#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700612
613/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700614#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600615#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700616
617/* Used by RM_DUCATI_DUCATI_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700618#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600619#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700620
621/* Used by RM_DUCATI_DUCATI_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700622#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600623#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700624
625/* Used by RM_EMU_DEBUGSS_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700626#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600627#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700628
629/* Used by RM_GFX_GFX_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700630#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600631#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700632
633/* Used by RM_IVAHD_IVAHD_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700634#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600635#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700636
637/*
638 * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
639 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
640 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
641 * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
642 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
643 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700644#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600645#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700646
647/* Used by RM_MPU_MPU_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700648#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600649#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700650
651/* Used by RM_MPU_MPU_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700652#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600653#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700654
655/* Used by RM_MPU_MPU_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700656#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600657#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700658
659/*
660 * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
661 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
662 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
663 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700664#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600665#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700666
667/*
668 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
669 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
670 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700671#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600672#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700673
674/*
675 * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
676 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
677 * RM_L4SEC_CRYPTODMA_CONTEXT
678 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700679#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600680#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700681
682/* Used by RM_IVAHD_SL2_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700683#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600684#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700685
686/* Used by RM_IVAHD_IVAHD_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700687#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600688#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700689
690/* Used by RM_IVAHD_IVAHD_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700691#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600692#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700693
694/* Used by RM_TESLA_TESLA_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700695#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600696#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700697
698/* Used by RM_TESLA_TESLA_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700699#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600700#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700701
702/* Used by RM_TESLA_TESLA_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700703#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600704#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700705
706/* Used by RM_WKUP_SARRAM_CONTEXT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700707#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600708#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700709
710/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600711 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
712 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
713 * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700714 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700715#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600716#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700717
718/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700719#define OMAP4430_MODEM_READY_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600720#define OMAP4430_MODEM_READY_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700721
722/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700723#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600724#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700725
726/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700727#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600728#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700729
730/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700731#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600732#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700733
734/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700735#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600736#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700737
738/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700739#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600740#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700741
742/* Used by PM_MPU_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700743#define OMAP4430_MPU_L1_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600744#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700745
746/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700747#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600748#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700749
750/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700751#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600752#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700753
754/* Used by PM_MPU_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700755#define OMAP4430_MPU_L2_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600756#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700757
758/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700759#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600760#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700761
762/* Used by PM_MPU_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700763#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600764#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700765
766/* Used by PM_MPU_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700767#define OMAP4430_MPU_RAM_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600768#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700769
770/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700771#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600772#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700773
774/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700775#define OMAP4430_MPU_WDT_RST_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600776#define OMAP4430_MPU_WDT_RST_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700777
778/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700779#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600780#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700781
782/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700783#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600784#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700785
786/* Used by PM_L4PER_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700787#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -0600788#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700789
790/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700791#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600792#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700793
794/* Used by PM_CORE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700795#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600796#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700797
798/* Used by PM_CORE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700799#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -0600800#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700801
802/*
803 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
804 * PRM_VC_VAL_CMD_VDD_MPU_L
805 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700806#define OMAP4430_OFF_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600807#define OMAP4430_OFF_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700808
809/*
810 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
811 * PRM_VC_VAL_CMD_VDD_MPU_L
812 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700813#define OMAP4430_ON_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600814#define OMAP4430_ON_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700815
816/*
817 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
818 * PRM_VC_VAL_CMD_VDD_MPU_L
819 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700820#define OMAP4430_ONLP_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600821#define OMAP4430_ONLP_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700822
823/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700824#define OMAP4430_OPP_CHANGE_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600825#define OMAP4430_OPP_CHANGE_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700826
827/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700828#define OMAP4430_OPP_SEL_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600829#define OMAP4430_OPP_SEL_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700830
831/* Used by PRM_SRAM_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700832#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600833#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700834
835/* Used by PRM_PSCON_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700836#define OMAP4430_PCHARGE_TIME_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600837#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700838
839/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700840#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600841#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700842
843/* Used by PM_ABE_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700844#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600845#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700846
847/* Used by PM_ABE_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700848#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600849#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700850
851/* Used by PRM_PHASE1_CNDP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700852#define OMAP4430_PHASE1_CNDP_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600853#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700854
855/* Used by PRM_PHASE2A_CNDP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700856#define OMAP4430_PHASE2A_CNDP_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600857#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700858
859/* Used by PRM_PHASE2B_CNDP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700860#define OMAP4430_PHASE2B_CNDP_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600861#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700862
863/* Used by PRM_PSCON_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700864#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600865#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700866
867/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600868 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
869 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
870 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
871 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700872 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700873#define OMAP4430_POWERSTATE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600874#define OMAP4430_POWERSTATE_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700875
876/*
Rajendra Nayak568997c2010-09-27 14:02:55 -0600877 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
878 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
879 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700880 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700881#define OMAP4430_POWERSTATEST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600882#define OMAP4430_POWERSTATEST_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700883
884/* Used by PRM_PWRREQCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700885#define OMAP4430_PWRREQ_COND_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600886#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700887
888/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700889#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -0600890#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700891
892/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700893#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -0600894#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700895
896/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700897#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -0600898#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700899
900/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700901#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -0600902#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700903
904/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700905#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -0600906#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700907
908/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700909#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -0600910#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700911
912/*
913 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
914 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
915 * PRM_VOLTSETUP_MPU_RET_SLEEP
916 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700917#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600918#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700919
920/*
921 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
922 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
923 * PRM_VOLTSETUP_MPU_RET_SLEEP
924 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700925#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -0600926#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700927
928/*
929 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
930 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
931 * PRM_VOLTSETUP_MPU_RET_SLEEP
932 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700933#define OMAP4430_RAMP_UP_COUNT_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600934#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700935
936/*
937 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
938 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
939 * PRM_VOLTSETUP_MPU_RET_SLEEP
940 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700941#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600942#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700943
944/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700945#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600946#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700947
948/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700949#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -0600950#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700951
952/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700953#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -0600954#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700955
956/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700957#define OMAP4430_REGADDR_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600958#define OMAP4430_REGADDR_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700959
960/*
961 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
962 * PRM_VC_VAL_CMD_VDD_MPU_L
963 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700964#define OMAP4430_RET_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600965#define OMAP4430_RET_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700966
967/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700968#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -0600969#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700970
971/* Used by PM_L4PER_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700972#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -0600973#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700974
975/* Used by PM_L4PER_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700976#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -0600977#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700978
979/*
980 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
981 * PRM_LDO_SRAM_MPU_CTRL
982 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700983#define OMAP4430_RETMODE_ENABLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600984#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700985
Rajendra Nayak568997c2010-09-27 14:02:55 -0600986/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700987#define OMAP4430_RST1_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600988#define OMAP4430_RST1_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700989
Rajendra Nayak568997c2010-09-27 14:02:55 -0600990/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700991#define OMAP4430_RST1ST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -0600992#define OMAP4430_RST1ST_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700993
Rajendra Nayak568997c2010-09-27 14:02:55 -0600994/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700995#define OMAP4430_RST2_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -0600996#define OMAP4430_RST2_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -0700997
Rajendra Nayak568997c2010-09-27 14:02:55 -0600998/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -0700999#define OMAP4430_RST2ST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001000#define OMAP4430_RST2ST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001001
1002/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001003#define OMAP4430_RST3_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001004#define OMAP4430_RST3_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001005
1006/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001007#define OMAP4430_RST3ST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001008#define OMAP4430_RST3ST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001009
1010/* Used by PRM_RSTTIME */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001011#define OMAP4430_RSTTIME1_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001012#define OMAP4430_RSTTIME1_MASK (0x3ff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001013
1014/* Used by PRM_RSTTIME */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001015#define OMAP4430_RSTTIME2_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -06001016#define OMAP4430_RSTTIME2_MASK (0x1f << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001017
1018/* Used by PRM_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001019#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001020#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001021
1022/* Used by PRM_RSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001023#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001024#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0)
1025
1026/* Used by REVISION_PRM */
1027#define OMAP4430_R_RTL_SHIFT 11
1028#define OMAP4430_R_RTL_MASK (0x1f << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001029
1030/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001031#define OMAP4430_SA_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001032#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001033
1034/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001035#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001036#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001037
1038/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001039#define OMAP4430_SA_VDD_IVA_L_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001040#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001041
1042/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001043#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001044#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001045
1046/* Used by PRM_VC_CFG_CHANNEL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001047#define OMAP4430_SA_VDD_MPU_L_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001048#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001049
1050/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001051#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001052#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16)
1053
1054/* Used by REVISION_PRM */
1055#define OMAP4430_SCHEME_SHIFT 30
1056#define OMAP4430_SCHEME_MASK (0x3 << 30)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001057
1058/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001059#define OMAP4430_SCLH_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001060#define OMAP4430_SCLH_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001061
1062/* Used by PRM_VC_CFG_I2C_CLK */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001063#define OMAP4430_SCLL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001064#define OMAP4430_SCLL_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001065
1066/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001067#define OMAP4430_SECURE_WDT_RST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -06001068#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001069
1070/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001071#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -06001072#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001073
1074/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001075#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -06001076#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001077
1078/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001079#define OMAP4430_SL2_MEM_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001080#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001081
1082/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001083#define OMAP4430_SLAVEADDR_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001084#define OMAP4430_SLAVEADDR_MASK (0x7f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001085
1086/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001087#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001088#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001089
1090/* Used by PRM_SRAM_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001091#define OMAP4430_SLPCNT_VALUE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001092#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001093
1094/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001095#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001096#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001097
1098/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001099#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001100#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
1101
1102/* Used by PRM_VC_ERRST */
1103#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1
1104#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1)
1105
1106/* Used by PRM_VC_ERRST */
1107#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9
1108#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9)
1109
1110/* Used by PRM_VC_ERRST */
1111#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17
1112#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17)
1113
1114/* Used by PRM_VC_ERRST */
1115#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0
1116#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0)
1117
1118/* Used by PRM_VC_ERRST */
1119#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8
1120#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8)
1121
1122/* Used by PRM_VC_ERRST */
1123#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16
1124#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16)
1125
1126/* Used by PRM_VC_ERRST */
1127#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
1128#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
1129
1130/* Used by PRM_VC_ERRST */
1131#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10
1132#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10)
1133
1134/* Used by PRM_VC_ERRST */
1135#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18
1136#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001137
1138/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001139#define OMAP4430_SR2EN_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001140#define OMAP4430_SR2EN_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001141
1142/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001143#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001144#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001145
1146/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001147#define OMAP4430_SR2_STATUS_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001148#define OMAP4430_SR2_STATUS_MASK (0x3 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001149
1150/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001151#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001152#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001153
1154/*
1155 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1156 * PRM_LDO_SRAM_MPU_CTRL
1157 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001158#define OMAP4430_SRAMLDO_STATUS_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001159#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001160
1161/*
1162 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1163 * PRM_LDO_SRAM_MPU_CTRL
1164 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001165#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -06001166#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001167
1168/* Used by PRM_VC_CFG_I2C_MODE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001169#define OMAP4430_SRMODEEN_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -06001170#define OMAP4430_SRMODEEN_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001171
1172/* Used by PRM_VOLTSETUP_WARMRESET */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001173#define OMAP4430_STABLE_COUNT_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001174#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001175
1176/* Used by PRM_VOLTSETUP_WARMRESET */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001177#define OMAP4430_STABLE_PRESCAL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001178#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8)
1179
1180/* Used by PRM_LDO_BANDGAP_SETUP */
1181#define OMAP4430_STARTUP_COUNT_SHIFT 0
1182#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0)
1183
1184/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1185#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24
1186#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001187
1188/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001189#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -06001190#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001191
1192/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001193#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -06001194#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001195
1196/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001197#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001198#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001199
1200/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001201#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22
Rajendra Nayak568997c2010-09-27 14:02:55 -06001202#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001203
1204/* Used by PM_IVAHD_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001205#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -06001206#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001207
1208/* Used by PM_IVAHD_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001209#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -06001210#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001211
1212/* Used by RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001213#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001214#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001215
1216/* Used by RM_TESLA_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001217#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001218#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001219
1220/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001221#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -06001222#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001223
1224/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001225#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -06001226#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001227
1228/* Used by PM_TESLA_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001229#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001230#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001231
1232/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001233#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001234#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001235
1236/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001237#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001238#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001239
1240/* Used by PM_TESLA_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001241#define OMAP4430_TESLA_L1_STATEST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -06001242#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001243
1244/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001245#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -06001246#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001247
1248/* Used by PM_TESLA_PWRSTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001249#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -06001250#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001251
1252/* Used by PM_TESLA_PWRSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001253#define OMAP4430_TESLA_L2_STATEST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001254#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001255
1256/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001257#define OMAP4430_TIMEOUT_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001258#define OMAP4430_TIMEOUT_MASK (0xffff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001259
1260/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001261#define OMAP4430_TIMEOUTEN_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001262#define OMAP4430_TIMEOUTEN_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001263
1264/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001265#define OMAP4430_TRANSITION_EN_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001266#define OMAP4430_TRANSITION_EN_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001267
1268/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001269#define OMAP4430_TRANSITION_ST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001270#define OMAP4430_TRANSITION_ST_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001271
1272/* Used by PRM_VC_VAL_BYPASS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001273#define OMAP4430_VALID_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -06001274#define OMAP4430_VALID_MASK (1 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001275
1276/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001277#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -06001278#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001279
1280/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001281#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -06001282#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14)
1283
1284/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1285#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22
1286#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22)
1287
1288/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1289#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22
1290#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001291
1292/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001293#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30
Rajendra Nayak568997c2010-09-27 14:02:55 -06001294#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001295
1296/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001297#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30
Rajendra Nayak568997c2010-09-27 14:02:55 -06001298#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001299
1300/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001301#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001302#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001303
1304/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001305#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001306#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001307
1308/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001309#define OMAP4430_VC_RAERR_EN_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -06001310#define OMAP4430_VC_RAERR_EN_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001311
1312/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001313#define OMAP4430_VC_RAERR_ST_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -06001314#define OMAP4430_VC_RAERR_ST_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001315
1316/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001317#define OMAP4430_VC_SAERR_EN_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -06001318#define OMAP4430_VC_SAERR_EN_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001319
1320/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001321#define OMAP4430_VC_SAERR_ST_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -06001322#define OMAP4430_VC_SAERR_ST_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001323
1324/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001325#define OMAP4430_VC_TOERR_EN_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -06001326#define OMAP4430_VC_TOERR_EN_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001327
1328/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001329#define OMAP4430_VC_TOERR_ST_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -06001330#define OMAP4430_VC_TOERR_ST_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001331
1332/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001333#define OMAP4430_VDDMAX_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -06001334#define OMAP4430_VDDMAX_MASK (0xff << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001335
1336/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001337#define OMAP4430_VDDMIN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001338#define OMAP4430_VDDMIN_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001339
1340/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001341#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -06001342#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001343
1344/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001345#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001346#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001347
1348/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001349#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -06001350#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001351
1352/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001353#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -06001354#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001355
1356/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001357#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001358#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001359
1360/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001361#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -06001362#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001363
1364/* Used by PRM_VOLTCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001365#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001366#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001367
1368/* Used by PRM_RSTST */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001369#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001370#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
1371
1372/* Used by PRM_VC_ERRST */
1373#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4
1374#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4)
1375
1376/* Used by PRM_VC_ERRST */
1377#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12
1378#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12)
1379
1380/* Used by PRM_VC_ERRST */
1381#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20
1382#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20)
1383
1384/* Used by PRM_VC_ERRST */
1385#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3
1386#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3)
1387
1388/* Used by PRM_VC_ERRST */
1389#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11
1390#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11)
1391
1392/* Used by PRM_VC_ERRST */
1393#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19
1394#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19)
1395
1396/* Used by PRM_VC_ERRST */
1397#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
1398#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
1399
1400/* Used by PRM_VC_ERRST */
1401#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13
1402#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13)
1403
1404/* Used by PRM_VC_ERRST */
1405#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21
1406#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001407
1408/* Used by PRM_VC_VAL_SMPS_RA_VOL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001409#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001410#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001411
1412/* Used by PRM_VC_VAL_SMPS_RA_VOL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001413#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001414#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001415
1416/* Used by PRM_VC_VAL_SMPS_RA_VOL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001417#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001418#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001419
1420/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001421#define OMAP4430_VPENABLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001422#define OMAP4430_VPENABLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001423
1424/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001425#define OMAP4430_VPINIDLE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001426#define OMAP4430_VPINIDLE_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001427
1428/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001429#define OMAP4430_VPVOLTAGE_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001430#define OMAP4430_VPVOLTAGE_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001431
1432/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001433#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -06001434#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001435
1436/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001437#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20
Rajendra Nayak568997c2010-09-27 14:02:55 -06001438#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001439
1440/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001441#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -06001442#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001443
1444/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001445#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18
Rajendra Nayak568997c2010-09-27 14:02:55 -06001446#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001447
1448/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001449#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17
Rajendra Nayak568997c2010-09-27 14:02:55 -06001450#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001451
1452/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001453#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17
Rajendra Nayak568997c2010-09-27 14:02:55 -06001454#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001455
1456/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001457#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -06001458#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001459
1460/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001461#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -06001462#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001463
1464/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001465#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001466#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001467
1468/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001469#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
Rajendra Nayak568997c2010-09-27 14:02:55 -06001470#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001471
1472/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001473#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21
Rajendra Nayak568997c2010-09-27 14:02:55 -06001474#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001475
1476/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001477#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21
Rajendra Nayak568997c2010-09-27 14:02:55 -06001478#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001479
1480/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001481#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28
Rajendra Nayak568997c2010-09-27 14:02:55 -06001482#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001483
1484/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001485#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28
Rajendra Nayak568997c2010-09-27 14:02:55 -06001486#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001487
1488/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001489#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26
Rajendra Nayak568997c2010-09-27 14:02:55 -06001490#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001491
1492/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001493#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26
Rajendra Nayak568997c2010-09-27 14:02:55 -06001494#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001495
1496/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001497#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25
Rajendra Nayak568997c2010-09-27 14:02:55 -06001498#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001499
1500/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001501#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25
Rajendra Nayak568997c2010-09-27 14:02:55 -06001502#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001503
1504/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001505#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27
Rajendra Nayak568997c2010-09-27 14:02:55 -06001506#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001507
1508/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001509#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27
Rajendra Nayak568997c2010-09-27 14:02:55 -06001510#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001511
1512/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001513#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -06001514#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001515
1516/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001517#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24
Rajendra Nayak568997c2010-09-27 14:02:55 -06001518#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001519
1520/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001521#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29
Rajendra Nayak568997c2010-09-27 14:02:55 -06001522#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001523
1524/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001525#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29
Rajendra Nayak568997c2010-09-27 14:02:55 -06001526#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001527
1528/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001529#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -06001530#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001531
1532/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001533#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -06001534#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001535
1536/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001537#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001538#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001539
1540/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001541#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001542#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001543
1544/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001545#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001546#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001547
1548/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001549#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001550#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001551
1552/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001553#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001554#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001555
1556/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001557#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001558#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001559
1560/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001561#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001562#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001563
1564/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001565#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001566#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001567
1568/* Used by PRM_IRQENABLE_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001569#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -06001570#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001571
1572/* Used by PRM_IRQSTATUS_MPU_2 */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001573#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -06001574#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001575
1576/* Used by PRM_SRAM_COUNT */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001577#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001578#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001579
1580/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001581#define OMAP4430_VSTEPMAX_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001582#define OMAP4430_VSTEPMAX_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001583
1584/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001585#define OMAP4430_VSTEPMIN_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001586#define OMAP4430_VSTEPMIN_MASK (0xff << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001587
1588/* Used by PRM_MODEM_IF_CTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001589#define OMAP4430_WAKE_MODEM_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001590#define OMAP4430_WAKE_MODEM_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001591
1592/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001593#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001594#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001595
1596/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001597#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001598#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001599
1600/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001601#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001602#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001603
1604/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001605#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001606#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001607
1608/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001609#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001610#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001611
1612/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001613#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001614#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001615
1616/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001617#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001618#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001619
1620/* Used by PM_ABE_DMIC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001621#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001622#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001623
1624/* Used by PM_L4PER_DMTIMER10_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001625#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001626#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001627
1628/* Used by PM_L4PER_DMTIMER11_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001629#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001630#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001631
1632/* Used by PM_L4PER_DMTIMER11_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001633#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001634#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001635
1636/* Used by PM_L4PER_DMTIMER2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001637#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001638#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001639
1640/* Used by PM_L4PER_DMTIMER3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001641#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001642#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001643
1644/* Used by PM_L4PER_DMTIMER3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001645#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001646#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001647
1648/* Used by PM_L4PER_DMTIMER4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001649#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001650#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001651
1652/* Used by PM_L4PER_DMTIMER4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001653#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001654#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001655
1656/* Used by PM_L4PER_DMTIMER9_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001657#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001658#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001659
1660/* Used by PM_L4PER_DMTIMER9_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001661#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001662#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001663
1664/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001665#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5
Rajendra Nayak568997c2010-09-27 14:02:55 -06001666#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001667
1668/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001669#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4
Rajendra Nayak568997c2010-09-27 14:02:55 -06001670#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001671
1672/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001673#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001674#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001675
1676/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001677#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001678#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001679
1680/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001681#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -06001682#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001683
1684/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001685#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06001686#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001687
1688/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001689#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11
Rajendra Nayak568997c2010-09-27 14:02:55 -06001690#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001691
1692/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001693#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10
Rajendra Nayak568997c2010-09-27 14:02:55 -06001694#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001695
1696/* Used by PM_WKUP_GPIO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001697#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001698#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001699
1700/* Used by PM_WKUP_GPIO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001701#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001702#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001703
1704/* Used by PM_WKUP_GPIO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001705#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001706#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001707
1708/* Used by PM_L4PER_GPIO2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001709#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001710#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001711
1712/* Used by PM_L4PER_GPIO2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001713#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001714#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001715
1716/* Used by PM_L4PER_GPIO2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001717#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001718#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001719
1720/* Used by PM_L4PER_GPIO3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001721#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001722#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001723
1724/* Used by PM_L4PER_GPIO3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001725#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001726#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001727
1728/* Used by PM_L4PER_GPIO4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001729#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001730#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001731
1732/* Used by PM_L4PER_GPIO4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001733#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001734#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001735
1736/* Used by PM_L4PER_GPIO5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001737#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001738#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001739
1740/* Used by PM_L4PER_GPIO5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001741#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001742#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001743
1744/* Used by PM_L4PER_GPIO6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001745#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001746#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001747
1748/* Used by PM_L4PER_GPIO6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001749#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001750#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001751
1752/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001753#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
Rajendra Nayak568997c2010-09-27 14:02:55 -06001754#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001755
1756/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001757#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13
Rajendra Nayak568997c2010-09-27 14:02:55 -06001758#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001759
1760/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001761#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
Rajendra Nayak568997c2010-09-27 14:02:55 -06001762#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001763
1764/* Used by PM_DSS_DSS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001765#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14
Rajendra Nayak568997c2010-09-27 14:02:55 -06001766#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001767
1768/* Used by PM_L4PER_HECC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001769#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001770#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001771
1772/* Used by PM_L4PER_HECC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001773#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001774#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001775
1776/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001777#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001778#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001779
1780/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001781#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001782#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001783
1784/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001785#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001786#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001787
1788/* Used by PM_L4PER_I2C1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001789#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001790#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001791
1792/* Used by PM_L4PER_I2C1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001793#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001794#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001795
1796/* Used by PM_L4PER_I2C1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001797#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001798#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001799
1800/* Used by PM_L4PER_I2C2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001801#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001802#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001803
1804/* Used by PM_L4PER_I2C2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001805#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001806#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001807
1808/* Used by PM_L4PER_I2C2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001809#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001810#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001811
1812/* Used by PM_L4PER_I2C3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001813#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001814#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001815
1816/* Used by PM_L4PER_I2C3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001817#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001818#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001819
1820/* Used by PM_L4PER_I2C3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001821#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001822#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001823
1824/* Used by PM_L4PER_I2C4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001825#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001826#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001827
1828/* Used by PM_L4PER_I2C4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001829#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001830#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001831
1832/* Used by PM_L4PER_I2C4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001833#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001834#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001835
1836/* Used by PM_L4PER_I2C5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001837#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001838#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001839
1840/* Used by PM_L4PER_I2C5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001841#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001842#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001843
1844/* Used by PM_WKUP_KEYBOARD_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001845#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001846#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001847
1848/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001849#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001850#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001851
1852/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001853#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001854#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001855
1856/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001857#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001858#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001859
1860/* Used by PM_ABE_MCASP_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001861#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001862#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001863
1864/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001865#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001866#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001867
1868/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001869#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001870#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001871
1872/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001873#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001874#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001875
1876/* Used by PM_L4PER_MCASP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001877#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001878#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001879
1880/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001881#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06001882#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001883
1884/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001885#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06001886#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001887
1888/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001889#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001890#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001891
1892/* Used by PM_L4PER_MCASP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001893#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001894#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001895
1896/* Used by PM_ABE_MCBSP1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001897#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001898#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001899
1900/* Used by PM_ABE_MCBSP1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001901#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001902#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001903
1904/* Used by PM_ABE_MCBSP1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001905#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001906#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001907
1908/* Used by PM_ABE_MCBSP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001909#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001910#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001911
1912/* Used by PM_ABE_MCBSP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001913#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001914#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001915
1916/* Used by PM_ABE_MCBSP2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001917#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001918#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001919
1920/* Used by PM_ABE_MCBSP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001921#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001922#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001923
1924/* Used by PM_ABE_MCBSP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001925#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001926#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001927
1928/* Used by PM_ABE_MCBSP3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001929#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001930#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001931
1932/* Used by PM_L4PER_MCBSP4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001933#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001934#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001935
1936/* Used by PM_L4PER_MCBSP4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001937#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001938#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001939
1940/* Used by PM_L4PER_MCBSP4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001941#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001942#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001943
1944/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001945#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001946#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001947
1948/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001949#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001950#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001951
1952/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001953#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001954#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001955
1956/* Used by PM_L4PER_MCSPI1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001957#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06001958#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001959
1960/* Used by PM_L4PER_MCSPI2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001961#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001962#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001963
1964/* Used by PM_L4PER_MCSPI2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001965#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001966#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001967
1968/* Used by PM_L4PER_MCSPI2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001969#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001970#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001971
1972/* Used by PM_L4PER_MCSPI3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001973#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001974#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001975
1976/* Used by PM_L4PER_MCSPI3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001977#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001978#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001979
1980/* Used by PM_L4PER_MCSPI4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001981#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001982#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001983
1984/* Used by PM_L4PER_MCSPI4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001985#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001986#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001987
1988/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001989#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06001990#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001991
1992/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001993#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06001994#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001995
1996/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07001997#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06001998#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07001999
2000/* Used by PM_L3INIT_MMC1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002001#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002002#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002003
2004/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002005#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002006#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002007
2008/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002009#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002010#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002011
2012/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002013#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002014#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002015
2016/* Used by PM_L3INIT_MMC2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002017#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002018#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002019
2020/* Used by PM_L3INIT_MMC6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002021#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002022#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002023
2024/* Used by PM_L3INIT_MMC6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002025#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002026#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002027
2028/* Used by PM_L3INIT_MMC6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002029#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002030#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002031
2032/* Used by PM_L4PER_MMCSD3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002033#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002034#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002035
2036/* Used by PM_L4PER_MMCSD3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002037#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002038#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002039
2040/* Used by PM_L4PER_MMCSD3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002041#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002042#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002043
2044/* Used by PM_L4PER_MMCSD4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002045#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002046#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002047
2048/* Used by PM_L4PER_MMCSD4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002049#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002050#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002051
2052/* Used by PM_L4PER_MMCSD4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002053#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002054#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002055
2056/* Used by PM_L4PER_MMCSD5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002057#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002058#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002059
2060/* Used by PM_L4PER_MMCSD5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002061#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002062#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002063
2064/* Used by PM_L4PER_MMCSD5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002065#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002066#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002067
2068/* Used by PM_L3INIT_PCIESS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002069#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002070#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002071
2072/* Used by PM_L3INIT_PCIESS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002073#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002074#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002075
2076/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002077#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06002078#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002079
2080/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002081#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06002082#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002083
2084/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002085#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002086#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002087
2088/* Used by PM_ABE_PDM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002089#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002090#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002091
2092/* Used by PM_WKUP_RTC_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002093#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002094#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002095
2096/* Used by PM_L3INIT_SATA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002097#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002098#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002099
2100/* Used by PM_L3INIT_SATA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002101#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002102#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002103
2104/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002105#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06002106#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002107
2108/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002109#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06002110#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002111
2112/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002113#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002114#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002115
2116/* Used by PM_ABE_SLIMBUS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002117#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002118#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002119
2120/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002121#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7
Rajendra Nayak568997c2010-09-27 14:02:55 -06002122#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002123
2124/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002125#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6
Rajendra Nayak568997c2010-09-27 14:02:55 -06002126#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002127
2128/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002129#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002130#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002131
2132/* Used by PM_L4PER_SLIMBUS2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002133#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002134#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002135
2136/* Used by PM_ALWON_SR_CORE_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002137#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002138#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002139
2140/* Used by PM_ALWON_SR_CORE_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002141#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002142#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002143
2144/* Used by PM_ALWON_SR_IVA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002145#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002146#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002147
2148/* Used by PM_ALWON_SR_IVA_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002149#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002150#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002151
2152/* Used by PM_ALWON_SR_MPU_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002153#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002154#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002155
2156/* Used by PM_WKUP_TIMER12_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002157#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002158#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002159
2160/* Used by PM_WKUP_TIMER1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002161#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002162#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002163
2164/* Used by PM_ABE_TIMER5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002165#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002166#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002167
2168/* Used by PM_ABE_TIMER5_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002169#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002170#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002171
2172/* Used by PM_ABE_TIMER6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002173#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002174#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002175
2176/* Used by PM_ABE_TIMER6_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002177#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002178#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002179
2180/* Used by PM_ABE_TIMER7_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002181#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002182#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002183
2184/* Used by PM_ABE_TIMER7_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002185#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002186#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002187
2188/* Used by PM_ABE_TIMER8_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002189#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002190#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002191
2192/* Used by PM_ABE_TIMER8_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002193#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002194#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002195
2196/* Used by PM_L4PER_UART1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002197#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002198#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002199
2200/* Used by PM_L4PER_UART1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002201#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002202#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002203
2204/* Used by PM_L4PER_UART2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002205#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002206#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002207
2208/* Used by PM_L4PER_UART2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002209#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002210#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002211
2212/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002213#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002214#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002215
2216/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002217#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002218#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002219
2220/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002221#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002222#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002223
2224/* Used by PM_L4PER_UART3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002225#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2
Rajendra Nayak568997c2010-09-27 14:02:55 -06002226#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002227
2228/* Used by PM_L4PER_UART4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002229#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002230#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002231
2232/* Used by PM_L4PER_UART4_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002233#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002234#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002235
2236/* Used by PM_L3INIT_UNIPRO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002237#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002238#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002239
2240/* Used by PM_L3INIT_UNIPRO1_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002241#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002242#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002243
2244/* Used by PM_L3INIT_USB_HOST_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002245#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002246#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002247
2248/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002249#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002250#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002251
2252/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002253#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002254#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002255
2256/* Used by PM_L3INIT_USB_HOST_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002257#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002258#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002259
2260/* Used by PM_L3INIT_USB_OTG_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002261#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002262#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002263
2264/* Used by PM_L3INIT_USB_OTG_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002265#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002266#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002267
2268/* Used by PM_L3INIT_USB_TLL_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002269#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002270#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002271
2272/* Used by PM_L3INIT_USB_TLL_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002273#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002274#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002275
2276/* Used by PM_WKUP_USIM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002277#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002278#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002279
2280/* Used by PM_WKUP_USIM_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002281#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3
Rajendra Nayak568997c2010-09-27 14:02:55 -06002282#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002283
2284/* Used by PM_WKUP_WDT2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002285#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002286#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002287
2288/* Used by PM_WKUP_WDT2_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002289#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002290#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002291
2292/* Used by PM_ABE_WDT3_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002293#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0
Rajendra Nayak568997c2010-09-27 14:02:55 -06002294#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002295
2296/* Used by PM_L3INIT_HSI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002297#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06002298#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002299
2300/* Used by PM_L3INIT_XHPI_WKDEP */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002301#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1
Rajendra Nayak568997c2010-09-27 14:02:55 -06002302#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002303
2304/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002305#define OMAP4430_WUCLK_CTRL_SHIFT 8
Rajendra Nayak568997c2010-09-27 14:02:55 -06002306#define OMAP4430_WUCLK_CTRL_MASK (1 << 8)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002307
2308/* Used by PRM_IO_PMCTRL */
Rajendra Nayak56ef28a2010-01-26 20:13:12 -07002309#define OMAP4430_WUCLK_STATUS_SHIFT 9
Rajendra Nayak568997c2010-09-27 14:02:55 -06002310#define OMAP4430_WUCLK_STATUS_MASK (1 << 9)
2311
2312/* Used by REVISION_PRM */
2313#define OMAP4430_X_MAJOR_SHIFT 8
2314#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
2315
2316/* Used by REVISION_PRM */
2317#define OMAP4430_Y_MINOR_SHIFT 0
2318#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
Rajendra Nayak234f0c42009-12-08 18:24:52 -07002319#endif