| Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 1 | * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX |
| 2 | |
| 3 | Required properties: |
| Markus Pargmann | 63edea1 | 2014-02-16 20:10:55 +0100 | [diff] [blame] | 4 | - compatible : Should be one of |
| 5 | "fsl,imx25-sdma" |
| 6 | "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" |
| 7 | "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" |
| 8 | "fsl,imx51-sdma" |
| 9 | "fsl,imx53-sdma" |
| 10 | "fsl,imx6q-sdma" |
| Geert Uytterhoeven | c1e0cff | 2014-03-11 11:23:48 +0100 | [diff] [blame] | 11 | The -to variants should be preferred since they allow to determine the |
| Markus Pargmann | 63edea1 | 2014-02-16 20:10:55 +0100 | [diff] [blame] | 12 | correct ROM script addresses needed for the driver to work without additional |
| 13 | firmware. |
| Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 14 | - reg : Should contain SDMA registers location and length |
| 15 | - interrupts : Should contain SDMA interrupt |
| Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 16 | - #dma-cells : Must be <3>. |
| 17 | The first cell specifies the DMA request/event ID. See details below |
| 18 | about the second and third cell. |
| Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 19 | - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM |
| 20 | scripts firmware |
| 21 | |
| Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 22 | The second cell of dma phandle specifies the peripheral type of DMA transfer. |
| 23 | The full ID of peripheral types can be found below. |
| 24 | |
| 25 | ID transfer type |
| 26 | --------------------- |
| 27 | 0 MCU domain SSI |
| 28 | 1 Shared SSI |
| 29 | 2 MMC |
| 30 | 3 SDHC |
| 31 | 4 MCU domain UART |
| 32 | 5 Shared UART |
| 33 | 6 FIRI |
| 34 | 7 MCU domain CSPI |
| 35 | 8 Shared CSPI |
| 36 | 9 SIM |
| 37 | 10 ATA |
| 38 | 11 CCM |
| 39 | 12 External peripheral |
| 40 | 13 Memory Stick Host Controller |
| 41 | 14 Shared Memory Stick Host Controller |
| 42 | 15 DSP |
| 43 | 16 Memory |
| 44 | 17 FIFO type Memory |
| 45 | 18 SPDIF |
| 46 | 19 IPU Memory |
| 47 | 20 ASRC |
| 48 | 21 ESAI |
| Nicolin Chen | 1a89557 | 2013-11-13 22:55:25 +0800 | [diff] [blame] | 49 | 22 SSI Dual FIFO (needs firmware ver >= 2) |
| Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 50 | |
| 51 | The third cell specifies the transfer priority as below. |
| 52 | |
| 53 | ID transfer priority |
| 54 | ------------------------- |
| 55 | 0 High |
| 56 | 1 Medium |
| 57 | 2 Low |
| 58 | |
| Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 59 | Examples: |
| 60 | |
| 61 | sdma@83fb0000 { |
| 62 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
| 63 | reg = <0x83fb0000 0x4000>; |
| 64 | interrupts = <6>; |
| Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 65 | #dma-cells = <3>; |
| Shawn Guo | 580975d | 2011-07-14 08:35:48 +0800 | [diff] [blame] | 66 | fsl,sdma-ram-script-name = "sdma-imx51.bin"; |
| 67 | }; |
| Shawn Guo | 9479e17 | 2013-05-30 22:23:32 +0800 | [diff] [blame] | 68 | |
| 69 | DMA clients connected to the i.MX SDMA controller must use the format |
| 70 | described in the dma.txt file. |
| 71 | |
| 72 | Examples: |
| 73 | |
| 74 | ssi2: ssi@70014000 { |
| 75 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
| 76 | reg = <0x70014000 0x4000>; |
| 77 | interrupts = <30>; |
| 78 | clocks = <&clks 49>; |
| 79 | dmas = <&sdma 24 1 0>, |
| 80 | <&sdma 25 1 0>; |
| 81 | dma-names = "rx", "tx"; |
| 82 | fsl,fifo-depth = <15>; |
| 83 | }; |