blob: d96e179490ce8a154a3653b69a585f9ded5cd835 [file] [log] [blame]
Stefan Roese7423d2d2012-11-26 15:46:12 +01001/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Maxime Ripard69144e32013-03-13 20:07:37 +010013/include/ "skeleton.dtsi"
Stefan Roese7423d2d2012-11-26 15:46:12 +010014
15/ {
Maxime Ripard69144e32013-03-13 20:07:37 +010016 interrupt-parent = <&intc>;
17
Emilio Lópeze751cce2013-11-16 15:17:29 -030018 aliases {
19 ethernet0 = &emac;
Maxime Ripard10b302a2013-11-17 10:03:04 +010020 serial0 = &uart0;
21 serial1 = &uart1;
Maxime Ripard143b13d2014-01-02 22:05:04 +010022 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 serial6 = &uart6;
27 serial7 = &uart7;
Emilio Lópeze751cce2013-11-16 15:17:29 -030028 };
29
Maxime Ripard69144e32013-03-13 20:07:37 +010030 cpus {
Arnd Bergmann8b2efa892013-06-10 16:48:36 +020031 #address-cells = <1>;
32 #size-cells = <0>;
Maxime Ripard69144e32013-03-13 20:07:37 +010033 cpu@0 {
Lorenzo Pieralisi14c44aa2013-04-18 18:41:57 +010034 device_type = "cpu";
Maxime Ripard69144e32013-03-13 20:07:37 +010035 compatible = "arm,cortex-a8";
Lorenzo Pieralisi14c44aa2013-04-18 18:41:57 +010036 reg = <0x0>;
Maxime Ripard69144e32013-03-13 20:07:37 +010037 };
38 };
39
Stefan Roese7423d2d2012-11-26 15:46:12 +010040 memory {
41 reg = <0x40000000 0x80000000>;
42 };
Maxime Ripard874b4e42013-01-26 15:36:54 +010043
Maxime Ripard69144e32013-03-13 20:07:37 +010044 clocks {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 /*
50 * This is a dummy clock, to be used as placeholder on
51 * other mux clocks when a specific parent clock is not
52 * yet implemented. It should be dropped when the driver
53 * is complete.
54 */
55 dummy: dummy {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <0>;
59 };
60
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080061 osc24M: clk@01c20050 {
Maxime Ripard69144e32013-03-13 20:07:37 +010062 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +010063 compatible = "allwinner,sun4i-a10-osc-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +010064 reg = <0x01c20050 0x4>;
Emilio López92fd6e02013-04-09 10:48:04 -030065 clock-frequency = <24000000>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080066 clock-output-names = "osc24M";
Maxime Ripard69144e32013-03-13 20:07:37 +010067 };
68
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080069 osc32k: clk@0 {
Maxime Ripard69144e32013-03-13 20:07:37 +010070 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080073 clock-output-names = "osc32k";
Maxime Ripard69144e32013-03-13 20:07:37 +010074 };
75
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080076 pll1: clk@01c20000 {
Maxime Ripard69144e32013-03-13 20:07:37 +010077 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +010078 compatible = "allwinner,sun4i-a10-pll1-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +010079 reg = <0x01c20000 0x4>;
80 clocks = <&osc24M>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080081 clock-output-names = "pll1";
Maxime Ripard69144e32013-03-13 20:07:37 +010082 };
83
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080084 pll4: clk@01c20018 {
Emilio Lópezec5589f2013-12-23 00:32:35 -030085 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +010086 compatible = "allwinner,sun4i-a10-pll1-clk";
Emilio Lópezec5589f2013-12-23 00:32:35 -030087 reg = <0x01c20018 0x4>;
88 clocks = <&osc24M>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080089 clock-output-names = "pll4";
Emilio Lópezec5589f2013-12-23 00:32:35 -030090 };
91
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +080092 pll5: clk@01c20020 {
Emilio Lópezc3e5e662013-12-23 00:32:38 -030093 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +010094 compatible = "allwinner,sun4i-a10-pll5-clk";
Emilio Lópezc3e5e662013-12-23 00:32:38 -030095 reg = <0x01c20020 0x4>;
96 clocks = <&osc24M>;
97 clock-output-names = "pll5_ddr", "pll5_other";
98 };
99
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800100 pll6: clk@01c20028 {
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300101 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100102 compatible = "allwinner,sun4i-a10-pll6-clk";
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300103 reg = <0x01c20028 0x4>;
104 clocks = <&osc24M>;
105 clock-output-names = "pll6_sata", "pll6_other", "pll6";
106 };
107
Maxime Ripard69144e32013-03-13 20:07:37 +0100108 /* dummy is 200M */
109 cpu: cpu@01c20054 {
110 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100111 compatible = "allwinner,sun4i-a10-cpu-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800114 clock-output-names = "cpu";
Maxime Ripard69144e32013-03-13 20:07:37 +0100115 };
116
117 axi: axi@01c20054 {
118 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100119 compatible = "allwinner,sun4i-a10-axi-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100120 reg = <0x01c20054 0x4>;
121 clocks = <&cpu>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800122 clock-output-names = "axi";
Maxime Ripard69144e32013-03-13 20:07:37 +0100123 };
124
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800125 axi_gates: clk@01c2005c {
Maxime Ripard69144e32013-03-13 20:07:37 +0100126 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100127 compatible = "allwinner,sun4i-a10-axi-gates-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100128 reg = <0x01c2005c 0x4>;
129 clocks = <&axi>;
130 clock-output-names = "axi_dram";
131 };
132
133 ahb: ahb@01c20054 {
134 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100135 compatible = "allwinner,sun4i-a10-ahb-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100136 reg = <0x01c20054 0x4>;
137 clocks = <&axi>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800138 clock-output-names = "ahb";
Maxime Ripard69144e32013-03-13 20:07:37 +0100139 };
140
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800141 ahb_gates: clk@01c20060 {
Maxime Ripard69144e32013-03-13 20:07:37 +0100142 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100143 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100144 reg = <0x01c20060 0x8>;
145 clocks = <&ahb>;
146 clock-output-names = "ahb_usb0", "ahb_ehci0",
147 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
148 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
149 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
150 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
151 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
152 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
153 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
154 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
155 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
156 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
157 };
158
159 apb0: apb0@01c20054 {
160 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100161 compatible = "allwinner,sun4i-a10-apb0-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100162 reg = <0x01c20054 0x4>;
163 clocks = <&ahb>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800164 clock-output-names = "apb0";
Maxime Ripard69144e32013-03-13 20:07:37 +0100165 };
166
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800167 apb0_gates: clk@01c20068 {
Maxime Ripard69144e32013-03-13 20:07:37 +0100168 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100169 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100170 reg = <0x01c20068 0x4>;
171 clocks = <&apb0>;
172 clock-output-names = "apb0_codec", "apb0_spdif",
173 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
174 "apb0_ir1", "apb0_keypad";
175 };
176
Maxime Ripard69144e32013-03-13 20:07:37 +0100177 apb1_mux: apb1_mux@01c20058 {
178 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100179 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100180 reg = <0x01c20058 0x4>;
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800182 clock-output-names = "apb1_mux";
Maxime Ripard69144e32013-03-13 20:07:37 +0100183 };
184
185 apb1: apb1@01c20058 {
186 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100187 compatible = "allwinner,sun4i-a10-apb1-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100188 reg = <0x01c20058 0x4>;
189 clocks = <&apb1_mux>;
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800190 clock-output-names = "apb1";
Maxime Ripard69144e32013-03-13 20:07:37 +0100191 };
192
Chen-Yu Tsaidfb12c02014-02-03 09:51:41 +0800193 apb1_gates: clk@01c2006c {
Maxime Ripard69144e32013-03-13 20:07:37 +0100194 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100195 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
Maxime Ripard69144e32013-03-13 20:07:37 +0100196 reg = <0x01c2006c 0x4>;
197 clocks = <&apb1>;
198 clock-output-names = "apb1_i2c0", "apb1_i2c1",
199 "apb1_i2c2", "apb1_can", "apb1_scr",
200 "apb1_ps20", "apb1_ps21", "apb1_uart0",
201 "apb1_uart1", "apb1_uart2", "apb1_uart3",
202 "apb1_uart4", "apb1_uart5", "apb1_uart6",
203 "apb1_uart7";
204 };
Emilio López4b756ff2013-12-23 00:32:41 -0300205
206 nand_clk: clk@01c20080 {
207 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100208 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300209 reg = <0x01c20080 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "nand";
212 };
213
214 ms_clk: clk@01c20084 {
215 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100216 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300217 reg = <0x01c20084 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ms";
220 };
221
222 mmc0_clk: clk@01c20088 {
223 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100224 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300225 reg = <0x01c20088 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc0";
228 };
229
230 mmc1_clk: clk@01c2008c {
231 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100232 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300233 reg = <0x01c2008c 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc1";
236 };
237
238 mmc2_clk: clk@01c20090 {
239 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100240 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300241 reg = <0x01c20090 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "mmc2";
244 };
245
246 mmc3_clk: clk@01c20094 {
247 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100248 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300249 reg = <0x01c20094 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "mmc3";
252 };
253
254 ts_clk: clk@01c20098 {
255 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100256 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300257 reg = <0x01c20098 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ts";
260 };
261
262 ss_clk: clk@01c2009c {
263 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100264 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300265 reg = <0x01c2009c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "ss";
268 };
269
270 spi0_clk: clk@01c200a0 {
271 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100272 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300273 reg = <0x01c200a0 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi0";
276 };
277
278 spi1_clk: clk@01c200a4 {
279 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100280 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300281 reg = <0x01c200a4 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "spi1";
284 };
285
286 spi2_clk: clk@01c200a8 {
287 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100288 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300289 reg = <0x01c200a8 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "spi2";
292 };
293
294 pata_clk: clk@01c200ac {
295 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100296 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300297 reg = <0x01c200ac 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "pata";
300 };
301
302 ir0_clk: clk@01c200b0 {
303 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100304 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300305 reg = <0x01c200b0 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "ir0";
308 };
309
310 ir1_clk: clk@01c200b4 {
311 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100312 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300313 reg = <0x01c200b4 0x4>;
314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
315 clock-output-names = "ir1";
316 };
317
Roman Byshko0076c8b2014-02-07 16:21:51 +0100318 usb_clk: clk@01c200cc {
319 #clock-cells = <1>;
320 #reset-cells = <1>;
321 compatible = "allwinner,sun4i-a10-usb-clk";
322 reg = <0x01c200cc 0x4>;
323 clocks = <&pll6 1>;
324 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
325 };
326
Emilio López4b756ff2013-12-23 00:32:41 -0300327 spi3_clk: clk@01c200d4 {
328 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100329 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López4b756ff2013-12-23 00:32:41 -0300330 reg = <0x01c200d4 0x4>;
331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
332 clock-output-names = "spi3";
333 };
Maxime Ripard69144e32013-03-13 20:07:37 +0100334 };
335
Maxime Ripardb74aec12013-08-03 16:07:36 +0200336 soc@01c00000 {
Maxime Ripard69144e32013-03-13 20:07:37 +0100337 compatible = "simple-bus";
338 #address-cells = <1>;
339 #size-cells = <1>;
Maxime Ripard69144e32013-03-13 20:07:37 +0100340 ranges;
341
Maxime Ripard65918e22014-02-22 22:35:55 +0100342 spi0: spi@01c05000 {
343 compatible = "allwinner,sun4i-a10-spi";
344 reg = <0x01c05000 0x1000>;
345 interrupts = <10>;
346 clocks = <&ahb_gates 20>, <&spi0_clk>;
347 clock-names = "ahb", "mod";
348 status = "disabled";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 };
352
353 spi1: spi@01c06000 {
354 compatible = "allwinner,sun4i-a10-spi";
355 reg = <0x01c06000 0x1000>;
356 interrupts = <11>;
357 clocks = <&ahb_gates 21>, <&spi1_clk>;
358 clock-names = "ahb", "mod";
359 status = "disabled";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 };
363
Maxime Riparde38afcb2013-05-30 03:49:23 +0000364 emac: ethernet@01c0b000 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100365 compatible = "allwinner,sun4i-a10-emac";
Maxime Riparde38afcb2013-05-30 03:49:23 +0000366 reg = <0x01c0b000 0x1000>;
367 interrupts = <55>;
368 clocks = <&ahb_gates 17>;
369 status = "disabled";
370 };
371
372 mdio@01c0b080 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100373 compatible = "allwinner,sun4i-a10-mdio";
Maxime Riparde38afcb2013-05-30 03:49:23 +0000374 reg = <0x01c0b080 0x14>;
375 status = "disabled";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 };
379
David Lanzendörferb258b362014-05-02 17:57:18 +0200380 mmc0: mmc@01c0f000 {
381 compatible = "allwinner,sun4i-a10-mmc";
382 reg = <0x01c0f000 0x1000>;
383 clocks = <&ahb_gates 8>, <&mmc0_clk>;
384 clock-names = "ahb", "mmc";
385 interrupts = <32>;
386 status = "disabled";
387 };
388
389 mmc1: mmc@01c10000 {
390 compatible = "allwinner,sun4i-a10-mmc";
391 reg = <0x01c10000 0x1000>;
392 clocks = <&ahb_gates 9>, <&mmc1_clk>;
393 clock-names = "ahb", "mmc";
394 interrupts = <33>;
395 status = "disabled";
396 };
397
398 mmc2: mmc@01c11000 {
399 compatible = "allwinner,sun4i-a10-mmc";
400 reg = <0x01c11000 0x1000>;
401 clocks = <&ahb_gates 10>, <&mmc2_clk>;
402 clock-names = "ahb", "mmc";
403 interrupts = <34>;
404 status = "disabled";
405 };
406
407 mmc3: mmc@01c12000 {
408 compatible = "allwinner,sun4i-a10-mmc";
409 reg = <0x01c12000 0x1000>;
410 clocks = <&ahb_gates 11>, <&mmc3_clk>;
411 clock-names = "ahb", "mmc";
412 interrupts = <35>;
413 status = "disabled";
414 };
415
Roman Byshko6ab1ce22014-03-01 20:26:23 +0100416 usbphy: phy@01c13400 {
417 #phy-cells = <1>;
418 compatible = "allwinner,sun4i-a10-usb-phy";
419 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
420 reg-names = "phy_ctrl", "pmu1", "pmu2";
421 clocks = <&usb_clk 8>;
422 clock-names = "usb_phy";
423 resets = <&usb_clk 1>, <&usb_clk 2>;
424 reset-names = "usb1_reset", "usb2_reset";
425 status = "disabled";
426 };
427
428 ehci0: usb@01c14000 {
429 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
430 reg = <0x01c14000 0x100>;
431 interrupts = <39>;
432 clocks = <&ahb_gates 1>;
433 phys = <&usbphy 1>;
434 phy-names = "usb";
435 status = "disabled";
436 };
437
438 ohci0: usb@01c14400 {
439 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
440 reg = <0x01c14400 0x100>;
441 interrupts = <64>;
442 clocks = <&usb_clk 6>, <&ahb_gates 2>;
443 phys = <&usbphy 1>;
444 phy-names = "usb";
445 status = "disabled";
446 };
447
Maxime Ripard65918e22014-02-22 22:35:55 +0100448 spi2: spi@01c17000 {
449 compatible = "allwinner,sun4i-a10-spi";
450 reg = <0x01c17000 0x1000>;
451 interrupts = <12>;
452 clocks = <&ahb_gates 22>, <&spi2_clk>;
453 clock-names = "ahb", "mod";
454 status = "disabled";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 };
458
Oliver Schinagl248bd1e2014-03-01 20:26:21 +0100459 ahci: sata@01c18000 {
460 compatible = "allwinner,sun4i-a10-ahci";
461 reg = <0x01c18000 0x1000>;
462 interrupts = <56>;
463 clocks = <&pll6 0>, <&ahb_gates 25>;
464 status = "disabled";
465 };
466
Roman Byshko6ab1ce22014-03-01 20:26:23 +0100467 ehci1: usb@01c1c000 {
468 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
469 reg = <0x01c1c000 0x100>;
470 interrupts = <40>;
471 clocks = <&ahb_gates 3>;
472 phys = <&usbphy 2>;
473 phy-names = "usb";
474 status = "disabled";
475 };
476
477 ohci1: usb@01c1c400 {
478 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
479 reg = <0x01c1c400 0x100>;
480 interrupts = <65>;
481 clocks = <&usb_clk 7>, <&ahb_gates 4>;
482 phys = <&usbphy 2>;
483 phy-names = "usb";
484 status = "disabled";
485 };
486
Maxime Ripard65918e22014-02-22 22:35:55 +0100487 spi3: spi@01c1f000 {
488 compatible = "allwinner,sun4i-a10-spi";
489 reg = <0x01c1f000 0x1000>;
490 interrupts = <50>;
491 clocks = <&ahb_gates 23>, <&spi3_clk>;
492 clock-names = "ahb", "mod";
493 status = "disabled";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 };
497
Maxime Ripard69144e32013-03-13 20:07:37 +0100498 intc: interrupt-controller@01c20400 {
Maxime Ripard09504a72014-02-07 21:50:26 +0100499 compatible = "allwinner,sun4i-a10-ic";
Maxime Ripard69144e32013-03-13 20:07:37 +0100500 reg = <0x01c20400 0x400>;
501 interrupt-controller;
502 #interrupt-cells = <1>;
503 };
504
Maxime Riparde10911e2013-01-27 19:26:05 +0100505 pio: pinctrl@01c20800 {
Maxime Ripard874b4e42013-01-26 15:36:54 +0100506 compatible = "allwinner,sun4i-a10-pinctrl";
507 reg = <0x01c20800 0x400>;
Maxime Ripard39138bc2013-04-06 15:00:48 +0200508 interrupts = <28>;
Emilio López36386d62013-03-27 18:20:41 -0300509 clocks = <&apb0_gates 5>;
Maxime Riparde10911e2013-01-27 19:26:05 +0100510 gpio-controller;
Maxime Ripard39138bc2013-04-06 15:00:48 +0200511 interrupt-controller;
Maxime Ripard874b4e42013-01-26 15:36:54 +0100512 #address-cells = <1>;
513 #size-cells = <0>;
Maxime Riparde10911e2013-01-27 19:26:05 +0100514 #gpio-cells = <3>;
Maxime Ripard581981b2013-01-26 15:36:55 +0100515
Alexandre Belloni1d5726e2014-04-28 18:17:10 +0200516 pwm0_pins_a: pwm0@0 {
517 allwinner,pins = "PB2";
518 allwinner,function = "pwm";
519 allwinner,drive = <0>;
520 allwinner,pull = <0>;
521 };
522
523 pwm1_pins_a: pwm1@0 {
524 allwinner,pins = "PI3";
525 allwinner,function = "pwm";
526 allwinner,drive = <0>;
527 allwinner,pull = <0>;
528 };
529
Maxime Ripard581981b2013-01-26 15:36:55 +0100530 uart0_pins_a: uart0@0 {
531 allwinner,pins = "PB22", "PB23";
532 allwinner,function = "uart0";
533 allwinner,drive = <0>;
534 allwinner,pull = <0>;
535 };
536
537 uart0_pins_b: uart0@1 {
538 allwinner,pins = "PF2", "PF4";
539 allwinner,function = "uart0";
540 allwinner,drive = <0>;
541 allwinner,pull = <0>;
542 };
543
544 uart1_pins_a: uart1@0 {
545 allwinner,pins = "PA10", "PA11";
546 allwinner,function = "uart1";
547 allwinner,drive = <0>;
548 allwinner,pull = <0>;
549 };
Maxime Ripard27cce4f2013-03-10 13:44:38 +0100550
551 i2c0_pins_a: i2c0@0 {
552 allwinner,pins = "PB0", "PB1";
553 allwinner,function = "i2c0";
554 allwinner,drive = <0>;
555 allwinner,pull = <0>;
556 };
557
558 i2c1_pins_a: i2c1@0 {
559 allwinner,pins = "PB18", "PB19";
560 allwinner,function = "i2c1";
561 allwinner,drive = <0>;
562 allwinner,pull = <0>;
563 };
564
565 i2c2_pins_a: i2c2@0 {
566 allwinner,pins = "PB20", "PB21";
567 allwinner,function = "i2c2";
568 allwinner,drive = <0>;
569 allwinner,pull = <0>;
570 };
Linus Torvalds496322b2013-07-09 18:24:39 -0700571
Maxime Ripardb21da662013-05-30 03:49:22 +0000572 emac_pins_a: emac0@0 {
573 allwinner,pins = "PA0", "PA1", "PA2",
574 "PA3", "PA4", "PA5", "PA6",
575 "PA7", "PA8", "PA9", "PA10",
576 "PA11", "PA12", "PA13", "PA14",
577 "PA15", "PA16";
578 allwinner,function = "emac";
579 allwinner,drive = <0>;
580 allwinner,pull = <0>;
581 };
Hans de Goedeb5f86a32014-05-02 17:57:19 +0200582
583 mmc0_pins_a: mmc0@0 {
584 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
585 allwinner,function = "mmc0";
586 allwinner,drive = <2>;
587 allwinner,pull = <0>;
588 };
589
590 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
591 allwinner,pins = "PH1";
592 allwinner,function = "gpio_in";
593 allwinner,drive = <0>;
594 allwinner,pull = <1>;
595 };
Maxime Ripard874b4e42013-01-26 15:36:54 +0100596 };
Maxime Ripard89b3c992013-02-20 17:25:03 -0800597
Maxime Ripard69144e32013-03-13 20:07:37 +0100598 timer@01c20c00 {
Maxime Ripardb4f26442014-02-06 10:40:32 +0100599 compatible = "allwinner,sun4i-a10-timer";
Maxime Ripard69144e32013-03-13 20:07:37 +0100600 reg = <0x01c20c00 0x90>;
601 interrupts = <22>;
602 clocks = <&osc24M>;
603 };
604
605 wdt: watchdog@01c20c90 {
Maxime Ripardca5d04d2014-02-07 22:29:26 +0100606 compatible = "allwinner,sun4i-a10-wdt";
Maxime Ripard69144e32013-03-13 20:07:37 +0100607 reg = <0x01c20c90 0x10>;
608 };
609
Carlo Caioneb5d905c2013-10-16 20:30:26 +0200610 rtc: rtc@01c20d00 {
Maxime Ripard5fc4bc82014-04-03 14:50:03 -0700611 compatible = "allwinner,sun4i-a10-rtc";
Carlo Caioneb5d905c2013-10-16 20:30:26 +0200612 reg = <0x01c20d00 0x20>;
613 interrupts = <24>;
614 };
615
Alexandre Belloni4b57a392014-04-28 18:17:11 +0200616 pwm: pwm@01c20e00 {
617 compatible = "allwinner,sun4i-a10-pwm";
618 reg = <0x01c20e00 0xc>;
619 clocks = <&osc24M>;
620 #pwm-cells = <3>;
621 status = "disabled";
622 };
623
Oliver Schinagl2bad9692013-09-03 12:33:28 +0200624 sid: eeprom@01c23800 {
Maxime Ripard043d56e2014-02-07 22:20:40 +0100625 compatible = "allwinner,sun4i-a10-sid";
Oliver Schinagl2bad9692013-09-03 12:33:28 +0200626 reg = <0x01c23800 0x10>;
627 };
628
Hans de Goede57c88392013-12-31 17:20:50 +0100629 rtp: rtp@01c25000 {
Maxime Ripard40dd8f32014-02-02 14:52:40 +0100630 compatible = "allwinner,sun4i-a10-ts";
Hans de Goede57c88392013-12-31 17:20:50 +0100631 reg = <0x01c25000 0x100>;
632 interrupts = <29>;
633 };
634
Maxime Ripard89b3c992013-02-20 17:25:03 -0800635 uart0: serial@01c28000 {
636 compatible = "snps,dw-apb-uart";
637 reg = <0x01c28000 0x400>;
638 interrupts = <1>;
639 reg-shift = <2>;
640 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300641 clocks = <&apb1_gates 16>;
Maxime Ripard89b3c992013-02-20 17:25:03 -0800642 status = "disabled";
643 };
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800644
Maxime Ripard69144e32013-03-13 20:07:37 +0100645 uart1: serial@01c28400 {
646 compatible = "snps,dw-apb-uart";
647 reg = <0x01c28400 0x400>;
648 interrupts = <2>;
649 reg-shift = <2>;
650 reg-io-width = <4>;
651 clocks = <&apb1_gates 17>;
652 status = "disabled";
653 };
654
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800655 uart2: serial@01c28800 {
656 compatible = "snps,dw-apb-uart";
657 reg = <0x01c28800 0x400>;
658 interrupts = <3>;
659 reg-shift = <2>;
660 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300661 clocks = <&apb1_gates 18>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800662 status = "disabled";
663 };
664
Maxime Ripard69144e32013-03-13 20:07:37 +0100665 uart3: serial@01c28c00 {
666 compatible = "snps,dw-apb-uart";
667 reg = <0x01c28c00 0x400>;
668 interrupts = <4>;
669 reg-shift = <2>;
670 reg-io-width = <4>;
671 clocks = <&apb1_gates 19>;
672 status = "disabled";
673 };
674
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800675 uart4: serial@01c29000 {
676 compatible = "snps,dw-apb-uart";
677 reg = <0x01c29000 0x400>;
678 interrupts = <17>;
679 reg-shift = <2>;
680 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300681 clocks = <&apb1_gates 20>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800682 status = "disabled";
683 };
684
685 uart5: serial@01c29400 {
686 compatible = "snps,dw-apb-uart";
687 reg = <0x01c29400 0x400>;
688 interrupts = <18>;
689 reg-shift = <2>;
690 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300691 clocks = <&apb1_gates 21>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800692 status = "disabled";
693 };
694
695 uart6: serial@01c29800 {
696 compatible = "snps,dw-apb-uart";
697 reg = <0x01c29800 0x400>;
698 interrupts = <19>;
699 reg-shift = <2>;
700 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300701 clocks = <&apb1_gates 22>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800702 status = "disabled";
703 };
704
705 uart7: serial@01c29c00 {
706 compatible = "snps,dw-apb-uart";
707 reg = <0x01c29c00 0x400>;
708 interrupts = <20>;
709 reg-shift = <2>;
710 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300711 clocks = <&apb1_gates 23>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800712 status = "disabled";
713 };
Maxime Ripardf1741fd2013-03-10 13:34:36 +0100714
715 i2c0: i2c@01c2ac00 {
Maxime Ripardd2755452014-03-31 14:54:58 +0200716 compatible = "allwinner,sun4i-a10-i2c";
Maxime Ripardf1741fd2013-03-10 13:34:36 +0100717 reg = <0x01c2ac00 0x400>;
718 interrupts = <7>;
719 clocks = <&apb1_gates 0>;
720 clock-frequency = <100000>;
721 status = "disabled";
Hans de Goede60bbe312014-04-13 13:41:03 +0200722 #address-cells = <1>;
723 #size-cells = <0>;
Maxime Ripardf1741fd2013-03-10 13:34:36 +0100724 };
725
726 i2c1: i2c@01c2b000 {
Maxime Ripardd2755452014-03-31 14:54:58 +0200727 compatible = "allwinner,sun4i-a10-i2c";
Maxime Ripardf1741fd2013-03-10 13:34:36 +0100728 reg = <0x01c2b000 0x400>;
729 interrupts = <8>;
730 clocks = <&apb1_gates 1>;
731 clock-frequency = <100000>;
732 status = "disabled";
Hans de Goede60bbe312014-04-13 13:41:03 +0200733 #address-cells = <1>;
734 #size-cells = <0>;
Maxime Ripardf1741fd2013-03-10 13:34:36 +0100735 };
736
737 i2c2: i2c@01c2b400 {
Maxime Ripardd2755452014-03-31 14:54:58 +0200738 compatible = "allwinner,sun4i-a10-i2c";
Maxime Ripardf1741fd2013-03-10 13:34:36 +0100739 reg = <0x01c2b400 0x400>;
740 interrupts = <9>;
741 clocks = <&apb1_gates 2>;
742 clock-frequency = <100000>;
743 status = "disabled";
Hans de Goede60bbe312014-04-13 13:41:03 +0200744 #address-cells = <1>;
745 #size-cells = <0>;
Maxime Ripardf1741fd2013-03-10 13:34:36 +0100746 };
Maxime Ripard874b4e42013-01-26 15:36:54 +0100747 };
Stefan Roese7423d2d2012-11-26 15:46:12 +0100748};